xref: /openbmc/u-boot/include/mmc.h (revision aea02abe)
1 /*
2  * Copyright 2008,2010 Freescale Semiconductor, Inc
3  * Andy Fleming
4  *
5  * Based (loosely) on the Linux code
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef _MMC_H_
11 #define _MMC_H_
12 
13 #include <linux/list.h>
14 #include <linux/compiler.h>
15 #include <part.h>
16 
17 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
18 #define SD_VERSION_SD	(1U << 31)
19 #define MMC_VERSION_MMC	(1U << 30)
20 
21 #define MAKE_SDMMC_VERSION(a, b, c)	\
22 	((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
23 #define MAKE_SD_VERSION(a, b, c)	\
24 	(SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
25 #define MAKE_MMC_VERSION(a, b, c)	\
26 	(MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
27 
28 #define EXTRACT_SDMMC_MAJOR_VERSION(x)	\
29 	(((u32)(x) >> 16) & 0xff)
30 #define EXTRACT_SDMMC_MINOR_VERSION(x)	\
31 	(((u32)(x) >> 8) & 0xff)
32 #define EXTRACT_SDMMC_CHANGE_VERSION(x)	\
33 	((u32)(x) & 0xff)
34 
35 #define SD_VERSION_3		MAKE_SD_VERSION(3, 0, 0)
36 #define SD_VERSION_2		MAKE_SD_VERSION(2, 0, 0)
37 #define SD_VERSION_1_0		MAKE_SD_VERSION(1, 0, 0)
38 #define SD_VERSION_1_10		MAKE_SD_VERSION(1, 10, 0)
39 
40 #define MMC_VERSION_UNKNOWN	MAKE_MMC_VERSION(0, 0, 0)
41 #define MMC_VERSION_1_2		MAKE_MMC_VERSION(1, 2, 0)
42 #define MMC_VERSION_1_4		MAKE_MMC_VERSION(1, 4, 0)
43 #define MMC_VERSION_2_2		MAKE_MMC_VERSION(2, 2, 0)
44 #define MMC_VERSION_3		MAKE_MMC_VERSION(3, 0, 0)
45 #define MMC_VERSION_4		MAKE_MMC_VERSION(4, 0, 0)
46 #define MMC_VERSION_4_1		MAKE_MMC_VERSION(4, 1, 0)
47 #define MMC_VERSION_4_2		MAKE_MMC_VERSION(4, 2, 0)
48 #define MMC_VERSION_4_3		MAKE_MMC_VERSION(4, 3, 0)
49 #define MMC_VERSION_4_41	MAKE_MMC_VERSION(4, 4, 1)
50 #define MMC_VERSION_4_5		MAKE_MMC_VERSION(4, 5, 0)
51 #define MMC_VERSION_5_0		MAKE_MMC_VERSION(5, 0, 0)
52 
53 #define MMC_MODE_HS		(1 << 0)
54 #define MMC_MODE_HS_52MHz	(1 << 1)
55 #define MMC_MODE_4BIT		(1 << 2)
56 #define MMC_MODE_8BIT		(1 << 3)
57 #define MMC_MODE_SPI		(1 << 4)
58 #define MMC_MODE_DDR_52MHz	(1 << 5)
59 
60 #define SD_DATA_4BIT	0x00040000
61 
62 #define IS_SD(x)	((x)->version & SD_VERSION_SD)
63 #define IS_MMC(x)	((x)->version & MMC_VERSION_MMC)
64 
65 #define MMC_DATA_READ		1
66 #define MMC_DATA_WRITE		2
67 
68 #define NO_CARD_ERR		-16 /* No SD/MMC card inserted */
69 #define UNUSABLE_ERR		-17 /* Unusable Card */
70 #define COMM_ERR		-18 /* Communications Error */
71 #define TIMEOUT			-19
72 #define SWITCH_ERR		-20 /* Card reports failure to switch mode */
73 
74 #define MMC_CMD_GO_IDLE_STATE		0
75 #define MMC_CMD_SEND_OP_COND		1
76 #define MMC_CMD_ALL_SEND_CID		2
77 #define MMC_CMD_SET_RELATIVE_ADDR	3
78 #define MMC_CMD_SET_DSR			4
79 #define MMC_CMD_SWITCH			6
80 #define MMC_CMD_SELECT_CARD		7
81 #define MMC_CMD_SEND_EXT_CSD		8
82 #define MMC_CMD_SEND_CSD		9
83 #define MMC_CMD_SEND_CID		10
84 #define MMC_CMD_STOP_TRANSMISSION	12
85 #define MMC_CMD_SEND_STATUS		13
86 #define MMC_CMD_SET_BLOCKLEN		16
87 #define MMC_CMD_READ_SINGLE_BLOCK	17
88 #define MMC_CMD_READ_MULTIPLE_BLOCK	18
89 #define MMC_CMD_SET_BLOCK_COUNT         23
90 #define MMC_CMD_WRITE_SINGLE_BLOCK	24
91 #define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
92 #define MMC_CMD_ERASE_GROUP_START	35
93 #define MMC_CMD_ERASE_GROUP_END		36
94 #define MMC_CMD_ERASE			38
95 #define MMC_CMD_APP_CMD			55
96 #define MMC_CMD_SPI_READ_OCR		58
97 #define MMC_CMD_SPI_CRC_ON_OFF		59
98 #define MMC_CMD_RES_MAN			62
99 
100 #define MMC_CMD62_ARG1			0xefac62ec
101 #define MMC_CMD62_ARG2			0xcbaea7
102 
103 
104 #define SD_CMD_SEND_RELATIVE_ADDR	3
105 #define SD_CMD_SWITCH_FUNC		6
106 #define SD_CMD_SEND_IF_COND		8
107 #define SD_CMD_SWITCH_UHS18V		11
108 
109 #define SD_CMD_APP_SET_BUS_WIDTH	6
110 #define SD_CMD_ERASE_WR_BLK_START	32
111 #define SD_CMD_ERASE_WR_BLK_END		33
112 #define SD_CMD_APP_SEND_OP_COND		41
113 #define SD_CMD_APP_SEND_SCR		51
114 
115 /* SCR definitions in different words */
116 #define SD_HIGHSPEED_BUSY	0x00020000
117 #define SD_HIGHSPEED_SUPPORTED	0x00020000
118 
119 #define OCR_BUSY		0x80000000
120 #define OCR_HCS			0x40000000
121 #define OCR_VOLTAGE_MASK	0x007FFF80
122 #define OCR_ACCESS_MODE		0x60000000
123 
124 #define MMC_ERASE_ARG		0x00000000
125 #define MMC_SECURE_ERASE_ARG	0x80000000
126 #define MMC_TRIM_ARG		0x00000001
127 #define MMC_DISCARD_ARG		0x00000003
128 #define MMC_SECURE_TRIM1_ARG	0x80000001
129 #define MMC_SECURE_TRIM2_ARG	0x80008000
130 
131 #define MMC_STATUS_MASK		(~0x0206BF7F)
132 #define MMC_STATUS_SWITCH_ERROR	(1 << 7)
133 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
134 #define MMC_STATUS_CURR_STATE	(0xf << 9)
135 #define MMC_STATUS_ERROR	(1 << 19)
136 
137 #define MMC_STATE_PRG		(7 << 9)
138 
139 #define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
140 #define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
141 #define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
142 #define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
143 #define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
144 #define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
145 #define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
146 #define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
147 #define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
148 #define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
149 #define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
150 #define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
151 #define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
152 #define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
153 #define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
154 #define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
155 #define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */
156 
157 #define MMC_SWITCH_MODE_CMD_SET		0x00 /* Change the command set */
158 #define MMC_SWITCH_MODE_SET_BITS	0x01 /* Set bits in EXT_CSD byte
159 						addressed by index which are
160 						1 in value field */
161 #define MMC_SWITCH_MODE_CLEAR_BITS	0x02 /* Clear bits in EXT_CSD byte
162 						addressed by index, which are
163 						1 in value field */
164 #define MMC_SWITCH_MODE_WRITE_BYTE	0x03 /* Set target byte to value */
165 
166 #define SD_SWITCH_CHECK		0
167 #define SD_SWITCH_SWITCH	1
168 
169 /*
170  * EXT_CSD fields
171  */
172 #define EXT_CSD_ENH_START_ADDR		136	/* R/W */
173 #define EXT_CSD_ENH_SIZE_MULT		140	/* R/W */
174 #define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
175 #define EXT_CSD_PARTITION_SETTING	155	/* R/W */
176 #define EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
177 #define EXT_CSD_MAX_ENH_SIZE_MULT	157	/* R */
178 #define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
179 #define EXT_CSD_RST_N_FUNCTION		162	/* R/W */
180 #define EXT_CSD_WR_REL_PARAM		166	/* R */
181 #define EXT_CSD_WR_REL_SET		167	/* R/W */
182 #define EXT_CSD_RPMB_MULT		168	/* RO */
183 #define EXT_CSD_ERASE_GROUP_DEF		175	/* R/W */
184 #define EXT_CSD_BOOT_BUS_WIDTH		177
185 #define EXT_CSD_PART_CONF		179	/* R/W */
186 #define EXT_CSD_BUS_WIDTH		183	/* R/W */
187 #define EXT_CSD_HS_TIMING		185	/* R/W */
188 #define EXT_CSD_REV			192	/* RO */
189 #define EXT_CSD_CARD_TYPE		196	/* RO */
190 #define EXT_CSD_SEC_CNT			212	/* RO, 4 bytes */
191 #define EXT_CSD_HC_WP_GRP_SIZE		221	/* RO */
192 #define EXT_CSD_HC_ERASE_GRP_SIZE	224	/* RO */
193 #define EXT_CSD_BOOT_MULT		226	/* RO */
194 
195 /*
196  * EXT_CSD field definitions
197  */
198 
199 #define EXT_CSD_CMD_SET_NORMAL		(1 << 0)
200 #define EXT_CSD_CMD_SET_SECURE		(1 << 1)
201 #define EXT_CSD_CMD_SET_CPSECURE	(1 << 2)
202 
203 #define EXT_CSD_CARD_TYPE_26	(1 << 0)	/* Card can run at 26MHz */
204 #define EXT_CSD_CARD_TYPE_52	(1 << 1)	/* Card can run at 52MHz */
205 #define EXT_CSD_CARD_TYPE_DDR_1_8V	(1 << 2)
206 #define EXT_CSD_CARD_TYPE_DDR_1_2V	(1 << 3)
207 #define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V \
208 					| EXT_CSD_CARD_TYPE_DDR_1_2V)
209 
210 #define EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
211 #define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
212 #define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */
213 #define EXT_CSD_DDR_BUS_WIDTH_4	5	/* Card is in 4 bit DDR mode */
214 #define EXT_CSD_DDR_BUS_WIDTH_8	6	/* Card is in 8 bit DDR mode */
215 
216 #define EXT_CSD_BOOT_ACK_ENABLE			(1 << 6)
217 #define EXT_CSD_BOOT_PARTITION_ENABLE		(1 << 3)
218 #define EXT_CSD_PARTITION_ACCESS_ENABLE		(1 << 0)
219 #define EXT_CSD_PARTITION_ACCESS_DISABLE	(0 << 0)
220 
221 #define EXT_CSD_BOOT_ACK(x)		(x << 6)
222 #define EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
223 #define EXT_CSD_PARTITION_ACCESS(x)	(x << 0)
224 
225 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)	(x << 3)
226 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x)	(x << 2)
227 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x)	(x)
228 
229 #define EXT_CSD_PARTITION_SETTING_COMPLETED	(1 << 0)
230 
231 #define EXT_CSD_ENH_USR		(1 << 0)	/* user data area is enhanced */
232 #define EXT_CSD_ENH_GP(x)	(1 << ((x)+1))	/* GP part (x+1) is enhanced */
233 
234 #define EXT_CSD_HS_CTRL_REL	(1 << 0)	/* host controlled WR_REL_SET */
235 
236 #define EXT_CSD_WR_DATA_REL_USR		(1 << 0)	/* user data area WR_REL */
237 #define EXT_CSD_WR_DATA_REL_GP(x)	(1 << ((x)+1))	/* GP part (x+1) WR_REL */
238 
239 #define R1_ILLEGAL_COMMAND		(1 << 22)
240 #define R1_APP_CMD			(1 << 5)
241 
242 #define MMC_RSP_PRESENT (1 << 0)
243 #define MMC_RSP_136	(1 << 1)		/* 136 bit response */
244 #define MMC_RSP_CRC	(1 << 2)		/* expect valid crc */
245 #define MMC_RSP_BUSY	(1 << 3)		/* card may send busy */
246 #define MMC_RSP_OPCODE	(1 << 4)		/* response contains opcode */
247 
248 #define MMC_RSP_NONE	(0)
249 #define MMC_RSP_R1	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
250 #define MMC_RSP_R1b	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
251 			MMC_RSP_BUSY)
252 #define MMC_RSP_R2	(MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
253 #define MMC_RSP_R3	(MMC_RSP_PRESENT)
254 #define MMC_RSP_R4	(MMC_RSP_PRESENT)
255 #define MMC_RSP_R5	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
256 #define MMC_RSP_R6	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
257 #define MMC_RSP_R7	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
258 
259 #define MMCPART_NOAVAILABLE	(0xff)
260 #define PART_ACCESS_MASK	(0x7)
261 #define PART_SUPPORT		(0x1)
262 #define ENHNCD_SUPPORT		(0x2)
263 #define PART_ENH_ATTRIB		(0x1f)
264 
265 /* Maximum block size for MMC */
266 #define MMC_MAX_BLOCK_LEN	512
267 
268 /* The number of MMC physical partitions.  These consist of:
269  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
270  */
271 #define MMC_NUM_BOOT_PARTITION	2
272 #define MMC_PART_RPMB           3       /* RPMB partition number */
273 
274 /* Driver model support */
275 
276 /**
277  * struct mmc_uclass_priv - Holds information about a device used by the uclass
278  */
279 struct mmc_uclass_priv {
280 	struct mmc *mmc;
281 };
282 
283 /**
284  * mmc_get_mmc_dev() - get the MMC struct pointer for a device
285  *
286  * Provided that the device is already probed and ready for use, this value
287  * will be available.
288  *
289  * @dev:	Device
290  * @return associated mmc struct pointer if available, else NULL
291  */
292 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
293 
294 /* End of driver model support */
295 
296 struct mmc_cid {
297 	unsigned long psn;
298 	unsigned short oid;
299 	unsigned char mid;
300 	unsigned char prv;
301 	unsigned char mdt;
302 	char pnm[7];
303 };
304 
305 struct mmc_cmd {
306 	ushort cmdidx;
307 	uint resp_type;
308 	uint cmdarg;
309 	uint response[4];
310 };
311 
312 struct mmc_data {
313 	union {
314 		char *dest;
315 		const char *src; /* src buffers don't get written to */
316 	};
317 	uint flags;
318 	uint blocks;
319 	uint blocksize;
320 };
321 
322 /* forward decl. */
323 struct mmc;
324 
325 struct mmc_ops {
326 	int (*send_cmd)(struct mmc *mmc,
327 			struct mmc_cmd *cmd, struct mmc_data *data);
328 	void (*set_ios)(struct mmc *mmc);
329 	int (*init)(struct mmc *mmc);
330 	int (*getcd)(struct mmc *mmc);
331 	int (*getwp)(struct mmc *mmc);
332 };
333 
334 struct mmc_config {
335 	const char *name;
336 	const struct mmc_ops *ops;
337 	uint host_caps;
338 	uint voltages;
339 	uint f_min;
340 	uint f_max;
341 	uint b_max;
342 	unsigned char part_type;
343 };
344 
345 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */
346 struct mmc {
347 	struct list_head link;
348 	const struct mmc_config *cfg;	/* provided configuration */
349 	uint version;
350 	void *priv;
351 	uint has_init;
352 	int high_capacity;
353 	uint bus_width;
354 	uint clock;
355 	uint card_caps;
356 	uint ocr;
357 	uint dsr;
358 	uint dsr_imp;
359 	uint scr[2];
360 	uint csd[4];
361 	uint cid[4];
362 	ushort rca;
363 	u8 part_support;
364 	u8 part_attr;
365 	u8 wr_rel_set;
366 	char part_config;
367 	uint tran_speed;
368 	uint read_bl_len;
369 	uint write_bl_len;
370 	uint erase_grp_size;	/* in 512-byte sectors */
371 	uint hc_wp_grp_size;	/* in 512-byte sectors */
372 	u64 capacity;
373 	u64 capacity_user;
374 	u64 capacity_boot;
375 	u64 capacity_rpmb;
376 	u64 capacity_gp[4];
377 	u64 enh_user_start;
378 	u64 enh_user_size;
379 	struct blk_desc block_dev;
380 	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
381 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
382 	char preinit;		/* start init as early as possible */
383 	int ddr_mode;
384 };
385 
386 struct mmc_hwpart_conf {
387 	struct {
388 		uint enh_start;	/* in 512-byte sectors */
389 		uint enh_size;	/* in 512-byte sectors, if 0 no enh area */
390 		unsigned wr_rel_change : 1;
391 		unsigned wr_rel_set : 1;
392 	} user;
393 	struct {
394 		uint size;	/* in 512-byte sectors */
395 		unsigned enhanced : 1;
396 		unsigned wr_rel_change : 1;
397 		unsigned wr_rel_set : 1;
398 	} gp_part[4];
399 };
400 
401 enum mmc_hwpart_conf_mode {
402 	MMC_HWPART_CONF_CHECK,
403 	MMC_HWPART_CONF_SET,
404 	MMC_HWPART_CONF_COMPLETE,
405 };
406 
407 int mmc_register(struct mmc *mmc);
408 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
409 void mmc_destroy(struct mmc *mmc);
410 int mmc_initialize(bd_t *bis);
411 int mmc_init(struct mmc *mmc);
412 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
413 void mmc_set_clock(struct mmc *mmc, uint clock);
414 struct mmc *find_mmc_device(int dev_num);
415 int mmc_set_dev(int dev_num);
416 void print_mmc_devices(char separator);
417 int get_mmc_num(void);
418 int mmc_switch_part(int dev_num, unsigned int part_num);
419 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
420 		      enum mmc_hwpart_conf_mode mode);
421 int mmc_getcd(struct mmc *mmc);
422 int board_mmc_getcd(struct mmc *mmc);
423 int mmc_getwp(struct mmc *mmc);
424 int board_mmc_getwp(struct mmc *mmc);
425 int mmc_set_dsr(struct mmc *mmc, u16 val);
426 /* Function to change the size of boot partition and rpmb partitions */
427 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
428 					unsigned long rpmbsize);
429 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
430 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
431 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
432 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
433 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
434 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
435 /* Functions to read / write the RPMB partition */
436 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
437 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
438 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
439 		  unsigned short cnt, unsigned char *key);
440 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
441 		   unsigned short cnt, unsigned char *key);
442 /**
443  * Start device initialization and return immediately; it does not block on
444  * polling OCR (operation condition register) status.  Then you should call
445  * mmc_init, which would block on polling OCR status and complete the device
446  * initializatin.
447  *
448  * @param mmc	Pointer to a MMC device struct
449  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
450  */
451 int mmc_start_init(struct mmc *mmc);
452 
453 /**
454  * Set preinit flag of mmc device.
455  *
456  * This will cause the device to be pre-inited during mmc_initialize(),
457  * which may save boot time if the device is not accessed until later.
458  * Some eMMC devices take 200-300ms to init, but unfortunately they
459  * must be sent a series of commands to even get them to start preparing
460  * for operation.
461  *
462  * @param mmc		Pointer to a MMC device struct
463  * @param preinit	preinit flag value
464  */
465 void mmc_set_preinit(struct mmc *mmc, int preinit);
466 
467 #ifdef CONFIG_GENERIC_MMC
468 #ifdef CONFIG_MMC_SPI
469 #define mmc_host_is_spi(mmc)	((mmc)->cfg->host_caps & MMC_MODE_SPI)
470 #else
471 #define mmc_host_is_spi(mmc)	0
472 #endif
473 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
474 #else
475 int mmc_legacy_init(int verbose);
476 #endif
477 
478 void board_mmc_power_init(void);
479 int board_mmc_init(bd_t *bis);
480 int cpu_mmc_init(bd_t *bis);
481 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
482 int mmc_get_env_dev(void);
483 
484 struct pci_device_id;
485 
486 /**
487  * pci_mmc_init() - set up PCI MMC devices
488  *
489  * This finds all the matching PCI IDs and sets them up as MMC devices.
490  *
491  * @name:		Name to use for devices
492  * @mmc_supported:	PCI IDs to search for, terminated by {0, 0}
493  */
494 int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
495 
496 /* Set block count limit because of 16 bit register limit on some hardware*/
497 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
498 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
499 #endif
500 
501 #endif /* _MMC_H_ */
502