1 /* 2 * Copyright 2008,2010 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based (loosely) on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _MMC_H_ 11 #define _MMC_H_ 12 13 #include <linux/list.h> 14 #include <linux/compiler.h> 15 #include <part.h> 16 17 #define SD_VERSION_SD 0x20000 18 #define SD_VERSION_3 (SD_VERSION_SD | 0x300) 19 #define SD_VERSION_2 (SD_VERSION_SD | 0x200) 20 #define SD_VERSION_1_0 (SD_VERSION_SD | 0x100) 21 #define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a) 22 #define MMC_VERSION_MMC 0x10000 23 #define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) 24 #define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102) 25 #define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104) 26 #define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202) 27 #define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300) 28 #define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400) 29 #define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401) 30 #define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402) 31 #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) 32 #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) 33 #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) 34 35 #define MMC_MODE_HS 0x001 36 #define MMC_MODE_HS_52MHz 0x010 37 #define MMC_MODE_4BIT 0x100 38 #define MMC_MODE_8BIT 0x200 39 #define MMC_MODE_SPI 0x400 40 #define MMC_MODE_HC 0x800 41 42 #define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) 43 #define MMC_MODE_WIDTH_BITS_SHIFT 8 44 45 #define SD_DATA_4BIT 0x00040000 46 47 #define IS_SD(x) (x->version & SD_VERSION_SD) 48 49 #define MMC_DATA_READ 1 50 #define MMC_DATA_WRITE 2 51 52 #define NO_CARD_ERR -16 /* No SD/MMC card inserted */ 53 #define UNUSABLE_ERR -17 /* Unusable Card */ 54 #define COMM_ERR -18 /* Communications Error */ 55 #define TIMEOUT -19 56 #define IN_PROGRESS -20 /* operation is in progress */ 57 58 #define MMC_CMD_GO_IDLE_STATE 0 59 #define MMC_CMD_SEND_OP_COND 1 60 #define MMC_CMD_ALL_SEND_CID 2 61 #define MMC_CMD_SET_RELATIVE_ADDR 3 62 #define MMC_CMD_SET_DSR 4 63 #define MMC_CMD_SWITCH 6 64 #define MMC_CMD_SELECT_CARD 7 65 #define MMC_CMD_SEND_EXT_CSD 8 66 #define MMC_CMD_SEND_CSD 9 67 #define MMC_CMD_SEND_CID 10 68 #define MMC_CMD_STOP_TRANSMISSION 12 69 #define MMC_CMD_SEND_STATUS 13 70 #define MMC_CMD_SET_BLOCKLEN 16 71 #define MMC_CMD_READ_SINGLE_BLOCK 17 72 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 73 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 74 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 75 #define MMC_CMD_ERASE_GROUP_START 35 76 #define MMC_CMD_ERASE_GROUP_END 36 77 #define MMC_CMD_ERASE 38 78 #define MMC_CMD_APP_CMD 55 79 #define MMC_CMD_SPI_READ_OCR 58 80 #define MMC_CMD_SPI_CRC_ON_OFF 59 81 #define MMC_CMD_RES_MAN 62 82 83 #define MMC_CMD62_ARG1 0xefac62ec 84 #define MMC_CMD62_ARG2 0xcbaea7 85 86 87 #define SD_CMD_SEND_RELATIVE_ADDR 3 88 #define SD_CMD_SWITCH_FUNC 6 89 #define SD_CMD_SEND_IF_COND 8 90 91 #define SD_CMD_APP_SET_BUS_WIDTH 6 92 #define SD_CMD_ERASE_WR_BLK_START 32 93 #define SD_CMD_ERASE_WR_BLK_END 33 94 #define SD_CMD_APP_SEND_OP_COND 41 95 #define SD_CMD_APP_SEND_SCR 51 96 97 /* SCR definitions in different words */ 98 #define SD_HIGHSPEED_BUSY 0x00020000 99 #define SD_HIGHSPEED_SUPPORTED 0x00020000 100 101 #define MMC_HS_TIMING 0x00000100 102 #define MMC_HS_52MHZ 0x2 103 104 #define OCR_BUSY 0x80000000 105 #define OCR_HCS 0x40000000 106 #define OCR_VOLTAGE_MASK 0x007FFF80 107 #define OCR_ACCESS_MODE 0x60000000 108 109 #define SECURE_ERASE 0x80000000 110 111 #define MMC_STATUS_MASK (~0x0206BF7F) 112 #define MMC_STATUS_RDY_FOR_DATA (1 << 8) 113 #define MMC_STATUS_CURR_STATE (0xf << 9) 114 #define MMC_STATUS_ERROR (1 << 19) 115 116 #define MMC_STATE_PRG (7 << 9) 117 118 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 119 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 120 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 121 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 122 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 123 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 124 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 125 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 126 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 127 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 128 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 129 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 130 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 131 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 132 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 133 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 134 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 135 136 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 137 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 138 addressed by index which are 139 1 in value field */ 140 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 141 addressed by index, which are 142 1 in value field */ 143 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 144 145 #define SD_SWITCH_CHECK 0 146 #define SD_SWITCH_SWITCH 1 147 148 /* 149 * EXT_CSD fields 150 */ 151 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 152 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ 153 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ 154 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 155 #define EXT_CSD_RPMB_MULT 168 /* RO */ 156 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 157 #define EXT_CSD_BOOT_BUS_WIDTH 177 158 #define EXT_CSD_PART_CONF 179 /* R/W */ 159 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 160 #define EXT_CSD_HS_TIMING 185 /* R/W */ 161 #define EXT_CSD_REV 192 /* RO */ 162 #define EXT_CSD_CARD_TYPE 196 /* RO */ 163 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 164 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 165 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 166 #define EXT_CSD_BOOT_MULT 226 /* RO */ 167 168 /* 169 * EXT_CSD field definitions 170 */ 171 172 #define EXT_CSD_CMD_SET_NORMAL (1 << 0) 173 #define EXT_CSD_CMD_SET_SECURE (1 << 1) 174 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) 175 176 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ 177 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ 178 179 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 180 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 181 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 182 183 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) 184 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) 185 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) 186 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) 187 188 #define EXT_CSD_BOOT_ACK(x) (x << 6) 189 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) 190 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) 191 192 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) 193 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) 194 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) 195 196 #define R1_ILLEGAL_COMMAND (1 << 22) 197 #define R1_APP_CMD (1 << 5) 198 199 #define MMC_RSP_PRESENT (1 << 0) 200 #define MMC_RSP_136 (1 << 1) /* 136 bit response */ 201 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 202 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 203 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 204 205 #define MMC_RSP_NONE (0) 206 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 207 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 208 MMC_RSP_BUSY) 209 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 210 #define MMC_RSP_R3 (MMC_RSP_PRESENT) 211 #define MMC_RSP_R4 (MMC_RSP_PRESENT) 212 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 213 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 214 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 215 216 #define MMCPART_NOAVAILABLE (0xff) 217 #define PART_ACCESS_MASK (0x7) 218 #define PART_SUPPORT (0x1) 219 #define PART_ENH_ATTRIB (0x1f) 220 221 /* Maximum block size for MMC */ 222 #define MMC_MAX_BLOCK_LEN 512 223 224 /* The number of MMC physical partitions. These consist of: 225 * boot partitions (2), general purpose partitions (4) in MMC v4.4. 226 */ 227 #define MMC_NUM_BOOT_PARTITION 2 228 229 struct mmc_cid { 230 unsigned long psn; 231 unsigned short oid; 232 unsigned char mid; 233 unsigned char prv; 234 unsigned char mdt; 235 char pnm[7]; 236 }; 237 238 struct mmc_cmd { 239 ushort cmdidx; 240 uint resp_type; 241 uint cmdarg; 242 uint response[4]; 243 }; 244 245 struct mmc_data { 246 union { 247 char *dest; 248 const char *src; /* src buffers don't get written to */ 249 }; 250 uint flags; 251 uint blocks; 252 uint blocksize; 253 }; 254 255 /* forward decl. */ 256 struct mmc; 257 258 struct mmc_ops { 259 int (*send_cmd)(struct mmc *mmc, 260 struct mmc_cmd *cmd, struct mmc_data *data); 261 void (*set_ios)(struct mmc *mmc); 262 int (*init)(struct mmc *mmc); 263 int (*getcd)(struct mmc *mmc); 264 int (*getwp)(struct mmc *mmc); 265 }; 266 267 struct mmc_config { 268 const char *name; 269 const struct mmc_ops *ops; 270 uint host_caps; 271 uint voltages; 272 uint f_min; 273 uint f_max; 274 uint b_max; 275 unsigned char part_type; 276 }; 277 278 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */ 279 struct mmc { 280 struct list_head link; 281 const struct mmc_config *cfg; /* provided configuration */ 282 uint version; 283 void *priv; 284 uint has_init; 285 int high_capacity; 286 uint bus_width; 287 uint clock; 288 uint card_caps; 289 uint ocr; 290 uint dsr; 291 uint dsr_imp; 292 uint scr[2]; 293 uint csd[4]; 294 uint cid[4]; 295 ushort rca; 296 char part_config; 297 char part_num; 298 uint tran_speed; 299 uint read_bl_len; 300 uint write_bl_len; 301 uint erase_grp_size; 302 u64 capacity; 303 u64 capacity_user; 304 u64 capacity_boot; 305 u64 capacity_rpmb; 306 u64 capacity_gp[4]; 307 block_dev_desc_t block_dev; 308 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 309 char init_in_progress; /* 1 if we have done mmc_start_init() */ 310 char preinit; /* start init as early as possible */ 311 uint op_cond_response; /* the response byte from the last op_cond */ 312 }; 313 314 int mmc_register(struct mmc *mmc); 315 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); 316 void mmc_destroy(struct mmc *mmc); 317 int mmc_initialize(bd_t *bis); 318 int mmc_init(struct mmc *mmc); 319 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 320 void mmc_set_clock(struct mmc *mmc, uint clock); 321 struct mmc *find_mmc_device(int dev_num); 322 int mmc_set_dev(int dev_num); 323 void print_mmc_devices(char separator); 324 int get_mmc_num(void); 325 int board_mmc_getcd(struct mmc *mmc); 326 int mmc_switch_part(int dev_num, unsigned int part_num); 327 int mmc_getcd(struct mmc *mmc); 328 int mmc_getwp(struct mmc *mmc); 329 int mmc_set_dsr(struct mmc *mmc, u16 val); 330 /* Function to change the size of boot partition and rpmb partitions */ 331 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 332 unsigned long rpmbsize); 333 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ 334 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); 335 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ 336 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); 337 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ 338 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); 339 340 /** 341 * Start device initialization and return immediately; it does not block on 342 * polling OCR (operation condition register) status. Then you should call 343 * mmc_init, which would block on polling OCR status and complete the device 344 * initializatin. 345 * 346 * @param mmc Pointer to a MMC device struct 347 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. 348 */ 349 int mmc_start_init(struct mmc *mmc); 350 351 /** 352 * Set preinit flag of mmc device. 353 * 354 * This will cause the device to be pre-inited during mmc_initialize(), 355 * which may save boot time if the device is not accessed until later. 356 * Some eMMC devices take 200-300ms to init, but unfortunately they 357 * must be sent a series of commands to even get them to start preparing 358 * for operation. 359 * 360 * @param mmc Pointer to a MMC device struct 361 * @param preinit preinit flag value 362 */ 363 void mmc_set_preinit(struct mmc *mmc, int preinit); 364 365 #ifdef CONFIG_GENERIC_MMC 366 #ifdef CONFIG_MMC_SPI 367 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) 368 #else 369 #define mmc_host_is_spi(mmc) 0 370 #endif 371 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); 372 #else 373 int mmc_legacy_init(int verbose); 374 #endif 375 376 int board_mmc_init(bd_t *bis); 377 378 /* Set block count limit because of 16 bit register limit on some hardware*/ 379 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT 380 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 381 #endif 382 383 #endif /* _MMC_H_ */ 384