1 /* 2 * Copyright 2008,2010 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based (loosely) on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _MMC_H_ 11 #define _MMC_H_ 12 13 #include <linux/list.h> 14 #include <linux/compiler.h> 15 #include <part.h> 16 17 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ 18 #define SD_VERSION_SD (1U << 31) 19 #define MMC_VERSION_MMC (1U << 30) 20 21 #define MAKE_SDMMC_VERSION(a, b, c) \ 22 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c)) 23 #define MAKE_SD_VERSION(a, b, c) \ 24 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) 25 #define MAKE_MMC_VERSION(a, b, c) \ 26 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) 27 28 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \ 29 (((u32)(x) >> 16) & 0xff) 30 #define EXTRACT_SDMMC_MINOR_VERSION(x) \ 31 (((u32)(x) >> 8) & 0xff) 32 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \ 33 ((u32)(x) & 0xff) 34 35 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) 36 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) 37 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) 38 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) 39 40 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) 41 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) 42 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) 43 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) 44 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) 45 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) 46 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) 47 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) 48 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) 49 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) 50 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) 51 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) 52 53 #define MMC_MODE_HS (1 << 0) 54 #define MMC_MODE_HS_52MHz (1 << 1) 55 #define MMC_MODE_4BIT (1 << 2) 56 #define MMC_MODE_8BIT (1 << 3) 57 #define MMC_MODE_SPI (1 << 4) 58 #define MMC_MODE_DDR_52MHz (1 << 5) 59 60 #define SD_DATA_4BIT 0x00040000 61 62 #define IS_SD(x) ((x)->version & SD_VERSION_SD) 63 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC) 64 65 #define MMC_DATA_READ 1 66 #define MMC_DATA_WRITE 2 67 68 #define NO_CARD_ERR -16 /* No SD/MMC card inserted */ 69 #define UNUSABLE_ERR -17 /* Unusable Card */ 70 #define COMM_ERR -18 /* Communications Error */ 71 #define TIMEOUT -19 72 #define SWITCH_ERR -20 /* Card reports failure to switch mode */ 73 74 #define MMC_CMD_GO_IDLE_STATE 0 75 #define MMC_CMD_SEND_OP_COND 1 76 #define MMC_CMD_ALL_SEND_CID 2 77 #define MMC_CMD_SET_RELATIVE_ADDR 3 78 #define MMC_CMD_SET_DSR 4 79 #define MMC_CMD_SWITCH 6 80 #define MMC_CMD_SELECT_CARD 7 81 #define MMC_CMD_SEND_EXT_CSD 8 82 #define MMC_CMD_SEND_CSD 9 83 #define MMC_CMD_SEND_CID 10 84 #define MMC_CMD_STOP_TRANSMISSION 12 85 #define MMC_CMD_SEND_STATUS 13 86 #define MMC_CMD_SET_BLOCKLEN 16 87 #define MMC_CMD_READ_SINGLE_BLOCK 17 88 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 89 #define MMC_CMD_SET_BLOCK_COUNT 23 90 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 91 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 92 #define MMC_CMD_ERASE_GROUP_START 35 93 #define MMC_CMD_ERASE_GROUP_END 36 94 #define MMC_CMD_ERASE 38 95 #define MMC_CMD_APP_CMD 55 96 #define MMC_CMD_SPI_READ_OCR 58 97 #define MMC_CMD_SPI_CRC_ON_OFF 59 98 #define MMC_CMD_RES_MAN 62 99 100 #define MMC_CMD62_ARG1 0xefac62ec 101 #define MMC_CMD62_ARG2 0xcbaea7 102 103 104 #define SD_CMD_SEND_RELATIVE_ADDR 3 105 #define SD_CMD_SWITCH_FUNC 6 106 #define SD_CMD_SEND_IF_COND 8 107 #define SD_CMD_SWITCH_UHS18V 11 108 109 #define SD_CMD_APP_SET_BUS_WIDTH 6 110 #define SD_CMD_ERASE_WR_BLK_START 32 111 #define SD_CMD_ERASE_WR_BLK_END 33 112 #define SD_CMD_APP_SEND_OP_COND 41 113 #define SD_CMD_APP_SEND_SCR 51 114 115 /* SCR definitions in different words */ 116 #define SD_HIGHSPEED_BUSY 0x00020000 117 #define SD_HIGHSPEED_SUPPORTED 0x00020000 118 119 #define OCR_BUSY 0x80000000 120 #define OCR_HCS 0x40000000 121 #define OCR_VOLTAGE_MASK 0x007FFF80 122 #define OCR_ACCESS_MODE 0x60000000 123 124 #define SECURE_ERASE 0x80000000 125 126 #define MMC_STATUS_MASK (~0x0206BF7F) 127 #define MMC_STATUS_SWITCH_ERROR (1 << 7) 128 #define MMC_STATUS_RDY_FOR_DATA (1 << 8) 129 #define MMC_STATUS_CURR_STATE (0xf << 9) 130 #define MMC_STATUS_ERROR (1 << 19) 131 132 #define MMC_STATE_PRG (7 << 9) 133 134 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 135 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 136 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 137 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 138 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 139 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 140 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 141 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 142 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 143 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 144 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 145 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 146 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 147 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 148 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 149 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 150 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 151 152 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 153 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 154 addressed by index which are 155 1 in value field */ 156 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 157 addressed by index, which are 158 1 in value field */ 159 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 160 161 #define SD_SWITCH_CHECK 0 162 #define SD_SWITCH_SWITCH 1 163 164 /* 165 * EXT_CSD fields 166 */ 167 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ 168 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ 169 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 170 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ 171 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ 172 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ 173 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ 174 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 175 #define EXT_CSD_WR_REL_PARAM 166 /* R */ 176 #define EXT_CSD_WR_REL_SET 167 /* R/W */ 177 #define EXT_CSD_RPMB_MULT 168 /* RO */ 178 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 179 #define EXT_CSD_BOOT_BUS_WIDTH 177 180 #define EXT_CSD_PART_CONF 179 /* R/W */ 181 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 182 #define EXT_CSD_HS_TIMING 185 /* R/W */ 183 #define EXT_CSD_REV 192 /* RO */ 184 #define EXT_CSD_CARD_TYPE 196 /* RO */ 185 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 186 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 187 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 188 #define EXT_CSD_BOOT_MULT 226 /* RO */ 189 190 /* 191 * EXT_CSD field definitions 192 */ 193 194 #define EXT_CSD_CMD_SET_NORMAL (1 << 0) 195 #define EXT_CSD_CMD_SET_SECURE (1 << 1) 196 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) 197 198 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ 199 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ 200 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) 201 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) 202 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 203 | EXT_CSD_CARD_TYPE_DDR_1_2V) 204 205 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 206 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 207 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 208 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 209 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 210 211 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) 212 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) 213 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) 214 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) 215 216 #define EXT_CSD_BOOT_ACK(x) (x << 6) 217 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) 218 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) 219 220 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) 221 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) 222 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) 223 224 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) 225 226 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ 227 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ 228 229 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ 230 231 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ 232 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ 233 234 #define R1_ILLEGAL_COMMAND (1 << 22) 235 #define R1_APP_CMD (1 << 5) 236 237 #define MMC_RSP_PRESENT (1 << 0) 238 #define MMC_RSP_136 (1 << 1) /* 136 bit response */ 239 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 240 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 241 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 242 243 #define MMC_RSP_NONE (0) 244 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 245 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 246 MMC_RSP_BUSY) 247 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 248 #define MMC_RSP_R3 (MMC_RSP_PRESENT) 249 #define MMC_RSP_R4 (MMC_RSP_PRESENT) 250 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 251 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 252 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 253 254 #define MMCPART_NOAVAILABLE (0xff) 255 #define PART_ACCESS_MASK (0x7) 256 #define PART_SUPPORT (0x1) 257 #define ENHNCD_SUPPORT (0x2) 258 #define PART_ENH_ATTRIB (0x1f) 259 260 /* Maximum block size for MMC */ 261 #define MMC_MAX_BLOCK_LEN 512 262 263 /* The number of MMC physical partitions. These consist of: 264 * boot partitions (2), general purpose partitions (4) in MMC v4.4. 265 */ 266 #define MMC_NUM_BOOT_PARTITION 2 267 #define MMC_PART_RPMB 3 /* RPMB partition number */ 268 269 struct mmc_cid { 270 unsigned long psn; 271 unsigned short oid; 272 unsigned char mid; 273 unsigned char prv; 274 unsigned char mdt; 275 char pnm[7]; 276 }; 277 278 struct mmc_cmd { 279 ushort cmdidx; 280 uint resp_type; 281 uint cmdarg; 282 uint response[4]; 283 }; 284 285 struct mmc_data { 286 union { 287 char *dest; 288 const char *src; /* src buffers don't get written to */ 289 }; 290 uint flags; 291 uint blocks; 292 uint blocksize; 293 }; 294 295 /* forward decl. */ 296 struct mmc; 297 298 struct mmc_ops { 299 int (*send_cmd)(struct mmc *mmc, 300 struct mmc_cmd *cmd, struct mmc_data *data); 301 void (*set_ios)(struct mmc *mmc); 302 int (*init)(struct mmc *mmc); 303 int (*getcd)(struct mmc *mmc); 304 int (*getwp)(struct mmc *mmc); 305 }; 306 307 struct mmc_config { 308 const char *name; 309 const struct mmc_ops *ops; 310 uint host_caps; 311 uint voltages; 312 uint f_min; 313 uint f_max; 314 uint b_max; 315 unsigned char part_type; 316 }; 317 318 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */ 319 struct mmc { 320 struct list_head link; 321 const struct mmc_config *cfg; /* provided configuration */ 322 uint version; 323 void *priv; 324 uint has_init; 325 int high_capacity; 326 uint bus_width; 327 uint clock; 328 uint card_caps; 329 uint ocr; 330 uint dsr; 331 uint dsr_imp; 332 uint scr[2]; 333 uint csd[4]; 334 uint cid[4]; 335 ushort rca; 336 u8 part_support; 337 u8 part_attr; 338 u8 wr_rel_set; 339 char part_config; 340 char part_num; 341 uint tran_speed; 342 uint read_bl_len; 343 uint write_bl_len; 344 uint erase_grp_size; /* in 512-byte sectors */ 345 uint hc_wp_grp_size; /* in 512-byte sectors */ 346 u64 capacity; 347 u64 capacity_user; 348 u64 capacity_boot; 349 u64 capacity_rpmb; 350 u64 capacity_gp[4]; 351 u64 enh_user_start; 352 u64 enh_user_size; 353 block_dev_desc_t block_dev; 354 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 355 char init_in_progress; /* 1 if we have done mmc_start_init() */ 356 char preinit; /* start init as early as possible */ 357 int ddr_mode; 358 }; 359 360 struct mmc_hwpart_conf { 361 struct { 362 uint enh_start; /* in 512-byte sectors */ 363 uint enh_size; /* in 512-byte sectors, if 0 no enh area */ 364 unsigned wr_rel_change : 1; 365 unsigned wr_rel_set : 1; 366 } user; 367 struct { 368 uint size; /* in 512-byte sectors */ 369 unsigned enhanced : 1; 370 unsigned wr_rel_change : 1; 371 unsigned wr_rel_set : 1; 372 } gp_part[4]; 373 }; 374 375 enum mmc_hwpart_conf_mode { 376 MMC_HWPART_CONF_CHECK, 377 MMC_HWPART_CONF_SET, 378 MMC_HWPART_CONF_COMPLETE, 379 }; 380 381 int mmc_register(struct mmc *mmc); 382 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); 383 void mmc_destroy(struct mmc *mmc); 384 int mmc_initialize(bd_t *bis); 385 int mmc_init(struct mmc *mmc); 386 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 387 void mmc_set_clock(struct mmc *mmc, uint clock); 388 struct mmc *find_mmc_device(int dev_num); 389 int mmc_set_dev(int dev_num); 390 void print_mmc_devices(char separator); 391 int get_mmc_num(void); 392 int mmc_switch_part(int dev_num, unsigned int part_num); 393 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, 394 enum mmc_hwpart_conf_mode mode); 395 int mmc_getcd(struct mmc *mmc); 396 int board_mmc_getcd(struct mmc *mmc); 397 int mmc_getwp(struct mmc *mmc); 398 int board_mmc_getwp(struct mmc *mmc); 399 int mmc_set_dsr(struct mmc *mmc, u16 val); 400 /* Function to change the size of boot partition and rpmb partitions */ 401 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 402 unsigned long rpmbsize); 403 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ 404 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); 405 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ 406 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); 407 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ 408 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); 409 /* Functions to read / write the RPMB partition */ 410 int mmc_rpmb_set_key(struct mmc *mmc, void *key); 411 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); 412 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, 413 unsigned short cnt, unsigned char *key); 414 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, 415 unsigned short cnt, unsigned char *key); 416 /** 417 * Start device initialization and return immediately; it does not block on 418 * polling OCR (operation condition register) status. Then you should call 419 * mmc_init, which would block on polling OCR status and complete the device 420 * initializatin. 421 * 422 * @param mmc Pointer to a MMC device struct 423 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. 424 */ 425 int mmc_start_init(struct mmc *mmc); 426 427 /** 428 * Set preinit flag of mmc device. 429 * 430 * This will cause the device to be pre-inited during mmc_initialize(), 431 * which may save boot time if the device is not accessed until later. 432 * Some eMMC devices take 200-300ms to init, but unfortunately they 433 * must be sent a series of commands to even get them to start preparing 434 * for operation. 435 * 436 * @param mmc Pointer to a MMC device struct 437 * @param preinit preinit flag value 438 */ 439 void mmc_set_preinit(struct mmc *mmc, int preinit); 440 441 #ifdef CONFIG_GENERIC_MMC 442 #ifdef CONFIG_MMC_SPI 443 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) 444 #else 445 #define mmc_host_is_spi(mmc) 0 446 #endif 447 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); 448 #else 449 int mmc_legacy_init(int verbose); 450 #endif 451 452 void board_mmc_power_init(void); 453 int board_mmc_init(bd_t *bis); 454 int cpu_mmc_init(bd_t *bis); 455 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); 456 457 struct pci_device_id; 458 459 /** 460 * pci_mmc_init() - set up PCI MMC devices 461 * 462 * This finds all the matching PCI IDs and sets them up as MMC devices. 463 * 464 * @name: Name to use for devices 465 * @mmc_supported: PCI IDs to search for 466 * @num_ids: Number of elements in @mmc_supported 467 */ 468 int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported, 469 int num_ids); 470 471 /* Set block count limit because of 16 bit register limit on some hardware*/ 472 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT 473 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 474 #endif 475 476 #endif /* _MMC_H_ */ 477