1 /* 2 * Copyright 2008,2010 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based (loosely) on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _MMC_H_ 11 #define _MMC_H_ 12 13 #include <linux/list.h> 14 #include <linux/compiler.h> 15 16 #define SD_VERSION_SD 0x20000 17 #define SD_VERSION_3 (SD_VERSION_SD | 0x300) 18 #define SD_VERSION_2 (SD_VERSION_SD | 0x200) 19 #define SD_VERSION_1_0 (SD_VERSION_SD | 0x100) 20 #define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a) 21 #define MMC_VERSION_MMC 0x10000 22 #define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) 23 #define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102) 24 #define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104) 25 #define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202) 26 #define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300) 27 #define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400) 28 #define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401) 29 #define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402) 30 #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) 31 #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) 32 #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) 33 34 #define MMC_MODE_HS 0x001 35 #define MMC_MODE_HS_52MHz 0x010 36 #define MMC_MODE_4BIT 0x100 37 #define MMC_MODE_8BIT 0x200 38 #define MMC_MODE_SPI 0x400 39 #define MMC_MODE_HC 0x800 40 41 #define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) 42 #define MMC_MODE_WIDTH_BITS_SHIFT 8 43 44 #define SD_DATA_4BIT 0x00040000 45 46 #define IS_SD(x) (x->version & SD_VERSION_SD) 47 48 #define MMC_DATA_READ 1 49 #define MMC_DATA_WRITE 2 50 51 #define NO_CARD_ERR -16 /* No SD/MMC card inserted */ 52 #define UNUSABLE_ERR -17 /* Unusable Card */ 53 #define COMM_ERR -18 /* Communications Error */ 54 #define TIMEOUT -19 55 #define IN_PROGRESS -20 /* operation is in progress */ 56 57 #define MMC_CMD_GO_IDLE_STATE 0 58 #define MMC_CMD_SEND_OP_COND 1 59 #define MMC_CMD_ALL_SEND_CID 2 60 #define MMC_CMD_SET_RELATIVE_ADDR 3 61 #define MMC_CMD_SET_DSR 4 62 #define MMC_CMD_SWITCH 6 63 #define MMC_CMD_SELECT_CARD 7 64 #define MMC_CMD_SEND_EXT_CSD 8 65 #define MMC_CMD_SEND_CSD 9 66 #define MMC_CMD_SEND_CID 10 67 #define MMC_CMD_STOP_TRANSMISSION 12 68 #define MMC_CMD_SEND_STATUS 13 69 #define MMC_CMD_SET_BLOCKLEN 16 70 #define MMC_CMD_READ_SINGLE_BLOCK 17 71 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 72 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 73 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 74 #define MMC_CMD_ERASE_GROUP_START 35 75 #define MMC_CMD_ERASE_GROUP_END 36 76 #define MMC_CMD_ERASE 38 77 #define MMC_CMD_APP_CMD 55 78 #define MMC_CMD_SPI_READ_OCR 58 79 #define MMC_CMD_SPI_CRC_ON_OFF 59 80 #define MMC_CMD_RES_MAN 62 81 82 #define MMC_CMD62_ARG1 0xefac62ec 83 #define MMC_CMD62_ARG2 0xcbaea7 84 85 86 #define SD_CMD_SEND_RELATIVE_ADDR 3 87 #define SD_CMD_SWITCH_FUNC 6 88 #define SD_CMD_SEND_IF_COND 8 89 90 #define SD_CMD_APP_SET_BUS_WIDTH 6 91 #define SD_CMD_ERASE_WR_BLK_START 32 92 #define SD_CMD_ERASE_WR_BLK_END 33 93 #define SD_CMD_APP_SEND_OP_COND 41 94 #define SD_CMD_APP_SEND_SCR 51 95 96 /* SCR definitions in different words */ 97 #define SD_HIGHSPEED_BUSY 0x00020000 98 #define SD_HIGHSPEED_SUPPORTED 0x00020000 99 100 #define MMC_HS_TIMING 0x00000100 101 #define MMC_HS_52MHZ 0x2 102 103 #define OCR_BUSY 0x80000000 104 #define OCR_HCS 0x40000000 105 #define OCR_VOLTAGE_MASK 0x007FFF80 106 #define OCR_ACCESS_MODE 0x60000000 107 108 #define SECURE_ERASE 0x80000000 109 110 #define MMC_STATUS_MASK (~0x0206BF7F) 111 #define MMC_STATUS_RDY_FOR_DATA (1 << 8) 112 #define MMC_STATUS_CURR_STATE (0xf << 9) 113 #define MMC_STATUS_ERROR (1 << 19) 114 115 #define MMC_STATE_PRG (7 << 9) 116 117 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 118 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 119 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 120 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 121 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 122 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 123 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 124 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 125 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 126 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 127 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 128 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 129 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 130 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 131 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 132 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 133 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 134 135 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 136 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 137 addressed by index which are 138 1 in value field */ 139 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 140 addressed by index, which are 141 1 in value field */ 142 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 143 144 #define SD_SWITCH_CHECK 0 145 #define SD_SWITCH_SWITCH 1 146 147 /* 148 * EXT_CSD fields 149 */ 150 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 151 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ 152 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ 153 #define EXT_CSD_RPMB_MULT 168 /* RO */ 154 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 155 #define EXT_CSD_BOOT_BUS_WIDTH 177 156 #define EXT_CSD_PART_CONF 179 /* R/W */ 157 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 158 #define EXT_CSD_HS_TIMING 185 /* R/W */ 159 #define EXT_CSD_REV 192 /* RO */ 160 #define EXT_CSD_CARD_TYPE 196 /* RO */ 161 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 162 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 163 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 164 #define EXT_CSD_BOOT_MULT 226 /* RO */ 165 166 /* 167 * EXT_CSD field definitions 168 */ 169 170 #define EXT_CSD_CMD_SET_NORMAL (1 << 0) 171 #define EXT_CSD_CMD_SET_SECURE (1 << 1) 172 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) 173 174 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ 175 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ 176 177 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 178 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 179 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 180 181 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) 182 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) 183 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) 184 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) 185 186 #define EXT_CSD_BOOT_ACK(x) (x << 6) 187 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) 188 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) 189 190 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) 191 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) 192 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) 193 194 #define R1_ILLEGAL_COMMAND (1 << 22) 195 #define R1_APP_CMD (1 << 5) 196 197 #define MMC_RSP_PRESENT (1 << 0) 198 #define MMC_RSP_136 (1 << 1) /* 136 bit response */ 199 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 200 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 201 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 202 203 #define MMC_RSP_NONE (0) 204 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 205 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 206 MMC_RSP_BUSY) 207 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 208 #define MMC_RSP_R3 (MMC_RSP_PRESENT) 209 #define MMC_RSP_R4 (MMC_RSP_PRESENT) 210 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 211 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 212 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 213 214 #define MMCPART_NOAVAILABLE (0xff) 215 #define PART_ACCESS_MASK (0x7) 216 #define PART_SUPPORT (0x1) 217 #define PART_ENH_ATTRIB (0x1f) 218 219 /* Maximum block size for MMC */ 220 #define MMC_MAX_BLOCK_LEN 512 221 222 /* The number of MMC physical partitions. These consist of: 223 * boot partitions (2), general purpose partitions (4) in MMC v4.4. 224 */ 225 #define MMC_NUM_BOOT_PARTITION 2 226 227 struct mmc_cid { 228 unsigned long psn; 229 unsigned short oid; 230 unsigned char mid; 231 unsigned char prv; 232 unsigned char mdt; 233 char pnm[7]; 234 }; 235 236 struct mmc_cmd { 237 ushort cmdidx; 238 uint resp_type; 239 uint cmdarg; 240 uint response[4]; 241 }; 242 243 struct mmc_data { 244 union { 245 char *dest; 246 const char *src; /* src buffers don't get written to */ 247 }; 248 uint flags; 249 uint blocks; 250 uint blocksize; 251 }; 252 253 struct mmc { 254 struct list_head link; 255 char name[32]; 256 void *priv; 257 uint voltages; 258 uint version; 259 uint has_init; 260 uint f_min; 261 uint f_max; 262 int high_capacity; 263 uint bus_width; 264 uint clock; 265 uint card_caps; 266 uint host_caps; 267 uint ocr; 268 uint dsr; 269 uint dsr_imp; 270 uint scr[2]; 271 uint csd[4]; 272 uint cid[4]; 273 ushort rca; 274 char part_config; 275 char part_num; 276 uint tran_speed; 277 uint read_bl_len; 278 uint write_bl_len; 279 uint erase_grp_size; 280 u64 capacity; 281 u64 capacity_user; 282 u64 capacity_boot; 283 u64 capacity_rpmb; 284 u64 capacity_gp[4]; 285 block_dev_desc_t block_dev; 286 int (*send_cmd)(struct mmc *mmc, 287 struct mmc_cmd *cmd, struct mmc_data *data); 288 void (*set_ios)(struct mmc *mmc); 289 int (*init)(struct mmc *mmc); 290 int (*getcd)(struct mmc *mmc); 291 int (*getwp)(struct mmc *mmc); 292 uint b_max; 293 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 294 char init_in_progress; /* 1 if we have done mmc_start_init() */ 295 char preinit; /* start init as early as possible */ 296 uint op_cond_response; /* the response byte from the last op_cond */ 297 }; 298 299 int mmc_register(struct mmc *mmc); 300 int mmc_initialize(bd_t *bis); 301 int mmc_init(struct mmc *mmc); 302 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 303 void mmc_set_clock(struct mmc *mmc, uint clock); 304 struct mmc *find_mmc_device(int dev_num); 305 int mmc_set_dev(int dev_num); 306 void print_mmc_devices(char separator); 307 int get_mmc_num(void); 308 int board_mmc_getcd(struct mmc *mmc); 309 int mmc_switch_part(int dev_num, unsigned int part_num); 310 int mmc_getcd(struct mmc *mmc); 311 int mmc_getwp(struct mmc *mmc); 312 int mmc_set_dsr(struct mmc *mmc, u16 val); 313 /* Function to change the size of boot partition and rpmb partitions */ 314 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 315 unsigned long rpmbsize); 316 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ 317 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); 318 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ 319 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); 320 321 /** 322 * Start device initialization and return immediately; it does not block on 323 * polling OCR (operation condition register) status. Then you should call 324 * mmc_init, which would block on polling OCR status and complete the device 325 * initializatin. 326 * 327 * @param mmc Pointer to a MMC device struct 328 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. 329 */ 330 int mmc_start_init(struct mmc *mmc); 331 332 /** 333 * Set preinit flag of mmc device. 334 * 335 * This will cause the device to be pre-inited during mmc_initialize(), 336 * which may save boot time if the device is not accessed until later. 337 * Some eMMC devices take 200-300ms to init, but unfortunately they 338 * must be sent a series of commands to even get them to start preparing 339 * for operation. 340 * 341 * @param mmc Pointer to a MMC device struct 342 * @param preinit preinit flag value 343 */ 344 void mmc_set_preinit(struct mmc *mmc, int preinit); 345 346 #ifdef CONFIG_GENERIC_MMC 347 #ifdef CONFIG_MMC_SPI 348 #define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI) 349 #else 350 #define mmc_host_is_spi(mmc) 0 351 #endif 352 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); 353 #else 354 int mmc_legacy_init(int verbose); 355 #endif 356 357 #endif /* _MMC_H_ */ 358