1 /* 2 * Copyright 2008,2010 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based (loosely) on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _MMC_H_ 11 #define _MMC_H_ 12 13 #include <linux/list.h> 14 #include <linux/compiler.h> 15 #include <part.h> 16 17 #define SD_VERSION_SD 0x20000 18 #define SD_VERSION_3 (SD_VERSION_SD | 0x300) 19 #define SD_VERSION_2 (SD_VERSION_SD | 0x200) 20 #define SD_VERSION_1_0 (SD_VERSION_SD | 0x100) 21 #define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a) 22 #define MMC_VERSION_MMC 0x10000 23 #define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) 24 #define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102) 25 #define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104) 26 #define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202) 27 #define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300) 28 #define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400) 29 #define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401) 30 #define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402) 31 #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) 32 #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) 33 #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) 34 35 #define MMC_MODE_HS (1 << 0) 36 #define MMC_MODE_HS_52MHz (1 << 1) 37 #define MMC_MODE_4BIT (1 << 2) 38 #define MMC_MODE_8BIT (1 << 3) 39 #define MMC_MODE_SPI (1 << 4) 40 #define MMC_MODE_HC (1 << 5) 41 #define MMC_MODE_DDR_52MHz (1 << 6) 42 43 #define SD_DATA_4BIT 0x00040000 44 45 #define IS_SD(x) (x->version & SD_VERSION_SD) 46 47 #define MMC_DATA_READ 1 48 #define MMC_DATA_WRITE 2 49 50 #define NO_CARD_ERR -16 /* No SD/MMC card inserted */ 51 #define UNUSABLE_ERR -17 /* Unusable Card */ 52 #define COMM_ERR -18 /* Communications Error */ 53 #define TIMEOUT -19 54 #define IN_PROGRESS -20 /* operation is in progress */ 55 #define SWITCH_ERR -21 /* Card reports failure to switch mode */ 56 57 #define MMC_CMD_GO_IDLE_STATE 0 58 #define MMC_CMD_SEND_OP_COND 1 59 #define MMC_CMD_ALL_SEND_CID 2 60 #define MMC_CMD_SET_RELATIVE_ADDR 3 61 #define MMC_CMD_SET_DSR 4 62 #define MMC_CMD_SWITCH 6 63 #define MMC_CMD_SELECT_CARD 7 64 #define MMC_CMD_SEND_EXT_CSD 8 65 #define MMC_CMD_SEND_CSD 9 66 #define MMC_CMD_SEND_CID 10 67 #define MMC_CMD_STOP_TRANSMISSION 12 68 #define MMC_CMD_SEND_STATUS 13 69 #define MMC_CMD_SET_BLOCKLEN 16 70 #define MMC_CMD_READ_SINGLE_BLOCK 17 71 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 72 #define MMC_CMD_SET_BLOCK_COUNT 23 73 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 74 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 75 #define MMC_CMD_ERASE_GROUP_START 35 76 #define MMC_CMD_ERASE_GROUP_END 36 77 #define MMC_CMD_ERASE 38 78 #define MMC_CMD_APP_CMD 55 79 #define MMC_CMD_SPI_READ_OCR 58 80 #define MMC_CMD_SPI_CRC_ON_OFF 59 81 #define MMC_CMD_RES_MAN 62 82 83 #define MMC_CMD62_ARG1 0xefac62ec 84 #define MMC_CMD62_ARG2 0xcbaea7 85 86 87 #define SD_CMD_SEND_RELATIVE_ADDR 3 88 #define SD_CMD_SWITCH_FUNC 6 89 #define SD_CMD_SEND_IF_COND 8 90 91 #define SD_CMD_APP_SET_BUS_WIDTH 6 92 #define SD_CMD_ERASE_WR_BLK_START 32 93 #define SD_CMD_ERASE_WR_BLK_END 33 94 #define SD_CMD_APP_SEND_OP_COND 41 95 #define SD_CMD_APP_SEND_SCR 51 96 97 /* SCR definitions in different words */ 98 #define SD_HIGHSPEED_BUSY 0x00020000 99 #define SD_HIGHSPEED_SUPPORTED 0x00020000 100 101 #define OCR_BUSY 0x80000000 102 #define OCR_HCS 0x40000000 103 #define OCR_VOLTAGE_MASK 0x007FFF80 104 #define OCR_ACCESS_MODE 0x60000000 105 106 #define SECURE_ERASE 0x80000000 107 108 #define MMC_STATUS_MASK (~0x0206BF7F) 109 #define MMC_STATUS_SWITCH_ERROR (1 << 7) 110 #define MMC_STATUS_RDY_FOR_DATA (1 << 8) 111 #define MMC_STATUS_CURR_STATE (0xf << 9) 112 #define MMC_STATUS_ERROR (1 << 19) 113 114 #define MMC_STATE_PRG (7 << 9) 115 116 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 117 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 118 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 119 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 120 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 121 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 122 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 123 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 124 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 125 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 126 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 127 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 128 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 129 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 130 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 131 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 132 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 133 134 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 135 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 136 addressed by index which are 137 1 in value field */ 138 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 139 addressed by index, which are 140 1 in value field */ 141 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 142 143 #define SD_SWITCH_CHECK 0 144 #define SD_SWITCH_SWITCH 1 145 146 /* 147 * EXT_CSD fields 148 */ 149 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 150 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ 151 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ 152 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 153 #define EXT_CSD_RPMB_MULT 168 /* RO */ 154 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 155 #define EXT_CSD_BOOT_BUS_WIDTH 177 156 #define EXT_CSD_PART_CONF 179 /* R/W */ 157 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 158 #define EXT_CSD_HS_TIMING 185 /* R/W */ 159 #define EXT_CSD_REV 192 /* RO */ 160 #define EXT_CSD_CARD_TYPE 196 /* RO */ 161 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 162 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 163 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 164 #define EXT_CSD_BOOT_MULT 226 /* RO */ 165 166 /* 167 * EXT_CSD field definitions 168 */ 169 170 #define EXT_CSD_CMD_SET_NORMAL (1 << 0) 171 #define EXT_CSD_CMD_SET_SECURE (1 << 1) 172 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) 173 174 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ 175 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ 176 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) 177 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) 178 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 179 | EXT_CSD_CARD_TYPE_DDR_1_2V) 180 181 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 182 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 183 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 184 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 185 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 186 187 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) 188 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) 189 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) 190 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) 191 192 #define EXT_CSD_BOOT_ACK(x) (x << 6) 193 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) 194 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) 195 196 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) 197 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) 198 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) 199 200 #define R1_ILLEGAL_COMMAND (1 << 22) 201 #define R1_APP_CMD (1 << 5) 202 203 #define MMC_RSP_PRESENT (1 << 0) 204 #define MMC_RSP_136 (1 << 1) /* 136 bit response */ 205 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 206 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 207 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 208 209 #define MMC_RSP_NONE (0) 210 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 211 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 212 MMC_RSP_BUSY) 213 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 214 #define MMC_RSP_R3 (MMC_RSP_PRESENT) 215 #define MMC_RSP_R4 (MMC_RSP_PRESENT) 216 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 217 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 218 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 219 220 #define MMCPART_NOAVAILABLE (0xff) 221 #define PART_ACCESS_MASK (0x7) 222 #define PART_SUPPORT (0x1) 223 #define PART_ENH_ATTRIB (0x1f) 224 225 /* Maximum block size for MMC */ 226 #define MMC_MAX_BLOCK_LEN 512 227 228 /* The number of MMC physical partitions. These consist of: 229 * boot partitions (2), general purpose partitions (4) in MMC v4.4. 230 */ 231 #define MMC_NUM_BOOT_PARTITION 2 232 #define MMC_PART_RPMB 3 /* RPMB partition number */ 233 234 struct mmc_cid { 235 unsigned long psn; 236 unsigned short oid; 237 unsigned char mid; 238 unsigned char prv; 239 unsigned char mdt; 240 char pnm[7]; 241 }; 242 243 struct mmc_cmd { 244 ushort cmdidx; 245 uint resp_type; 246 uint cmdarg; 247 uint response[4]; 248 }; 249 250 struct mmc_data { 251 union { 252 char *dest; 253 const char *src; /* src buffers don't get written to */ 254 }; 255 uint flags; 256 uint blocks; 257 uint blocksize; 258 }; 259 260 /* forward decl. */ 261 struct mmc; 262 263 struct mmc_ops { 264 int (*send_cmd)(struct mmc *mmc, 265 struct mmc_cmd *cmd, struct mmc_data *data); 266 void (*set_ios)(struct mmc *mmc); 267 int (*init)(struct mmc *mmc); 268 int (*getcd)(struct mmc *mmc); 269 int (*getwp)(struct mmc *mmc); 270 }; 271 272 struct mmc_config { 273 const char *name; 274 const struct mmc_ops *ops; 275 uint host_caps; 276 uint voltages; 277 uint f_min; 278 uint f_max; 279 uint b_max; 280 unsigned char part_type; 281 }; 282 283 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */ 284 struct mmc { 285 struct list_head link; 286 const struct mmc_config *cfg; /* provided configuration */ 287 uint version; 288 void *priv; 289 uint has_init; 290 int high_capacity; 291 uint bus_width; 292 uint clock; 293 uint card_caps; 294 uint ocr; 295 uint dsr; 296 uint dsr_imp; 297 uint scr[2]; 298 uint csd[4]; 299 uint cid[4]; 300 ushort rca; 301 char part_config; 302 char part_num; 303 uint tran_speed; 304 uint read_bl_len; 305 uint write_bl_len; 306 uint erase_grp_size; 307 u64 capacity; 308 u64 capacity_user; 309 u64 capacity_boot; 310 u64 capacity_rpmb; 311 u64 capacity_gp[4]; 312 block_dev_desc_t block_dev; 313 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 314 char init_in_progress; /* 1 if we have done mmc_start_init() */ 315 char preinit; /* start init as early as possible */ 316 uint op_cond_response; /* the response byte from the last op_cond */ 317 }; 318 319 int mmc_register(struct mmc *mmc); 320 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); 321 void mmc_destroy(struct mmc *mmc); 322 int mmc_initialize(bd_t *bis); 323 int mmc_init(struct mmc *mmc); 324 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 325 void mmc_set_clock(struct mmc *mmc, uint clock); 326 struct mmc *find_mmc_device(int dev_num); 327 int mmc_set_dev(int dev_num); 328 void print_mmc_devices(char separator); 329 int get_mmc_num(void); 330 int mmc_switch_part(int dev_num, unsigned int part_num); 331 int mmc_getcd(struct mmc *mmc); 332 int board_mmc_getcd(struct mmc *mmc); 333 int mmc_getwp(struct mmc *mmc); 334 int board_mmc_getwp(struct mmc *mmc); 335 int mmc_set_dsr(struct mmc *mmc, u16 val); 336 /* Function to change the size of boot partition and rpmb partitions */ 337 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 338 unsigned long rpmbsize); 339 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ 340 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); 341 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ 342 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); 343 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ 344 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); 345 /* Functions to read / write the RPMB partition */ 346 int mmc_rpmb_set_key(struct mmc *mmc, void *key); 347 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); 348 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, 349 unsigned short cnt, unsigned char *key); 350 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, 351 unsigned short cnt, unsigned char *key); 352 /** 353 * Start device initialization and return immediately; it does not block on 354 * polling OCR (operation condition register) status. Then you should call 355 * mmc_init, which would block on polling OCR status and complete the device 356 * initializatin. 357 * 358 * @param mmc Pointer to a MMC device struct 359 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. 360 */ 361 int mmc_start_init(struct mmc *mmc); 362 363 /** 364 * Set preinit flag of mmc device. 365 * 366 * This will cause the device to be pre-inited during mmc_initialize(), 367 * which may save boot time if the device is not accessed until later. 368 * Some eMMC devices take 200-300ms to init, but unfortunately they 369 * must be sent a series of commands to even get them to start preparing 370 * for operation. 371 * 372 * @param mmc Pointer to a MMC device struct 373 * @param preinit preinit flag value 374 */ 375 void mmc_set_preinit(struct mmc *mmc, int preinit); 376 377 #ifdef CONFIG_GENERIC_MMC 378 #ifdef CONFIG_MMC_SPI 379 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) 380 #else 381 #define mmc_host_is_spi(mmc) 0 382 #endif 383 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); 384 #else 385 int mmc_legacy_init(int verbose); 386 #endif 387 388 int board_mmc_init(bd_t *bis); 389 int cpu_mmc_init(bd_t *bis); 390 391 /* Set block count limit because of 16 bit register limit on some hardware*/ 392 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT 393 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 394 #endif 395 396 #endif /* _MMC_H_ */ 397