1 /* 2 * Copyright 2008,2010 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based (loosely) on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _MMC_H_ 11 #define _MMC_H_ 12 13 #include <linux/list.h> 14 #include <linux/compiler.h> 15 #include <part.h> 16 17 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ 18 #define SD_VERSION_SD (1U << 31) 19 #define MMC_VERSION_MMC (1U << 30) 20 21 #define MAKE_SDMMC_VERSION(a, b, c) \ 22 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c)) 23 #define MAKE_SD_VERSION(a, b, c) \ 24 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) 25 #define MAKE_MMC_VERSION(a, b, c) \ 26 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) 27 28 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \ 29 (((u32)(x) >> 16) & 0xff) 30 #define EXTRACT_SDMMC_MINOR_VERSION(x) \ 31 (((u32)(x) >> 8) & 0xff) 32 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \ 33 ((u32)(x) & 0xff) 34 35 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) 36 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) 37 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) 38 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) 39 40 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) 41 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) 42 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) 43 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) 44 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) 45 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) 46 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) 47 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) 48 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) 49 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) 50 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) 51 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) 52 #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) 53 54 #define MMC_MODE_HS (1 << 0) 55 #define MMC_MODE_HS_52MHz (1 << 1) 56 #define MMC_MODE_4BIT (1 << 2) 57 #define MMC_MODE_8BIT (1 << 3) 58 #define MMC_MODE_SPI (1 << 4) 59 #define MMC_MODE_DDR_52MHz (1 << 5) 60 61 #define SD_DATA_4BIT 0x00040000 62 63 #define IS_SD(x) ((x)->version & SD_VERSION_SD) 64 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC) 65 66 #define MMC_DATA_READ 1 67 #define MMC_DATA_WRITE 2 68 69 #define NO_CARD_ERR -16 /* No SD/MMC card inserted */ 70 #define UNUSABLE_ERR -17 /* Unusable Card */ 71 #define COMM_ERR -18 /* Communications Error */ 72 #define TIMEOUT -19 73 #define SWITCH_ERR -20 /* Card reports failure to switch mode */ 74 75 #define MMC_CMD_GO_IDLE_STATE 0 76 #define MMC_CMD_SEND_OP_COND 1 77 #define MMC_CMD_ALL_SEND_CID 2 78 #define MMC_CMD_SET_RELATIVE_ADDR 3 79 #define MMC_CMD_SET_DSR 4 80 #define MMC_CMD_SWITCH 6 81 #define MMC_CMD_SELECT_CARD 7 82 #define MMC_CMD_SEND_EXT_CSD 8 83 #define MMC_CMD_SEND_CSD 9 84 #define MMC_CMD_SEND_CID 10 85 #define MMC_CMD_STOP_TRANSMISSION 12 86 #define MMC_CMD_SEND_STATUS 13 87 #define MMC_CMD_SET_BLOCKLEN 16 88 #define MMC_CMD_READ_SINGLE_BLOCK 17 89 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 90 #define MMC_CMD_SET_BLOCK_COUNT 23 91 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 92 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 93 #define MMC_CMD_ERASE_GROUP_START 35 94 #define MMC_CMD_ERASE_GROUP_END 36 95 #define MMC_CMD_ERASE 38 96 #define MMC_CMD_APP_CMD 55 97 #define MMC_CMD_SPI_READ_OCR 58 98 #define MMC_CMD_SPI_CRC_ON_OFF 59 99 #define MMC_CMD_RES_MAN 62 100 101 #define MMC_CMD62_ARG1 0xefac62ec 102 #define MMC_CMD62_ARG2 0xcbaea7 103 104 105 #define SD_CMD_SEND_RELATIVE_ADDR 3 106 #define SD_CMD_SWITCH_FUNC 6 107 #define SD_CMD_SEND_IF_COND 8 108 #define SD_CMD_SWITCH_UHS18V 11 109 110 #define SD_CMD_APP_SET_BUS_WIDTH 6 111 #define SD_CMD_ERASE_WR_BLK_START 32 112 #define SD_CMD_ERASE_WR_BLK_END 33 113 #define SD_CMD_APP_SEND_OP_COND 41 114 #define SD_CMD_APP_SEND_SCR 51 115 116 /* SCR definitions in different words */ 117 #define SD_HIGHSPEED_BUSY 0x00020000 118 #define SD_HIGHSPEED_SUPPORTED 0x00020000 119 120 #define OCR_BUSY 0x80000000 121 #define OCR_HCS 0x40000000 122 #define OCR_VOLTAGE_MASK 0x007FFF80 123 #define OCR_ACCESS_MODE 0x60000000 124 125 #define MMC_ERASE_ARG 0x00000000 126 #define MMC_SECURE_ERASE_ARG 0x80000000 127 #define MMC_TRIM_ARG 0x00000001 128 #define MMC_DISCARD_ARG 0x00000003 129 #define MMC_SECURE_TRIM1_ARG 0x80000001 130 #define MMC_SECURE_TRIM2_ARG 0x80008000 131 132 #define MMC_STATUS_MASK (~0x0206BF7F) 133 #define MMC_STATUS_SWITCH_ERROR (1 << 7) 134 #define MMC_STATUS_RDY_FOR_DATA (1 << 8) 135 #define MMC_STATUS_CURR_STATE (0xf << 9) 136 #define MMC_STATUS_ERROR (1 << 19) 137 138 #define MMC_STATE_PRG (7 << 9) 139 140 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 141 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 142 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 143 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 144 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 145 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 146 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 147 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 148 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 149 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 150 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 151 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 152 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 153 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 154 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 155 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 156 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 157 158 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 159 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 160 addressed by index which are 161 1 in value field */ 162 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 163 addressed by index, which are 164 1 in value field */ 165 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 166 167 #define SD_SWITCH_CHECK 0 168 #define SD_SWITCH_SWITCH 1 169 170 /* 171 * EXT_CSD fields 172 */ 173 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ 174 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ 175 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 176 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ 177 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ 178 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ 179 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ 180 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 181 #define EXT_CSD_WR_REL_PARAM 166 /* R */ 182 #define EXT_CSD_WR_REL_SET 167 /* R/W */ 183 #define EXT_CSD_RPMB_MULT 168 /* RO */ 184 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 185 #define EXT_CSD_BOOT_BUS_WIDTH 177 186 #define EXT_CSD_PART_CONF 179 /* R/W */ 187 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 188 #define EXT_CSD_HS_TIMING 185 /* R/W */ 189 #define EXT_CSD_REV 192 /* RO */ 190 #define EXT_CSD_CARD_TYPE 196 /* RO */ 191 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 192 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 193 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 194 #define EXT_CSD_BOOT_MULT 226 /* RO */ 195 196 /* 197 * EXT_CSD field definitions 198 */ 199 200 #define EXT_CSD_CMD_SET_NORMAL (1 << 0) 201 #define EXT_CSD_CMD_SET_SECURE (1 << 1) 202 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) 203 204 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ 205 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ 206 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) 207 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) 208 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 209 | EXT_CSD_CARD_TYPE_DDR_1_2V) 210 211 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 212 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 213 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 214 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 215 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 216 217 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) 218 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) 219 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) 220 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) 221 222 #define EXT_CSD_BOOT_ACK(x) (x << 6) 223 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) 224 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) 225 226 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) 227 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) 228 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) 229 230 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) 231 232 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ 233 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ 234 235 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ 236 237 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ 238 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ 239 240 #define R1_ILLEGAL_COMMAND (1 << 22) 241 #define R1_APP_CMD (1 << 5) 242 243 #define MMC_RSP_PRESENT (1 << 0) 244 #define MMC_RSP_136 (1 << 1) /* 136 bit response */ 245 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 246 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 247 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 248 249 #define MMC_RSP_NONE (0) 250 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 251 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 252 MMC_RSP_BUSY) 253 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 254 #define MMC_RSP_R3 (MMC_RSP_PRESENT) 255 #define MMC_RSP_R4 (MMC_RSP_PRESENT) 256 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 257 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 258 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 259 260 #define MMCPART_NOAVAILABLE (0xff) 261 #define PART_ACCESS_MASK (0x7) 262 #define PART_SUPPORT (0x1) 263 #define ENHNCD_SUPPORT (0x2) 264 #define PART_ENH_ATTRIB (0x1f) 265 266 /* Maximum block size for MMC */ 267 #define MMC_MAX_BLOCK_LEN 512 268 269 /* The number of MMC physical partitions. These consist of: 270 * boot partitions (2), general purpose partitions (4) in MMC v4.4. 271 */ 272 #define MMC_NUM_BOOT_PARTITION 2 273 #define MMC_PART_RPMB 3 /* RPMB partition number */ 274 275 /* Driver model support */ 276 277 /** 278 * struct mmc_uclass_priv - Holds information about a device used by the uclass 279 */ 280 struct mmc_uclass_priv { 281 struct mmc *mmc; 282 }; 283 284 /** 285 * mmc_get_mmc_dev() - get the MMC struct pointer for a device 286 * 287 * Provided that the device is already probed and ready for use, this value 288 * will be available. 289 * 290 * @dev: Device 291 * @return associated mmc struct pointer if available, else NULL 292 */ 293 struct mmc *mmc_get_mmc_dev(struct udevice *dev); 294 295 /* End of driver model support */ 296 297 struct mmc_cid { 298 unsigned long psn; 299 unsigned short oid; 300 unsigned char mid; 301 unsigned char prv; 302 unsigned char mdt; 303 char pnm[7]; 304 }; 305 306 struct mmc_cmd { 307 ushort cmdidx; 308 uint resp_type; 309 uint cmdarg; 310 uint response[4]; 311 }; 312 313 struct mmc_data { 314 union { 315 char *dest; 316 const char *src; /* src buffers don't get written to */ 317 }; 318 uint flags; 319 uint blocks; 320 uint blocksize; 321 }; 322 323 /* forward decl. */ 324 struct mmc; 325 326 struct mmc_ops { 327 int (*send_cmd)(struct mmc *mmc, 328 struct mmc_cmd *cmd, struct mmc_data *data); 329 void (*set_ios)(struct mmc *mmc); 330 int (*init)(struct mmc *mmc); 331 int (*getcd)(struct mmc *mmc); 332 int (*getwp)(struct mmc *mmc); 333 }; 334 335 struct mmc_config { 336 const char *name; 337 const struct mmc_ops *ops; 338 uint host_caps; 339 uint voltages; 340 uint f_min; 341 uint f_max; 342 uint b_max; 343 unsigned char part_type; 344 }; 345 346 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */ 347 struct mmc { 348 #ifndef CONFIG_BLK 349 struct list_head link; 350 #endif 351 const struct mmc_config *cfg; /* provided configuration */ 352 uint version; 353 void *priv; 354 uint has_init; 355 int high_capacity; 356 uint bus_width; 357 uint clock; 358 uint card_caps; 359 uint ocr; 360 uint dsr; 361 uint dsr_imp; 362 uint scr[2]; 363 uint csd[4]; 364 uint cid[4]; 365 ushort rca; 366 u8 part_support; 367 u8 part_attr; 368 u8 wr_rel_set; 369 char part_config; 370 uint tran_speed; 371 uint read_bl_len; 372 uint write_bl_len; 373 uint erase_grp_size; /* in 512-byte sectors */ 374 uint hc_wp_grp_size; /* in 512-byte sectors */ 375 u64 capacity; 376 u64 capacity_user; 377 u64 capacity_boot; 378 u64 capacity_rpmb; 379 u64 capacity_gp[4]; 380 u64 enh_user_start; 381 u64 enh_user_size; 382 #ifndef CONFIG_BLK 383 struct blk_desc block_dev; 384 #endif 385 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 386 char init_in_progress; /* 1 if we have done mmc_start_init() */ 387 char preinit; /* start init as early as possible */ 388 int ddr_mode; 389 #ifdef CONFIG_DM_MMC 390 struct udevice *dev; /* Device for this MMC controller */ 391 #endif 392 }; 393 394 struct mmc_hwpart_conf { 395 struct { 396 uint enh_start; /* in 512-byte sectors */ 397 uint enh_size; /* in 512-byte sectors, if 0 no enh area */ 398 unsigned wr_rel_change : 1; 399 unsigned wr_rel_set : 1; 400 } user; 401 struct { 402 uint size; /* in 512-byte sectors */ 403 unsigned enhanced : 1; 404 unsigned wr_rel_change : 1; 405 unsigned wr_rel_set : 1; 406 } gp_part[4]; 407 }; 408 409 enum mmc_hwpart_conf_mode { 410 MMC_HWPART_CONF_CHECK, 411 MMC_HWPART_CONF_SET, 412 MMC_HWPART_CONF_COMPLETE, 413 }; 414 415 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); 416 417 /** 418 * mmc_bind() - Set up a new MMC device ready for probing 419 * 420 * A child block device is bound with the IF_TYPE_MMC interface type. This 421 * allows the device to be used with CONFIG_BLK 422 * 423 * @dev: MMC device to set up 424 * @mmc: MMC struct 425 * @cfg: MMC configuration 426 * @return 0 if OK, -ve on error 427 */ 428 int mmc_bind(struct udevice *dev, struct mmc *mmc, 429 const struct mmc_config *cfg); 430 void mmc_destroy(struct mmc *mmc); 431 432 /** 433 * mmc_unbind() - Unbind a MMC device's child block device 434 * 435 * @dev: MMC device 436 * @return 0 if OK, -ve on error 437 */ 438 int mmc_unbind(struct udevice *dev); 439 int mmc_initialize(bd_t *bis); 440 int mmc_init(struct mmc *mmc); 441 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 442 void mmc_set_clock(struct mmc *mmc, uint clock); 443 struct mmc *find_mmc_device(int dev_num); 444 int mmc_set_dev(int dev_num); 445 void print_mmc_devices(char separator); 446 int get_mmc_num(void); 447 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, 448 enum mmc_hwpart_conf_mode mode); 449 int mmc_getcd(struct mmc *mmc); 450 int board_mmc_getcd(struct mmc *mmc); 451 int mmc_getwp(struct mmc *mmc); 452 int board_mmc_getwp(struct mmc *mmc); 453 int mmc_set_dsr(struct mmc *mmc, u16 val); 454 /* Function to change the size of boot partition and rpmb partitions */ 455 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 456 unsigned long rpmbsize); 457 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ 458 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); 459 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ 460 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); 461 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ 462 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); 463 /* Functions to read / write the RPMB partition */ 464 int mmc_rpmb_set_key(struct mmc *mmc, void *key); 465 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); 466 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, 467 unsigned short cnt, unsigned char *key); 468 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, 469 unsigned short cnt, unsigned char *key); 470 /** 471 * Start device initialization and return immediately; it does not block on 472 * polling OCR (operation condition register) status. Then you should call 473 * mmc_init, which would block on polling OCR status and complete the device 474 * initializatin. 475 * 476 * @param mmc Pointer to a MMC device struct 477 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. 478 */ 479 int mmc_start_init(struct mmc *mmc); 480 481 /** 482 * Set preinit flag of mmc device. 483 * 484 * This will cause the device to be pre-inited during mmc_initialize(), 485 * which may save boot time if the device is not accessed until later. 486 * Some eMMC devices take 200-300ms to init, but unfortunately they 487 * must be sent a series of commands to even get them to start preparing 488 * for operation. 489 * 490 * @param mmc Pointer to a MMC device struct 491 * @param preinit preinit flag value 492 */ 493 void mmc_set_preinit(struct mmc *mmc, int preinit); 494 495 #ifdef CONFIG_MMC_SPI 496 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) 497 #else 498 #define mmc_host_is_spi(mmc) 0 499 #endif 500 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); 501 502 void board_mmc_power_init(void); 503 int board_mmc_init(bd_t *bis); 504 int cpu_mmc_init(bd_t *bis); 505 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); 506 int mmc_get_env_dev(void); 507 508 struct pci_device_id; 509 510 /** 511 * pci_mmc_init() - set up PCI MMC devices 512 * 513 * This finds all the matching PCI IDs and sets them up as MMC devices. 514 * 515 * @name: Name to use for devices 516 * @mmc_supported: PCI IDs to search for, terminated by {0, 0} 517 */ 518 int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported); 519 520 /* Set block count limit because of 16 bit register limit on some hardware*/ 521 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT 522 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 523 #endif 524 525 /** 526 * mmc_get_blk_desc() - Get the block descriptor for an MMC device 527 * 528 * @mmc: MMC device 529 * @return block device if found, else NULL 530 */ 531 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc); 532 533 #endif /* _MMC_H_ */ 534