183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
271f95118Swdenk /*
34a6ee172SJerry Huang * Copyright 2008,2010 Freescale Semiconductor, Inc
4272cc70bSAndy Fleming * Andy Fleming
5272cc70bSAndy Fleming *
6272cc70bSAndy Fleming * Based (loosely) on the Linux code
771f95118Swdenk */
871f95118Swdenk
971f95118Swdenk #ifndef _MMC_H_
1071f95118Swdenk #define _MMC_H_
1171f95118Swdenk
12272cc70bSAndy Fleming #include <linux/list.h>
133697e599SPeng Fan #include <linux/sizes.h>
140d986e61SLad, Prabhakar #include <linux/compiler.h>
1507a2d42cSMateusz Zalega #include <part.h>
16272cc70bSAndy Fleming
17f99c2efeSJean-Jacques Hiblot #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
18f99c2efeSJean-Jacques Hiblot #define MMC_SUPPORTS_TUNING
19f99c2efeSJean-Jacques Hiblot #endif
20f99c2efeSJean-Jacques Hiblot #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
21f99c2efeSJean-Jacques Hiblot #define MMC_SUPPORTS_TUNING
22f99c2efeSJean-Jacques Hiblot #endif
23f99c2efeSJean-Jacques Hiblot
244b7cee53SPantelis Antoniou /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
254b7cee53SPantelis Antoniou #define SD_VERSION_SD (1U << 31)
264b7cee53SPantelis Antoniou #define MMC_VERSION_MMC (1U << 30)
274b7cee53SPantelis Antoniou
284b7cee53SPantelis Antoniou #define MAKE_SDMMC_VERSION(a, b, c) \
294b7cee53SPantelis Antoniou ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
304b7cee53SPantelis Antoniou #define MAKE_SD_VERSION(a, b, c) \
314b7cee53SPantelis Antoniou (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
324b7cee53SPantelis Antoniou #define MAKE_MMC_VERSION(a, b, c) \
334b7cee53SPantelis Antoniou (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
344b7cee53SPantelis Antoniou
354b7cee53SPantelis Antoniou #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
364b7cee53SPantelis Antoniou (((u32)(x) >> 16) & 0xff)
374b7cee53SPantelis Antoniou #define EXTRACT_SDMMC_MINOR_VERSION(x) \
384b7cee53SPantelis Antoniou (((u32)(x) >> 8) & 0xff)
394b7cee53SPantelis Antoniou #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
404b7cee53SPantelis Antoniou ((u32)(x) & 0xff)
414b7cee53SPantelis Antoniou
424b7cee53SPantelis Antoniou #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
434b7cee53SPantelis Antoniou #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
444b7cee53SPantelis Antoniou #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
454b7cee53SPantelis Antoniou #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
464b7cee53SPantelis Antoniou
474b7cee53SPantelis Antoniou #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
484b7cee53SPantelis Antoniou #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
494b7cee53SPantelis Antoniou #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
504b7cee53SPantelis Antoniou #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
514b7cee53SPantelis Antoniou #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
524b7cee53SPantelis Antoniou #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
534b7cee53SPantelis Antoniou #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
544b7cee53SPantelis Antoniou #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
554b7cee53SPantelis Antoniou #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
56ace1bed3SJean-Jacques Hiblot #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
574b7cee53SPantelis Antoniou #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
584b7cee53SPantelis Antoniou #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
594b7cee53SPantelis Antoniou #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
601a3619cfSStefan Wahren #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
61272cc70bSAndy Fleming
6235f9e196SJean-Jacques Hiblot #define MMC_CAP(mode) (1 << mode)
6335f9e196SJean-Jacques Hiblot #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
6435f9e196SJean-Jacques Hiblot #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
6535f9e196SJean-Jacques Hiblot #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
66634d4849SKishon Vijay Abraham I #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
673dd2626fSPeng Fan #define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
6835f9e196SJean-Jacques Hiblot
6935f9e196SJean-Jacques Hiblot #define MMC_MODE_8BIT BIT(30)
7035f9e196SJean-Jacques Hiblot #define MMC_MODE_4BIT BIT(29)
71d0c221feSJean-Jacques Hiblot #define MMC_MODE_1BIT BIT(28)
7235f9e196SJean-Jacques Hiblot #define MMC_MODE_SPI BIT(27)
7335f9e196SJean-Jacques Hiblot
7462722036SŁukasz Majewski
75272cc70bSAndy Fleming #define SD_DATA_4BIT 0x00040000
76272cc70bSAndy Fleming
774b7cee53SPantelis Antoniou #define IS_SD(x) ((x)->version & SD_VERSION_SD)
783f2da751SAndrew Gabbasov #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
79272cc70bSAndy Fleming
80272cc70bSAndy Fleming #define MMC_DATA_READ 1
81272cc70bSAndy Fleming #define MMC_DATA_WRITE 2
82272cc70bSAndy Fleming
83341188b9SHaavard Skinnemoen #define MMC_CMD_GO_IDLE_STATE 0
84341188b9SHaavard Skinnemoen #define MMC_CMD_SEND_OP_COND 1
85341188b9SHaavard Skinnemoen #define MMC_CMD_ALL_SEND_CID 2
86341188b9SHaavard Skinnemoen #define MMC_CMD_SET_RELATIVE_ADDR 3
87341188b9SHaavard Skinnemoen #define MMC_CMD_SET_DSR 4
88272cc70bSAndy Fleming #define MMC_CMD_SWITCH 6
89341188b9SHaavard Skinnemoen #define MMC_CMD_SELECT_CARD 7
90272cc70bSAndy Fleming #define MMC_CMD_SEND_EXT_CSD 8
91341188b9SHaavard Skinnemoen #define MMC_CMD_SEND_CSD 9
92341188b9SHaavard Skinnemoen #define MMC_CMD_SEND_CID 10
93272cc70bSAndy Fleming #define MMC_CMD_STOP_TRANSMISSION 12
94341188b9SHaavard Skinnemoen #define MMC_CMD_SEND_STATUS 13
95341188b9SHaavard Skinnemoen #define MMC_CMD_SET_BLOCKLEN 16
96341188b9SHaavard Skinnemoen #define MMC_CMD_READ_SINGLE_BLOCK 17
97341188b9SHaavard Skinnemoen #define MMC_CMD_READ_MULTIPLE_BLOCK 18
98c10b85d6SJean-Jacques Hiblot #define MMC_CMD_SEND_TUNING_BLOCK 19
99634d4849SKishon Vijay Abraham I #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
10091fdabc6SPierre Aubert #define MMC_CMD_SET_BLOCK_COUNT 23
101272cc70bSAndy Fleming #define MMC_CMD_WRITE_SINGLE_BLOCK 24
102272cc70bSAndy Fleming #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
103e6f99a56SLei Wen #define MMC_CMD_ERASE_GROUP_START 35
104e6f99a56SLei Wen #define MMC_CMD_ERASE_GROUP_END 36
105e6f99a56SLei Wen #define MMC_CMD_ERASE 38
106341188b9SHaavard Skinnemoen #define MMC_CMD_APP_CMD 55
107d52ebf10SThomas Chou #define MMC_CMD_SPI_READ_OCR 58
108d52ebf10SThomas Chou #define MMC_CMD_SPI_CRC_ON_OFF 59
1093690d6d6SAmar #define MMC_CMD_RES_MAN 62
1103690d6d6SAmar
1113690d6d6SAmar #define MMC_CMD62_ARG1 0xefac62ec
1123690d6d6SAmar #define MMC_CMD62_ARG2 0xcbaea7
1133690d6d6SAmar
114341188b9SHaavard Skinnemoen
115341188b9SHaavard Skinnemoen #define SD_CMD_SEND_RELATIVE_ADDR 3
116272cc70bSAndy Fleming #define SD_CMD_SWITCH_FUNC 6
117341188b9SHaavard Skinnemoen #define SD_CMD_SEND_IF_COND 8
118f022d36eSOtavio Salvador #define SD_CMD_SWITCH_UHS18V 11
119341188b9SHaavard Skinnemoen
120341188b9SHaavard Skinnemoen #define SD_CMD_APP_SET_BUS_WIDTH 6
1213697e599SPeng Fan #define SD_CMD_APP_SD_STATUS 13
122e6f99a56SLei Wen #define SD_CMD_ERASE_WR_BLK_START 32
123e6f99a56SLei Wen #define SD_CMD_ERASE_WR_BLK_END 33
124341188b9SHaavard Skinnemoen #define SD_CMD_APP_SEND_OP_COND 41
125272cc70bSAndy Fleming #define SD_CMD_APP_SEND_SCR 51
126272cc70bSAndy Fleming
mmc_is_tuning_cmd(uint cmdidx)127634d4849SKishon Vijay Abraham I static inline bool mmc_is_tuning_cmd(uint cmdidx)
128634d4849SKishon Vijay Abraham I {
129c10b85d6SJean-Jacques Hiblot if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
130c10b85d6SJean-Jacques Hiblot (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
131634d4849SKishon Vijay Abraham I return true;
132634d4849SKishon Vijay Abraham I return false;
133634d4849SKishon Vijay Abraham I }
134634d4849SKishon Vijay Abraham I
135272cc70bSAndy Fleming /* SCR definitions in different words */
136272cc70bSAndy Fleming #define SD_HIGHSPEED_BUSY 0x00020000
137272cc70bSAndy Fleming #define SD_HIGHSPEED_SUPPORTED 0x00020000
138272cc70bSAndy Fleming
139c10b85d6SJean-Jacques Hiblot #define UHS_SDR12_BUS_SPEED 0
140c10b85d6SJean-Jacques Hiblot #define HIGH_SPEED_BUS_SPEED 1
141c10b85d6SJean-Jacques Hiblot #define UHS_SDR25_BUS_SPEED 1
142c10b85d6SJean-Jacques Hiblot #define UHS_SDR50_BUS_SPEED 2
143c10b85d6SJean-Jacques Hiblot #define UHS_SDR104_BUS_SPEED 3
144c10b85d6SJean-Jacques Hiblot #define UHS_DDR50_BUS_SPEED 4
145c10b85d6SJean-Jacques Hiblot
146c10b85d6SJean-Jacques Hiblot #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
147c10b85d6SJean-Jacques Hiblot #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
148c10b85d6SJean-Jacques Hiblot #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
149c10b85d6SJean-Jacques Hiblot #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
150c10b85d6SJean-Jacques Hiblot #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
151c10b85d6SJean-Jacques Hiblot
1520b453ffeSRabin Vincent #define OCR_BUSY 0x80000000
153272cc70bSAndy Fleming #define OCR_HCS 0x40000000
154c10b85d6SJean-Jacques Hiblot #define OCR_S18R 0x1000000
15531cacbabSRaffaele Recalcati #define OCR_VOLTAGE_MASK 0x007FFF80
15631cacbabSRaffaele Recalcati #define OCR_ACCESS_MODE 0x60000000
157272cc70bSAndy Fleming
1581aa2d074SEric Nelson #define MMC_ERASE_ARG 0x00000000
1591aa2d074SEric Nelson #define MMC_SECURE_ERASE_ARG 0x80000000
1601aa2d074SEric Nelson #define MMC_TRIM_ARG 0x00000001
1611aa2d074SEric Nelson #define MMC_DISCARD_ARG 0x00000003
1621aa2d074SEric Nelson #define MMC_SECURE_TRIM1_ARG 0x80000001
1631aa2d074SEric Nelson #define MMC_SECURE_TRIM2_ARG 0x80008000
164e6f99a56SLei Wen
1655d4fc8d9SRaffaele Recalcati #define MMC_STATUS_MASK (~0x0206BF7F)
1666b2221b0SAndrew Gabbasov #define MMC_STATUS_SWITCH_ERROR (1 << 7)
1675d4fc8d9SRaffaele Recalcati #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
1685d4fc8d9SRaffaele Recalcati #define MMC_STATUS_CURR_STATE (0xf << 9)
169ed018b21SThomas Chou #define MMC_STATUS_ERROR (1 << 19)
1705d4fc8d9SRaffaele Recalcati
171d617c426SJan Kloetzke #define MMC_STATE_PRG (7 << 9)
172d617c426SJan Kloetzke
173272cc70bSAndy Fleming #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
174272cc70bSAndy Fleming #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
175272cc70bSAndy Fleming #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
176272cc70bSAndy Fleming #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
177272cc70bSAndy Fleming #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
178272cc70bSAndy Fleming #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
179272cc70bSAndy Fleming #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
180272cc70bSAndy Fleming #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
181272cc70bSAndy Fleming #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
182272cc70bSAndy Fleming #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
183272cc70bSAndy Fleming #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
184272cc70bSAndy Fleming #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
185272cc70bSAndy Fleming #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
186272cc70bSAndy Fleming #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
187272cc70bSAndy Fleming #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
188272cc70bSAndy Fleming #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
189272cc70bSAndy Fleming #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
190272cc70bSAndy Fleming
191272cc70bSAndy Fleming #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
192272cc70bSAndy Fleming #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
193272cc70bSAndy Fleming addressed by index which are
194272cc70bSAndy Fleming 1 in value field */
195272cc70bSAndy Fleming #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
196272cc70bSAndy Fleming addressed by index, which are
197272cc70bSAndy Fleming 1 in value field */
198272cc70bSAndy Fleming #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
199272cc70bSAndy Fleming
200272cc70bSAndy Fleming #define SD_SWITCH_CHECK 0
201272cc70bSAndy Fleming #define SD_SWITCH_SWITCH 1
202272cc70bSAndy Fleming
203272cc70bSAndy Fleming /*
204272cc70bSAndy Fleming * EXT_CSD fields
205272cc70bSAndy Fleming */
206a7f852b6SDiego Santa Cruz #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
207a7f852b6SDiego Santa Cruz #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
208f866a46dSStephen Warren #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
209d7b29129SMarkus Niebel #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
2101937e5aaSOliver Metz #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
211ac9da0e0SDiego Santa Cruz #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
2120560db18SLei Wen #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
21333ace362STom Rini #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
214cd3d4880STomas Melin #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
2158dda5b0eSDiego Santa Cruz #define EXT_CSD_WR_REL_PARAM 166 /* R */
2168dda5b0eSDiego Santa Cruz #define EXT_CSD_WR_REL_SET 167 /* R/W */
217f866a46dSStephen Warren #define EXT_CSD_RPMB_MULT 168 /* RO */
2180560db18SLei Wen #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
2193690d6d6SAmar #define EXT_CSD_BOOT_BUS_WIDTH 177
220bc897b1dSLei Wen #define EXT_CSD_PART_CONF 179 /* R/W */
221272cc70bSAndy Fleming #define EXT_CSD_BUS_WIDTH 183 /* R/W */
222272cc70bSAndy Fleming #define EXT_CSD_HS_TIMING 185 /* R/W */
223272cc70bSAndy Fleming #define EXT_CSD_REV 192 /* RO */
2240560db18SLei Wen #define EXT_CSD_CARD_TYPE 196 /* RO */
225272cc70bSAndy Fleming #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
226f866a46dSStephen Warren #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
2270560db18SLei Wen #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
2288948ea83SStephen Warren #define EXT_CSD_BOOT_MULT 226 /* RO */
229cd3d4880STomas Melin #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
230272cc70bSAndy Fleming
231272cc70bSAndy Fleming /*
232272cc70bSAndy Fleming * EXT_CSD field definitions
233272cc70bSAndy Fleming */
234272cc70bSAndy Fleming
235272cc70bSAndy Fleming #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
236272cc70bSAndy Fleming #define EXT_CSD_CMD_SET_SECURE (1 << 1)
237272cc70bSAndy Fleming #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
238272cc70bSAndy Fleming
239272cc70bSAndy Fleming #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
240272cc70bSAndy Fleming #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
241d22e3d46SJaehoon Chung #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
242d22e3d46SJaehoon Chung #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
243d22e3d46SJaehoon Chung #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
244d22e3d46SJaehoon Chung | EXT_CSD_CARD_TYPE_DDR_1_2V)
245272cc70bSAndy Fleming
246634d4849SKishon Vijay Abraham I #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
247634d4849SKishon Vijay Abraham I /* SDR mode @1.8V I/O */
248634d4849SKishon Vijay Abraham I #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
249634d4849SKishon Vijay Abraham I /* SDR mode @1.2V I/O */
250634d4849SKishon Vijay Abraham I #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
251634d4849SKishon Vijay Abraham I EXT_CSD_CARD_TYPE_HS200_1_2V)
2523dd2626fSPeng Fan #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
2533dd2626fSPeng Fan #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
2543dd2626fSPeng Fan #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
2553dd2626fSPeng Fan EXT_CSD_CARD_TYPE_HS400_1_2V)
256634d4849SKishon Vijay Abraham I
257272cc70bSAndy Fleming #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
258272cc70bSAndy Fleming #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
259272cc70bSAndy Fleming #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
260d22e3d46SJaehoon Chung #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
261d22e3d46SJaehoon Chung #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
2623862b854SJean-Jacques Hiblot #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
263341188b9SHaavard Skinnemoen
2643862b854SJean-Jacques Hiblot #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
2653862b854SJean-Jacques Hiblot #define EXT_CSD_TIMING_HS 1 /* HS */
266634d4849SKishon Vijay Abraham I #define EXT_CSD_TIMING_HS200 2 /* HS200 */
2673dd2626fSPeng Fan #define EXT_CSD_TIMING_HS400 3 /* HS400 */
268634d4849SKishon Vijay Abraham I
2693690d6d6SAmar #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
2703690d6d6SAmar #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
2713690d6d6SAmar #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
2723690d6d6SAmar #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
2733690d6d6SAmar
2743690d6d6SAmar #define EXT_CSD_BOOT_ACK(x) (x << 6)
2753690d6d6SAmar #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
2763690d6d6SAmar #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
2773690d6d6SAmar
278bdb60996SAngelo Dureghello #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
279bdb60996SAngelo Dureghello #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
280bdb60996SAngelo Dureghello #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
281bdb60996SAngelo Dureghello
2825a99b9deSTom Rini #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
2835a99b9deSTom Rini #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
2845a99b9deSTom Rini #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
2853690d6d6SAmar
286d7b29129SMarkus Niebel #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
287d7b29129SMarkus Niebel
288c3dbb4f9SDiego Santa Cruz #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
289c3dbb4f9SDiego Santa Cruz #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
290c3dbb4f9SDiego Santa Cruz
2918dda5b0eSDiego Santa Cruz #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
2928dda5b0eSDiego Santa Cruz
2938dda5b0eSDiego Santa Cruz #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
2948dda5b0eSDiego Santa Cruz #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
2958dda5b0eSDiego Santa Cruz
2961de97f98SAndy Fleming #define R1_ILLEGAL_COMMAND (1 << 22)
2971de97f98SAndy Fleming #define R1_APP_CMD (1 << 5)
2981de97f98SAndy Fleming
299272cc70bSAndy Fleming #define MMC_RSP_PRESENT (1 << 0)
300272cc70bSAndy Fleming #define MMC_RSP_136 (1 << 1) /* 136 bit response */
301272cc70bSAndy Fleming #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
302272cc70bSAndy Fleming #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
303272cc70bSAndy Fleming #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
304272cc70bSAndy Fleming
305272cc70bSAndy Fleming #define MMC_RSP_NONE (0)
306272cc70bSAndy Fleming #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
307272cc70bSAndy Fleming #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
308272cc70bSAndy Fleming MMC_RSP_BUSY)
309272cc70bSAndy Fleming #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
310272cc70bSAndy Fleming #define MMC_RSP_R3 (MMC_RSP_PRESENT)
311272cc70bSAndy Fleming #define MMC_RSP_R4 (MMC_RSP_PRESENT)
312272cc70bSAndy Fleming #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
313272cc70bSAndy Fleming #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
314272cc70bSAndy Fleming #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
315272cc70bSAndy Fleming
316bc897b1dSLei Wen #define MMCPART_NOAVAILABLE (0xff)
317bc897b1dSLei Wen #define PART_ACCESS_MASK (0x7)
318bc897b1dSLei Wen #define PART_SUPPORT (0x1)
319c3dbb4f9SDiego Santa Cruz #define ENHNCD_SUPPORT (0x2)
3201937e5aaSOliver Metz #define PART_ENH_ATTRIB (0x1f)
32171f95118Swdenk
32283dc4227SKishon Vijay Abraham I #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
32383dc4227SKishon Vijay Abraham I #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
32483dc4227SKishon Vijay Abraham I
325aff5d3c8SKishon Vijay Abraham I enum mmc_voltage {
326aff5d3c8SKishon Vijay Abraham I MMC_SIGNAL_VOLTAGE_000 = 0,
327bc1e3272SJean-Jacques Hiblot MMC_SIGNAL_VOLTAGE_120 = 1,
328bc1e3272SJean-Jacques Hiblot MMC_SIGNAL_VOLTAGE_180 = 2,
329bc1e3272SJean-Jacques Hiblot MMC_SIGNAL_VOLTAGE_330 = 4,
330aff5d3c8SKishon Vijay Abraham I };
331aff5d3c8SKishon Vijay Abraham I
332bc1e3272SJean-Jacques Hiblot #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
333bc1e3272SJean-Jacques Hiblot MMC_SIGNAL_VOLTAGE_180 |\
334bc1e3272SJean-Jacques Hiblot MMC_SIGNAL_VOLTAGE_330)
335bc1e3272SJean-Jacques Hiblot
3368bfa195eSSimon Glass /* Maximum block size for MMC */
3378bfa195eSSimon Glass #define MMC_MAX_BLOCK_LEN 512
3388bfa195eSSimon Glass
3393690d6d6SAmar /* The number of MMC physical partitions. These consist of:
3403690d6d6SAmar * boot partitions (2), general purpose partitions (4) in MMC v4.4.
3413690d6d6SAmar */
3423690d6d6SAmar #define MMC_NUM_BOOT_PARTITION 2
34391fdabc6SPierre Aubert #define MMC_PART_RPMB 3 /* RPMB partition number */
3443690d6d6SAmar
345e7ecf7cbSSimon Glass /* Driver model support */
346e7ecf7cbSSimon Glass
347e7ecf7cbSSimon Glass /**
348e7ecf7cbSSimon Glass * struct mmc_uclass_priv - Holds information about a device used by the uclass
349e7ecf7cbSSimon Glass */
350e7ecf7cbSSimon Glass struct mmc_uclass_priv {
351e7ecf7cbSSimon Glass struct mmc *mmc;
352e7ecf7cbSSimon Glass };
353e7ecf7cbSSimon Glass
354e7ecf7cbSSimon Glass /**
355e7ecf7cbSSimon Glass * mmc_get_mmc_dev() - get the MMC struct pointer for a device
356e7ecf7cbSSimon Glass *
357e7ecf7cbSSimon Glass * Provided that the device is already probed and ready for use, this value
358e7ecf7cbSSimon Glass * will be available.
359e7ecf7cbSSimon Glass *
360e7ecf7cbSSimon Glass * @dev: Device
361e7ecf7cbSSimon Glass * @return associated mmc struct pointer if available, else NULL
362e7ecf7cbSSimon Glass */
363e7ecf7cbSSimon Glass struct mmc *mmc_get_mmc_dev(struct udevice *dev);
364e7ecf7cbSSimon Glass
365e7ecf7cbSSimon Glass /* End of driver model support */
366e7ecf7cbSSimon Glass
3671de97f98SAndy Fleming struct mmc_cid {
3681de97f98SAndy Fleming unsigned long psn;
3691de97f98SAndy Fleming unsigned short oid;
3701de97f98SAndy Fleming unsigned char mid;
3711de97f98SAndy Fleming unsigned char prv;
3721de97f98SAndy Fleming unsigned char mdt;
3731de97f98SAndy Fleming char pnm[7];
3741de97f98SAndy Fleming };
3751de97f98SAndy Fleming
376272cc70bSAndy Fleming struct mmc_cmd {
377272cc70bSAndy Fleming ushort cmdidx;
378272cc70bSAndy Fleming uint resp_type;
379272cc70bSAndy Fleming uint cmdarg;
3800b453ffeSRabin Vincent uint response[4];
381272cc70bSAndy Fleming };
382272cc70bSAndy Fleming
383272cc70bSAndy Fleming struct mmc_data {
384272cc70bSAndy Fleming union {
385272cc70bSAndy Fleming char *dest;
386272cc70bSAndy Fleming const char *src; /* src buffers don't get written to */
387272cc70bSAndy Fleming };
388272cc70bSAndy Fleming uint flags;
389272cc70bSAndy Fleming uint blocks;
390272cc70bSAndy Fleming uint blocksize;
391272cc70bSAndy Fleming };
392272cc70bSAndy Fleming
393ab769f22SPantelis Antoniou /* forward decl. */
394ab769f22SPantelis Antoniou struct mmc;
395ab769f22SPantelis Antoniou
396e7881d85SSimon Glass #if CONFIG_IS_ENABLED(DM_MMC)
3978ca51e51SSimon Glass struct dm_mmc_ops {
3988ca51e51SSimon Glass /**
3998ca51e51SSimon Glass * send_cmd() - Send a command to the MMC device
4008ca51e51SSimon Glass *
4018ca51e51SSimon Glass * @dev: Device to receive the command
4028ca51e51SSimon Glass * @cmd: Command to send
4038ca51e51SSimon Glass * @data: Additional data to send/receive
4048ca51e51SSimon Glass * @return 0 if OK, -ve on error
4058ca51e51SSimon Glass */
4068ca51e51SSimon Glass int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
4078ca51e51SSimon Glass struct mmc_data *data);
4088ca51e51SSimon Glass
4098ca51e51SSimon Glass /**
4108ca51e51SSimon Glass * set_ios() - Set the I/O speed/width for an MMC device
4118ca51e51SSimon Glass *
4128ca51e51SSimon Glass * @dev: Device to update
4138ca51e51SSimon Glass * @return 0 if OK, -ve on error
4148ca51e51SSimon Glass */
4158ca51e51SSimon Glass int (*set_ios)(struct udevice *dev);
4168ca51e51SSimon Glass
4178ca51e51SSimon Glass /**
418318a7a57SJean-Jacques Hiblot * send_init_stream() - send the initialization stream: 74 clock cycles
419318a7a57SJean-Jacques Hiblot * This is used after power up before sending the first command
420318a7a57SJean-Jacques Hiblot *
421318a7a57SJean-Jacques Hiblot * @dev: Device to update
422318a7a57SJean-Jacques Hiblot */
423318a7a57SJean-Jacques Hiblot void (*send_init_stream)(struct udevice *dev);
424318a7a57SJean-Jacques Hiblot
425318a7a57SJean-Jacques Hiblot /**
4268ca51e51SSimon Glass * get_cd() - See whether a card is present
4278ca51e51SSimon Glass *
4288ca51e51SSimon Glass * @dev: Device to check
4298ca51e51SSimon Glass * @return 0 if not present, 1 if present, -ve on error
4308ca51e51SSimon Glass */
4318ca51e51SSimon Glass int (*get_cd)(struct udevice *dev);
4328ca51e51SSimon Glass
4338ca51e51SSimon Glass /**
4348ca51e51SSimon Glass * get_wp() - See whether a card has write-protect enabled
4358ca51e51SSimon Glass *
4368ca51e51SSimon Glass * @dev: Device to check
4378ca51e51SSimon Glass * @return 0 if write-enabled, 1 if write-protected, -ve on error
4388ca51e51SSimon Glass */
4398ca51e51SSimon Glass int (*get_wp)(struct udevice *dev);
440ec841209SKishon Vijay Abraham I
441f99c2efeSJean-Jacques Hiblot #ifdef MMC_SUPPORTS_TUNING
442ec841209SKishon Vijay Abraham I /**
443ec841209SKishon Vijay Abraham I * execute_tuning() - Start the tuning process
444ec841209SKishon Vijay Abraham I *
445ec841209SKishon Vijay Abraham I * @dev: Device to start the tuning
446ec841209SKishon Vijay Abraham I * @opcode: Command opcode to send
447ec841209SKishon Vijay Abraham I * @return 0 if OK, -ve on error
448ec841209SKishon Vijay Abraham I */
449ec841209SKishon Vijay Abraham I int (*execute_tuning)(struct udevice *dev, uint opcode);
450f99c2efeSJean-Jacques Hiblot #endif
451c10b85d6SJean-Jacques Hiblot
452f99c2efeSJean-Jacques Hiblot #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
453c10b85d6SJean-Jacques Hiblot /**
454c10b85d6SJean-Jacques Hiblot * wait_dat0() - wait until dat0 is in the target state
455c10b85d6SJean-Jacques Hiblot * (CLK must be running during the wait)
456c10b85d6SJean-Jacques Hiblot *
457c10b85d6SJean-Jacques Hiblot * @dev: Device to check
458c10b85d6SJean-Jacques Hiblot * @state: target state
459c10b85d6SJean-Jacques Hiblot * @timeout: timeout in us
460c10b85d6SJean-Jacques Hiblot * @return 0 if dat0 is in the target state, -ve on error
461c10b85d6SJean-Jacques Hiblot */
462c10b85d6SJean-Jacques Hiblot int (*wait_dat0)(struct udevice *dev, int state, int timeout);
463f99c2efeSJean-Jacques Hiblot #endif
4648ca51e51SSimon Glass };
4658ca51e51SSimon Glass
4668ca51e51SSimon Glass #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
4678ca51e51SSimon Glass
4688ca51e51SSimon Glass int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
4698ca51e51SSimon Glass struct mmc_data *data);
4708ca51e51SSimon Glass int dm_mmc_set_ios(struct udevice *dev);
471318a7a57SJean-Jacques Hiblot void dm_mmc_send_init_stream(struct udevice *dev);
4728ca51e51SSimon Glass int dm_mmc_get_cd(struct udevice *dev);
4738ca51e51SSimon Glass int dm_mmc_get_wp(struct udevice *dev);
474ec841209SKishon Vijay Abraham I int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
475c10b85d6SJean-Jacques Hiblot int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
4768ca51e51SSimon Glass
4778ca51e51SSimon Glass /* Transition functions for compatibility */
4788ca51e51SSimon Glass int mmc_set_ios(struct mmc *mmc);
479318a7a57SJean-Jacques Hiblot void mmc_send_init_stream(struct mmc *mmc);
4808ca51e51SSimon Glass int mmc_getcd(struct mmc *mmc);
4818ca51e51SSimon Glass int mmc_getwp(struct mmc *mmc);
482ec841209SKishon Vijay Abraham I int mmc_execute_tuning(struct mmc *mmc, uint opcode);
483c10b85d6SJean-Jacques Hiblot int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
4848ca51e51SSimon Glass
4858ca51e51SSimon Glass #else
486ab769f22SPantelis Antoniou struct mmc_ops {
487ab769f22SPantelis Antoniou int (*send_cmd)(struct mmc *mmc,
488ab769f22SPantelis Antoniou struct mmc_cmd *cmd, struct mmc_data *data);
48907b0b9c0SJaehoon Chung int (*set_ios)(struct mmc *mmc);
490ab769f22SPantelis Antoniou int (*init)(struct mmc *mmc);
491ab769f22SPantelis Antoniou int (*getcd)(struct mmc *mmc);
492ab769f22SPantelis Antoniou int (*getwp)(struct mmc *mmc);
493ab769f22SPantelis Antoniou };
4948ca51e51SSimon Glass #endif
495ab769f22SPantelis Antoniou
49693bfd616SPantelis Antoniou struct mmc_config {
49793bfd616SPantelis Antoniou const char *name;
498e7881d85SSimon Glass #if !CONFIG_IS_ENABLED(DM_MMC)
49993bfd616SPantelis Antoniou const struct mmc_ops *ops;
5008ca51e51SSimon Glass #endif
50193bfd616SPantelis Antoniou uint host_caps;
502272cc70bSAndy Fleming uint voltages;
503272cc70bSAndy Fleming uint f_min;
504272cc70bSAndy Fleming uint f_max;
50593bfd616SPantelis Antoniou uint b_max;
50693bfd616SPantelis Antoniou unsigned char part_type;
50793bfd616SPantelis Antoniou };
50893bfd616SPantelis Antoniou
5093697e599SPeng Fan struct sd_ssr {
5103697e599SPeng Fan unsigned int au; /* In sectors */
5113697e599SPeng Fan unsigned int erase_timeout; /* In milliseconds */
5123697e599SPeng Fan unsigned int erase_offset; /* In milliseconds */
5133697e599SPeng Fan };
5143697e599SPeng Fan
51535f9e196SJean-Jacques Hiblot enum bus_mode {
51635f9e196SJean-Jacques Hiblot MMC_LEGACY,
51735f9e196SJean-Jacques Hiblot SD_LEGACY,
51835f9e196SJean-Jacques Hiblot MMC_HS,
51935f9e196SJean-Jacques Hiblot SD_HS,
520f99c2efeSJean-Jacques Hiblot MMC_HS_52,
521f99c2efeSJean-Jacques Hiblot MMC_DDR_52,
52235f9e196SJean-Jacques Hiblot UHS_SDR12,
52335f9e196SJean-Jacques Hiblot UHS_SDR25,
52435f9e196SJean-Jacques Hiblot UHS_SDR50,
52535f9e196SJean-Jacques Hiblot UHS_DDR50,
526f99c2efeSJean-Jacques Hiblot UHS_SDR104,
52735f9e196SJean-Jacques Hiblot MMC_HS_200,
5283dd2626fSPeng Fan MMC_HS_400,
52935f9e196SJean-Jacques Hiblot MMC_MODES_END
53035f9e196SJean-Jacques Hiblot };
53135f9e196SJean-Jacques Hiblot
53235f9e196SJean-Jacques Hiblot const char *mmc_mode_name(enum bus_mode mode);
5334c9d2aaaSJean-Jacques Hiblot void mmc_dump_capabilities(const char *text, uint caps);
53435f9e196SJean-Jacques Hiblot
mmc_is_mode_ddr(enum bus_mode mode)5353862b854SJean-Jacques Hiblot static inline bool mmc_is_mode_ddr(enum bus_mode mode)
5363862b854SJean-Jacques Hiblot {
537f99c2efeSJean-Jacques Hiblot if (mode == MMC_DDR_52)
5383862b854SJean-Jacques Hiblot return true;
539f99c2efeSJean-Jacques Hiblot #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
540f99c2efeSJean-Jacques Hiblot else if (mode == UHS_DDR50)
541f99c2efeSJean-Jacques Hiblot return true;
542f99c2efeSJean-Jacques Hiblot #endif
5433dd2626fSPeng Fan #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
5443dd2626fSPeng Fan else if (mode == MMC_HS_400)
5453dd2626fSPeng Fan return true;
5463dd2626fSPeng Fan #endif
5473862b854SJean-Jacques Hiblot else
5483862b854SJean-Jacques Hiblot return false;
5493862b854SJean-Jacques Hiblot }
5503862b854SJean-Jacques Hiblot
551c10b85d6SJean-Jacques Hiblot #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
552c10b85d6SJean-Jacques Hiblot MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
553c10b85d6SJean-Jacques Hiblot MMC_CAP(UHS_DDR50))
554c10b85d6SJean-Jacques Hiblot
supports_uhs(uint caps)555c10b85d6SJean-Jacques Hiblot static inline bool supports_uhs(uint caps)
556c10b85d6SJean-Jacques Hiblot {
557f99c2efeSJean-Jacques Hiblot #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
558c10b85d6SJean-Jacques Hiblot return (caps & UHS_CAPS) ? true : false;
559f99c2efeSJean-Jacques Hiblot #else
560f99c2efeSJean-Jacques Hiblot return false;
561f99c2efeSJean-Jacques Hiblot #endif
562c10b85d6SJean-Jacques Hiblot }
563c10b85d6SJean-Jacques Hiblot
5648ca51e51SSimon Glass /*
5658ca51e51SSimon Glass * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
5668ca51e51SSimon Glass * with mmc_get_mmc_dev().
5678ca51e51SSimon Glass *
5688ca51e51SSimon Glass * TODO struct mmc should be in mmc_private but it's hard to fix right now
5698ca51e51SSimon Glass */
57093bfd616SPantelis Antoniou struct mmc {
571c4d660d4SSimon Glass #if !CONFIG_IS_ENABLED(BLK)
57293bfd616SPantelis Antoniou struct list_head link;
57333fb211dSSimon Glass #endif
57493bfd616SPantelis Antoniou const struct mmc_config *cfg; /* provided configuration */
57593bfd616SPantelis Antoniou uint version;
57693bfd616SPantelis Antoniou void *priv;
57793bfd616SPantelis Antoniou uint has_init;
578272cc70bSAndy Fleming int high_capacity;
57935f67820SKishon Vijay Abraham I bool clk_disable; /* true if the clock can be turned off */
580272cc70bSAndy Fleming uint bus_width;
581272cc70bSAndy Fleming uint clock;
582aff5d3c8SKishon Vijay Abraham I enum mmc_voltage signal_voltage;
583272cc70bSAndy Fleming uint card_caps;
58404a2ea24SJean-Jacques Hiblot uint host_caps;
585272cc70bSAndy Fleming uint ocr;
586ab71188cSMarkus Niebel uint dsr;
587ab71188cSMarkus Niebel uint dsr_imp;
588272cc70bSAndy Fleming uint scr[2];
589272cc70bSAndy Fleming uint csd[4];
5900b453ffeSRabin Vincent uint cid[4];
591272cc70bSAndy Fleming ushort rca;
592c3dbb4f9SDiego Santa Cruz u8 part_support;
593c3dbb4f9SDiego Santa Cruz u8 part_attr;
5949e41a00bSDiego Santa Cruz u8 wr_rel_set;
5957ca0d3ddSTom Rini u8 part_config;
596272cc70bSAndy Fleming uint tran_speed;
59735f9e196SJean-Jacques Hiblot uint legacy_speed; /* speed for the legacy mode provided by the card */
598272cc70bSAndy Fleming uint read_bl_len;
599e6fa5a54SJean-Jacques Hiblot #if CONFIG_IS_ENABLED(MMC_WRITE)
600272cc70bSAndy Fleming uint write_bl_len;
601a4ff9f83SDiego Santa Cruz uint erase_grp_size; /* in 512-byte sectors */
602e6fa5a54SJean-Jacques Hiblot #endif
603b7a6e2c9SJean-Jacques Hiblot #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
604037dc0abSDiego Santa Cruz uint hc_wp_grp_size; /* in 512-byte sectors */
605b7a6e2c9SJean-Jacques Hiblot #endif
6065b2e72f3SJean-Jacques Hiblot #if CONFIG_IS_ENABLED(MMC_WRITE)
6073697e599SPeng Fan struct sd_ssr ssr; /* SD status register */
6085b2e72f3SJean-Jacques Hiblot #endif
609272cc70bSAndy Fleming u64 capacity;
610f866a46dSStephen Warren u64 capacity_user;
611f866a46dSStephen Warren u64 capacity_boot;
612f866a46dSStephen Warren u64 capacity_rpmb;
613f866a46dSStephen Warren u64 capacity_gp[4];
614173c06dfSJean-Jacques Hiblot #ifndef CONFIG_SPL_BUILD
615a7f852b6SDiego Santa Cruz u64 enh_user_start;
616a7f852b6SDiego Santa Cruz u64 enh_user_size;
617173c06dfSJean-Jacques Hiblot #endif
618c4d660d4SSimon Glass #if !CONFIG_IS_ENABLED(BLK)
6194101f687SSimon Glass struct blk_desc block_dev;
62033fb211dSSimon Glass #endif
621e9550449SChe-Liang Chiou char op_cond_pending; /* 1 if we are waiting on an op_cond command */
622e9550449SChe-Liang Chiou char init_in_progress; /* 1 if we have done mmc_start_init() */
623e9550449SChe-Liang Chiou char preinit; /* start init as early as possible */
624786e8f81SAndrew Gabbasov int ddr_mode;
625c4d660d4SSimon Glass #if CONFIG_IS_ENABLED(DM_MMC)
626cffe5d86SSimon Glass struct udevice *dev; /* Device for this MMC controller */
62706ec045fSJean-Jacques Hiblot #if CONFIG_IS_ENABLED(DM_REGULATOR)
62806ec045fSJean-Jacques Hiblot struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
62906ec045fSJean-Jacques Hiblot struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
63006ec045fSJean-Jacques Hiblot #endif
631cffe5d86SSimon Glass #endif
632dfda9d88SJean-Jacques Hiblot u8 *ext_csd;
633bc1e3272SJean-Jacques Hiblot u32 cardtype; /* cardtype read from the MMC */
634bc1e3272SJean-Jacques Hiblot enum mmc_voltage current_voltage;
63501298da3SJean-Jacques Hiblot enum bus_mode selected_mode; /* mode currently used */
63601298da3SJean-Jacques Hiblot enum bus_mode best_mode; /* best mode is the supported mode with the
63701298da3SJean-Jacques Hiblot * highest bandwidth. It may not always be the
63801298da3SJean-Jacques Hiblot * operating mode due to limitations when
63901298da3SJean-Jacques Hiblot * accessing the boot partitions
64001298da3SJean-Jacques Hiblot */
64183dc4227SKishon Vijay Abraham I u32 quirks;
642*730fd353SChin-Ting Kuo int drv_type;
643272cc70bSAndy Fleming };
644272cc70bSAndy Fleming
645ac9da0e0SDiego Santa Cruz struct mmc_hwpart_conf {
646ac9da0e0SDiego Santa Cruz struct {
647ac9da0e0SDiego Santa Cruz uint enh_start; /* in 512-byte sectors */
648ac9da0e0SDiego Santa Cruz uint enh_size; /* in 512-byte sectors, if 0 no enh area */
6498dda5b0eSDiego Santa Cruz unsigned wr_rel_change : 1;
6508dda5b0eSDiego Santa Cruz unsigned wr_rel_set : 1;
651ac9da0e0SDiego Santa Cruz } user;
652ac9da0e0SDiego Santa Cruz struct {
653ac9da0e0SDiego Santa Cruz uint size; /* in 512-byte sectors */
6548dda5b0eSDiego Santa Cruz unsigned enhanced : 1;
6558dda5b0eSDiego Santa Cruz unsigned wr_rel_change : 1;
6568dda5b0eSDiego Santa Cruz unsigned wr_rel_set : 1;
657ac9da0e0SDiego Santa Cruz } gp_part[4];
658ac9da0e0SDiego Santa Cruz };
659ac9da0e0SDiego Santa Cruz
660ac9da0e0SDiego Santa Cruz enum mmc_hwpart_conf_mode {
661ac9da0e0SDiego Santa Cruz MMC_HWPART_CONF_CHECK,
662ac9da0e0SDiego Santa Cruz MMC_HWPART_CONF_SET,
663ac9da0e0SDiego Santa Cruz MMC_HWPART_CONF_COMPLETE,
664ac9da0e0SDiego Santa Cruz };
665ac9da0e0SDiego Santa Cruz
66693bfd616SPantelis Antoniou struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
667ad27dd5eSSimon Glass
668ad27dd5eSSimon Glass /**
669ad27dd5eSSimon Glass * mmc_bind() - Set up a new MMC device ready for probing
670ad27dd5eSSimon Glass *
671ad27dd5eSSimon Glass * A child block device is bound with the IF_TYPE_MMC interface type. This
672ad27dd5eSSimon Glass * allows the device to be used with CONFIG_BLK
673ad27dd5eSSimon Glass *
674ad27dd5eSSimon Glass * @dev: MMC device to set up
675ad27dd5eSSimon Glass * @mmc: MMC struct
676ad27dd5eSSimon Glass * @cfg: MMC configuration
677ad27dd5eSSimon Glass * @return 0 if OK, -ve on error
678ad27dd5eSSimon Glass */
679ad27dd5eSSimon Glass int mmc_bind(struct udevice *dev, struct mmc *mmc,
680ad27dd5eSSimon Glass const struct mmc_config *cfg);
68193bfd616SPantelis Antoniou void mmc_destroy(struct mmc *mmc);
682ad27dd5eSSimon Glass
683ad27dd5eSSimon Glass /**
684ad27dd5eSSimon Glass * mmc_unbind() - Unbind a MMC device's child block device
685ad27dd5eSSimon Glass *
686ad27dd5eSSimon Glass * @dev: MMC device
687ad27dd5eSSimon Glass * @return 0 if OK, -ve on error
688ad27dd5eSSimon Glass */
689ad27dd5eSSimon Glass int mmc_unbind(struct udevice *dev);
690272cc70bSAndy Fleming int mmc_initialize(bd_t *bis);
691272cc70bSAndy Fleming int mmc_init(struct mmc *mmc);
6929815e3baSJean-Jacques Hiblot int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
6937abff2c3SJean-Jacques Hiblot
694fceea992SMarek Vasut #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
695fceea992SMarek Vasut CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
696fceea992SMarek Vasut CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
697fceea992SMarek Vasut int mmc_deinit(struct mmc *mmc);
698fceea992SMarek Vasut #endif
699fceea992SMarek Vasut
7007abff2c3SJean-Jacques Hiblot /**
7017abff2c3SJean-Jacques Hiblot * mmc_of_parse() - Parse the device tree to get the capabilities of the host
7027abff2c3SJean-Jacques Hiblot *
7037abff2c3SJean-Jacques Hiblot * @dev: MMC device
7047abff2c3SJean-Jacques Hiblot * @cfg: MMC configuration
7057abff2c3SJean-Jacques Hiblot * @return 0 if OK, -ve on error
7067abff2c3SJean-Jacques Hiblot */
7077abff2c3SJean-Jacques Hiblot int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
7087abff2c3SJean-Jacques Hiblot
709272cc70bSAndy Fleming int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
71035f67820SKishon Vijay Abraham I
71135f67820SKishon Vijay Abraham I /**
712bc1e3272SJean-Jacques Hiblot * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
713bc1e3272SJean-Jacques Hiblot *
714bc1e3272SJean-Jacques Hiblot * @voltage: The mmc_voltage to convert
715bc1e3272SJean-Jacques Hiblot * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
716bc1e3272SJean-Jacques Hiblot */
717bc1e3272SJean-Jacques Hiblot int mmc_voltage_to_mv(enum mmc_voltage voltage);
718bc1e3272SJean-Jacques Hiblot
719bc1e3272SJean-Jacques Hiblot /**
72035f67820SKishon Vijay Abraham I * mmc_set_clock() - change the bus clock
72135f67820SKishon Vijay Abraham I * @mmc: MMC struct
72235f67820SKishon Vijay Abraham I * @clock: bus frequency in Hz
72335f67820SKishon Vijay Abraham I * @disable: flag indicating if the clock must on or off
72435f67820SKishon Vijay Abraham I * @return 0 if OK, -ve on error
72535f67820SKishon Vijay Abraham I */
72635f67820SKishon Vijay Abraham I int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
72735f67820SKishon Vijay Abraham I
72865117182SJaehoon Chung #define MMC_CLK_ENABLE false
72965117182SJaehoon Chung #define MMC_CLK_DISABLE true
73065117182SJaehoon Chung
731272cc70bSAndy Fleming struct mmc *find_mmc_device(int dev_num);
73289716964SSteve Sakoman int mmc_set_dev(int dev_num);
733272cc70bSAndy Fleming void print_mmc_devices(char separator);
73446683f3dSKever Yang
73546683f3dSKever Yang /**
73646683f3dSKever Yang * get_mmc_num() - get the total MMC device number
73746683f3dSKever Yang *
73846683f3dSKever Yang * @return 0 if there is no MMC device, else the number of devices
73946683f3dSKever Yang */
740ea6ebe21SLei Wen int get_mmc_num(void);
741b5b838f1SMarek Vasut int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
742ac9da0e0SDiego Santa Cruz int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
743ac9da0e0SDiego Santa Cruz enum mmc_hwpart_conf_mode mode);
7448ca51e51SSimon Glass
745e7881d85SSimon Glass #if !CONFIG_IS_ENABLED(DM_MMC)
74648972d90SThierry Reding int mmc_getcd(struct mmc *mmc);
747750121c3SJeroen Hofstee int board_mmc_getcd(struct mmc *mmc);
748d23d8d7eSNikita Kiryanov int mmc_getwp(struct mmc *mmc);
749750121c3SJeroen Hofstee int board_mmc_getwp(struct mmc *mmc);
7508ca51e51SSimon Glass #endif
7518ca51e51SSimon Glass
752ab71188cSMarkus Niebel int mmc_set_dsr(struct mmc *mmc, u16 val);
7533690d6d6SAmar /* Function to change the size of boot partition and rpmb partitions */
7543690d6d6SAmar int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
7553690d6d6SAmar unsigned long rpmbsize);
756792970b0STom Rini /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
757792970b0STom Rini int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
7585a99b9deSTom Rini /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
7595a99b9deSTom Rini int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
76033ace362STom Rini /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
76133ace362STom Rini int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
76291fdabc6SPierre Aubert /* Functions to read / write the RPMB partition */
76391fdabc6SPierre Aubert int mmc_rpmb_set_key(struct mmc *mmc, void *key);
76491fdabc6SPierre Aubert int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
76591fdabc6SPierre Aubert int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
76691fdabc6SPierre Aubert unsigned short cnt, unsigned char *key);
76791fdabc6SPierre Aubert int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
76891fdabc6SPierre Aubert unsigned short cnt, unsigned char *key);
7694853ad3eSJens Wiklander
7704853ad3eSJens Wiklander /**
7714853ad3eSJens Wiklander * mmc_rpmb_route_frames() - route RPMB data frames
7724853ad3eSJens Wiklander * @mmc Pointer to a MMC device struct
7734853ad3eSJens Wiklander * @req Request data frames
7744853ad3eSJens Wiklander * @reqlen Length of data frames in bytes
7754853ad3eSJens Wiklander * @rsp Supplied buffer for response data frames
7764853ad3eSJens Wiklander * @rsplen Length of supplied buffer for response data frames
7774853ad3eSJens Wiklander *
7784853ad3eSJens Wiklander * The RPMB data frames are routed to/from some external entity, for
7794853ad3eSJens Wiklander * example a Trusted Exectuion Environment in an arm TrustZone protected
7804853ad3eSJens Wiklander * secure world. It's expected that it's the external entity who is in
7814853ad3eSJens Wiklander * control of the RPMB key.
7824853ad3eSJens Wiklander *
7834853ad3eSJens Wiklander * Returns 0 on success, < 0 on error.
7844853ad3eSJens Wiklander */
7854853ad3eSJens Wiklander int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
7864853ad3eSJens Wiklander void *rsp, unsigned long rsplen);
7874853ad3eSJens Wiklander
788cd3d4880STomas Melin #ifdef CONFIG_CMD_BKOPS_ENABLE
789cd3d4880STomas Melin int mmc_set_bkops_enable(struct mmc *mmc);
790cd3d4880STomas Melin #endif
791cd3d4880STomas Melin
792e9550449SChe-Liang Chiou /**
793e9550449SChe-Liang Chiou * Start device initialization and return immediately; it does not block on
7946c09eba5SJon Nettleton * polling OCR (operation condition register) status. Useful for checking
7956c09eba5SJon Nettleton * the presence of SD/eMMC when no card detect logic is available.
7966c09eba5SJon Nettleton *
7976c09eba5SJon Nettleton * @param mmc Pointer to a MMC device struct
7986c09eba5SJon Nettleton * @return 0 on success, <0 on error.
7996c09eba5SJon Nettleton */
8006c09eba5SJon Nettleton int mmc_get_op_cond(struct mmc *mmc);
8016c09eba5SJon Nettleton
8026c09eba5SJon Nettleton /**
8036c09eba5SJon Nettleton * Start device initialization and return immediately; it does not block on
804e9550449SChe-Liang Chiou * polling OCR (operation condition register) status. Then you should call
805e9550449SChe-Liang Chiou * mmc_init, which would block on polling OCR status and complete the device
806e9550449SChe-Liang Chiou * initializatin.
807e9550449SChe-Liang Chiou *
808e9550449SChe-Liang Chiou * @param mmc Pointer to a MMC device struct
80931d95004SBaruch Siach * @return 0 on success, <0 on error.
810e9550449SChe-Liang Chiou */
811e9550449SChe-Liang Chiou int mmc_start_init(struct mmc *mmc);
812e9550449SChe-Liang Chiou
813e9550449SChe-Liang Chiou /**
814e9550449SChe-Liang Chiou * Set preinit flag of mmc device.
815e9550449SChe-Liang Chiou *
816e9550449SChe-Liang Chiou * This will cause the device to be pre-inited during mmc_initialize(),
817e9550449SChe-Liang Chiou * which may save boot time if the device is not accessed until later.
818e9550449SChe-Liang Chiou * Some eMMC devices take 200-300ms to init, but unfortunately they
819e9550449SChe-Liang Chiou * must be sent a series of commands to even get them to start preparing
820e9550449SChe-Liang Chiou * for operation.
821e9550449SChe-Liang Chiou *
822e9550449SChe-Liang Chiou * @param mmc Pointer to a MMC device struct
823e9550449SChe-Liang Chiou * @param preinit preinit flag value
824e9550449SChe-Liang Chiou */
825e9550449SChe-Liang Chiou void mmc_set_preinit(struct mmc *mmc, int preinit);
826e9550449SChe-Liang Chiou
8278687d5c8SPaul Burton #ifdef CONFIG_MMC_SPI
8280b2da7e2STom Rini #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
8298687d5c8SPaul Burton #else
8308687d5c8SPaul Burton #define mmc_host_is_spi(mmc) 0
8318687d5c8SPaul Burton #endif
832d52ebf10SThomas Chou struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
8331592ef85SReinhard Meyer
83495de9ab2SPaul Kocialkowski void board_mmc_power_init(void);
8353c7ca967SFabio Estevam int board_mmc_init(bd_t *bis);
836750121c3SJeroen Hofstee int cpu_mmc_init(bd_t *bis);
837aeb80555SJeroen Hofstee int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
83843d17c48SRajesh Bhagat # ifdef CONFIG_SYS_MMC_ENV_PART
83943d17c48SRajesh Bhagat extern uint mmc_get_env_part(struct mmc *mmc);
84043d17c48SRajesh Bhagat # endif
841aa844fe1SClemens Gruber int mmc_get_env_dev(void);
8423c7ca967SFabio Estevam
84393bfd616SPantelis Antoniou /* Set block count limit because of 16 bit register limit on some hardware*/
84493bfd616SPantelis Antoniou #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
84593bfd616SPantelis Antoniou #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
84693bfd616SPantelis Antoniou #endif
84793bfd616SPantelis Antoniou
848cb5ec33dSSimon Glass /**
849cb5ec33dSSimon Glass * mmc_get_blk_desc() - Get the block descriptor for an MMC device
850cb5ec33dSSimon Glass *
851cb5ec33dSSimon Glass * @mmc: MMC device
852cb5ec33dSSimon Glass * @return block device if found, else NULL
853cb5ec33dSSimon Glass */
854cb5ec33dSSimon Glass struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
855cb5ec33dSSimon Glass
85671f95118Swdenk #endif /* _MMC_H_ */
857