1 /*----------------------------------------------------------------------------+ 2 | This source code is dual-licensed. You may use it under the terms of the 3 | GNU General Public License version 2, or under the license below. 4 | 5 | This source code has been made available to you by IBM on an AS-IS 6 | basis. Anyone receiving this source is licensed under IBM 7 | copyrights to use it in any way he or she deems fit, including 8 | copying it, modifying it, compiling it, and redistributing it either 9 | with or without modifications. No license under IBM patents or 10 | patent applications is to be implied by the copyright license. 11 | 12 | Any user of this software should understand that IBM cannot provide 13 | technical support for this software and will not be responsible for 14 | any consequences resulting from the use of this software. 15 | 16 | Any person who transfers this source code or any derivative work 17 | must include the IBM copyright notice, this paragraph, and the 18 | preceding two paragraphs in the transferred software. 19 | 20 | COPYRIGHT I B M CORPORATION 1999 21 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 22 | 23 | Additions (C) Copyright 2009 Industrie Dial Face S.p.A. 24 +----------------------------------------------------------------------------*/ 25 /*----------------------------------------------------------------------------+ 26 | 27 | File Name: miiphy.h 28 | 29 | Function: Include file defining PHY registers. 30 | 31 | Author: Mark Wisner 32 | 33 +----------------------------------------------------------------------------*/ 34 #ifndef _miiphy_h_ 35 #define _miiphy_h_ 36 37 #include <net.h> 38 39 int miiphy_read (char *devname, unsigned char addr, unsigned char reg, 40 unsigned short *value); 41 int miiphy_write (char *devname, unsigned char addr, unsigned char reg, 42 unsigned short value); 43 int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, 44 unsigned char *model, unsigned char *rev); 45 int miiphy_reset (char *devname, unsigned char addr); 46 int miiphy_speed (char *devname, unsigned char addr); 47 int miiphy_duplex (char *devname, unsigned char addr); 48 int miiphy_is_1000base_x (char *devname, unsigned char addr); 49 #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 50 int miiphy_link (char *devname, unsigned char addr); 51 #endif 52 53 void miiphy_init (void); 54 55 void miiphy_register (char *devname, 56 int (*read) (char *devname, unsigned char addr, 57 unsigned char reg, unsigned short *value), 58 int (*write) (char *devname, unsigned char addr, 59 unsigned char reg, unsigned short value)); 60 61 int miiphy_set_current_dev (char *devname); 62 char *miiphy_get_current_dev (void); 63 64 void miiphy_listdev (void); 65 66 #ifdef CONFIG_BITBANGMII 67 68 #define BB_MII_DEVNAME "bb_miiphy" 69 70 struct bb_miiphy_bus { 71 char name[NAMESIZE]; 72 int (*init)(struct bb_miiphy_bus *bus); 73 int (*mdio_active)(struct bb_miiphy_bus *bus); 74 int (*mdio_tristate)(struct bb_miiphy_bus *bus); 75 int (*set_mdio)(struct bb_miiphy_bus *bus, int v); 76 int (*get_mdio)(struct bb_miiphy_bus *bus, int *v); 77 int (*set_mdc)(struct bb_miiphy_bus *bus, int v); 78 int (*delay)(struct bb_miiphy_bus *bus); 79 #ifdef CONFIG_BITBANGMII_MULTI 80 void *priv; 81 #endif 82 }; 83 84 extern struct bb_miiphy_bus bb_miiphy_buses[]; 85 extern int bb_miiphy_buses_num; 86 87 void bb_miiphy_init (void); 88 int bb_miiphy_read (char *devname, unsigned char addr, 89 unsigned char reg, unsigned short *value); 90 int bb_miiphy_write (char *devname, unsigned char addr, 91 unsigned char reg, unsigned short value); 92 #endif 93 94 /* phy seed setup */ 95 #define AUTO 99 96 #define _1000BASET 1000 97 #define _100BASET 100 98 #define _10BASET 10 99 #define HALF 22 100 #define FULL 44 101 102 /* phy register offsets */ 103 #define PHY_BMCR 0x00 104 #define PHY_BMSR 0x01 105 #define PHY_PHYIDR1 0x02 106 #define PHY_PHYIDR2 0x03 107 #define PHY_ANAR 0x04 108 #define PHY_ANLPAR 0x05 109 #define PHY_ANER 0x06 110 #define PHY_ANNPTR 0x07 111 #define PHY_ANLPNP 0x08 112 #define PHY_1000BTCR 0x09 113 #define PHY_1000BTSR 0x0A 114 #define PHY_EXSR 0x0F 115 #define PHY_PHYSTS 0x10 116 #define PHY_MIPSCR 0x11 117 #define PHY_MIPGSR 0x12 118 #define PHY_DCR 0x13 119 #define PHY_FCSCR 0x14 120 #define PHY_RECR 0x15 121 #define PHY_PCSR 0x16 122 #define PHY_LBR 0x17 123 #define PHY_10BTSCR 0x18 124 #define PHY_PHYCTRL 0x19 125 126 /* PHY BMCR */ 127 #define PHY_BMCR_RESET 0x8000 128 #define PHY_BMCR_LOOP 0x4000 129 #define PHY_BMCR_100MB 0x2000 130 #define PHY_BMCR_AUTON 0x1000 131 #define PHY_BMCR_POWD 0x0800 132 #define PHY_BMCR_ISO 0x0400 133 #define PHY_BMCR_RST_NEG 0x0200 134 #define PHY_BMCR_DPLX 0x0100 135 #define PHY_BMCR_COL_TST 0x0080 136 137 #define PHY_BMCR_SPEED_MASK 0x2040 138 #define PHY_BMCR_1000_MBPS 0x0040 139 #define PHY_BMCR_100_MBPS 0x2000 140 #define PHY_BMCR_10_MBPS 0x0000 141 142 /* phy BMSR */ 143 #define PHY_BMSR_100T4 0x8000 144 #define PHY_BMSR_100TXF 0x4000 145 #define PHY_BMSR_100TXH 0x2000 146 #define PHY_BMSR_10TF 0x1000 147 #define PHY_BMSR_10TH 0x0800 148 #define PHY_BMSR_EXT_STAT 0x0100 149 #define PHY_BMSR_PRE_SUP 0x0040 150 #define PHY_BMSR_AUTN_COMP 0x0020 151 #define PHY_BMSR_RF 0x0010 152 #define PHY_BMSR_AUTN_ABLE 0x0008 153 #define PHY_BMSR_LS 0x0004 154 #define PHY_BMSR_JD 0x0002 155 #define PHY_BMSR_EXT 0x0001 156 157 /*phy ANLPAR */ 158 #define PHY_ANLPAR_NP 0x8000 159 #define PHY_ANLPAR_ACK 0x4000 160 #define PHY_ANLPAR_RF 0x2000 161 #define PHY_ANLPAR_ASYMP 0x0800 162 #define PHY_ANLPAR_PAUSE 0x0400 163 #define PHY_ANLPAR_T4 0x0200 164 #define PHY_ANLPAR_TXFD 0x0100 165 #define PHY_ANLPAR_TX 0x0080 166 #define PHY_ANLPAR_10FD 0x0040 167 #define PHY_ANLPAR_10 0x0020 168 #define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ 169 /* phy ANLPAR 1000BASE-X */ 170 #define PHY_X_ANLPAR_NP 0x8000 171 #define PHY_X_ANLPAR_ACK 0x4000 172 #define PHY_X_ANLPAR_RF_MASK 0x3000 173 #define PHY_X_ANLPAR_PAUSE_MASK 0x0180 174 #define PHY_X_ANLPAR_HD 0x0040 175 #define PHY_X_ANLPAR_FD 0x0020 176 177 #define PHY_ANLPAR_PSB_MASK 0x001f 178 #define PHY_ANLPAR_PSB_802_3 0x0001 179 #define PHY_ANLPAR_PSB_802_9 0x0002 180 181 /* phy 1000BTCR */ 182 #define PHY_1000BTCR_1000FD 0x0200 183 #define PHY_1000BTCR_1000HD 0x0100 184 185 /* phy 1000BTSR */ 186 #define PHY_1000BTSR_MSCF 0x8000 187 #define PHY_1000BTSR_MSCR 0x4000 188 #define PHY_1000BTSR_LRS 0x2000 189 #define PHY_1000BTSR_RRS 0x1000 190 #define PHY_1000BTSR_1000FD 0x0800 191 #define PHY_1000BTSR_1000HD 0x0400 192 193 /* phy EXSR */ 194 #define PHY_EXSR_1000XF 0x8000 195 #define PHY_EXSR_1000XH 0x4000 196 #define PHY_EXSR_1000TF 0x2000 197 #define PHY_EXSR_1000TH 0x1000 198 199 #endif 200