1 /*----------------------------------------------------------------------------+ 2 | This source code is dual-licensed. You may use it under the terms of the 3 | GNU General Public License version 2, or under the license below. 4 | 5 | This source code has been made available to you by IBM on an AS-IS 6 | basis. Anyone receiving this source is licensed under IBM 7 | copyrights to use it in any way he or she deems fit, including 8 | copying it, modifying it, compiling it, and redistributing it either 9 | with or without modifications. No license under IBM patents or 10 | patent applications is to be implied by the copyright license. 11 | 12 | Any user of this software should understand that IBM cannot provide 13 | technical support for this software and will not be responsible for 14 | any consequences resulting from the use of this software. 15 | 16 | Any person who transfers this source code or any derivative work 17 | must include the IBM copyright notice, this paragraph, and the 18 | preceding two paragraphs in the transferred software. 19 | 20 | COPYRIGHT I B M CORPORATION 1999 21 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 22 +----------------------------------------------------------------------------*/ 23 /*----------------------------------------------------------------------------+ 24 | 25 | File Name: miiphy.h 26 | 27 | Function: Include file defining PHY registers. 28 | 29 | Author: Mark Wisner 30 | 31 +----------------------------------------------------------------------------*/ 32 #ifndef _miiphy_h_ 33 #define _miiphy_h_ 34 35 #include <net.h> 36 37 int miiphy_read (char *devname, unsigned char addr, unsigned char reg, 38 unsigned short *value); 39 int miiphy_write (char *devname, unsigned char addr, unsigned char reg, 40 unsigned short value); 41 int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, 42 unsigned char *model, unsigned char *rev); 43 int miiphy_reset (char *devname, unsigned char addr); 44 int miiphy_speed (char *devname, unsigned char addr); 45 int miiphy_duplex (char *devname, unsigned char addr); 46 int miiphy_is_1000base_x (char *devname, unsigned char addr); 47 #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 48 int miiphy_link (char *devname, unsigned char addr); 49 #endif 50 51 void miiphy_init (void); 52 53 void miiphy_register (char *devname, 54 int (*read) (char *devname, unsigned char addr, 55 unsigned char reg, unsigned short *value), 56 int (*write) (char *devname, unsigned char addr, 57 unsigned char reg, unsigned short value)); 58 59 int miiphy_set_current_dev (char *devname); 60 char *miiphy_get_current_dev (void); 61 62 void miiphy_listdev (void); 63 64 #define BB_MII_DEVNAME "bbmii" 65 66 int bb_miiphy_read (char *devname, unsigned char addr, 67 unsigned char reg, unsigned short *value); 68 int bb_miiphy_write (char *devname, unsigned char addr, 69 unsigned char reg, unsigned short value); 70 71 /* phy seed setup */ 72 #define AUTO 99 73 #define _1000BASET 1000 74 #define _100BASET 100 75 #define _10BASET 10 76 #define HALF 22 77 #define FULL 44 78 79 /* phy register offsets */ 80 #define PHY_BMCR 0x00 81 #define PHY_BMSR 0x01 82 #define PHY_PHYIDR1 0x02 83 #define PHY_PHYIDR2 0x03 84 #define PHY_ANAR 0x04 85 #define PHY_ANLPAR 0x05 86 #define PHY_ANER 0x06 87 #define PHY_ANNPTR 0x07 88 #define PHY_ANLPNP 0x08 89 #define PHY_1000BTCR 0x09 90 #define PHY_1000BTSR 0x0A 91 #define PHY_EXSR 0x0F 92 #define PHY_PHYSTS 0x10 93 #define PHY_MIPSCR 0x11 94 #define PHY_MIPGSR 0x12 95 #define PHY_DCR 0x13 96 #define PHY_FCSCR 0x14 97 #define PHY_RECR 0x15 98 #define PHY_PCSR 0x16 99 #define PHY_LBR 0x17 100 #define PHY_10BTSCR 0x18 101 #define PHY_PHYCTRL 0x19 102 103 /* PHY BMCR */ 104 #define PHY_BMCR_RESET 0x8000 105 #define PHY_BMCR_LOOP 0x4000 106 #define PHY_BMCR_100MB 0x2000 107 #define PHY_BMCR_AUTON 0x1000 108 #define PHY_BMCR_POWD 0x0800 109 #define PHY_BMCR_ISO 0x0400 110 #define PHY_BMCR_RST_NEG 0x0200 111 #define PHY_BMCR_DPLX 0x0100 112 #define PHY_BMCR_COL_TST 0x0080 113 114 #define PHY_BMCR_SPEED_MASK 0x2040 115 #define PHY_BMCR_1000_MBPS 0x0040 116 #define PHY_BMCR_100_MBPS 0x2000 117 #define PHY_BMCR_10_MBPS 0x0000 118 119 /* phy BMSR */ 120 #define PHY_BMSR_100T4 0x8000 121 #define PHY_BMSR_100TXF 0x4000 122 #define PHY_BMSR_100TXH 0x2000 123 #define PHY_BMSR_10TF 0x1000 124 #define PHY_BMSR_10TH 0x0800 125 #define PHY_BMSR_EXT_STAT 0x0100 126 #define PHY_BMSR_PRE_SUP 0x0040 127 #define PHY_BMSR_AUTN_COMP 0x0020 128 #define PHY_BMSR_RF 0x0010 129 #define PHY_BMSR_AUTN_ABLE 0x0008 130 #define PHY_BMSR_LS 0x0004 131 #define PHY_BMSR_JD 0x0002 132 #define PHY_BMSR_EXT 0x0001 133 134 /*phy ANLPAR */ 135 #define PHY_ANLPAR_NP 0x8000 136 #define PHY_ANLPAR_ACK 0x4000 137 #define PHY_ANLPAR_RF 0x2000 138 #define PHY_ANLPAR_ASYMP 0x0800 139 #define PHY_ANLPAR_PAUSE 0x0400 140 #define PHY_ANLPAR_T4 0x0200 141 #define PHY_ANLPAR_TXFD 0x0100 142 #define PHY_ANLPAR_TX 0x0080 143 #define PHY_ANLPAR_10FD 0x0040 144 #define PHY_ANLPAR_10 0x0020 145 #define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ 146 /* phy ANLPAR 1000BASE-X */ 147 #define PHY_X_ANLPAR_NP 0x8000 148 #define PHY_X_ANLPAR_ACK 0x4000 149 #define PHY_X_ANLPAR_RF_MASK 0x3000 150 #define PHY_X_ANLPAR_PAUSE_MASK 0x0180 151 #define PHY_X_ANLPAR_HD 0x0040 152 #define PHY_X_ANLPAR_FD 0x0020 153 154 #define PHY_ANLPAR_PSB_MASK 0x001f 155 #define PHY_ANLPAR_PSB_802_3 0x0001 156 #define PHY_ANLPAR_PSB_802_9 0x0002 157 158 /* phy 1000BTCR */ 159 #define PHY_1000BTCR_1000FD 0x0200 160 #define PHY_1000BTCR_1000HD 0x0100 161 162 /* phy 1000BTSR */ 163 #define PHY_1000BTSR_MSCF 0x8000 164 #define PHY_1000BTSR_MSCR 0x4000 165 #define PHY_1000BTSR_LRS 0x2000 166 #define PHY_1000BTSR_RRS 0x1000 167 #define PHY_1000BTSR_1000FD 0x0800 168 #define PHY_1000BTSR_1000HD 0x0400 169 170 /* phy EXSR */ 171 #define PHY_EXSR_1000XF 0x8000 172 #define PHY_EXSR_1000XH 0x4000 173 #define PHY_EXSR_1000TF 0x2000 174 #define PHY_EXSR_1000TH 0x1000 175 176 #endif 177