1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __MC34704_H__ 7 #define __MC34704_H__ 8 9 enum { 10 MC34704_RESERVED0_REG = 0, /* 0x00 */ 11 MC34704_GENERAL1_REG, /* 0x01 */ 12 MC34704_GENERAL2_REG, /* 0x02 */ 13 MC34704_GENERAL3_REG, /* 0x03 */ 14 MC34704_RESERVED4_REG, /* 0x04 */ 15 MC34704_VGSET2_REG, /* 0x05 */ 16 MC34704_REG2SET1_REG, /* 0x06 */ 17 MC34704_REG2SET2_REG, /* 0x07 */ 18 MC34704_REG3SET1_REG, /* 0x08 */ 19 MC34704_REG3SET2_REG, /* 0x09 */ 20 MC34704_REG4SET1_REG, /* 0x0a */ 21 MC34704_REG4SET2_REG, /* 0x0b */ 22 MC34704_REG5SET1_REG, /* 0x0c */ 23 MC34704_REG5SET2_REG, /* 0x0d */ 24 MC34704_REG5SET3_REG, /* 0x0e */ 25 MC34704_RESERVEDF_REG, /* 0x0f */ 26 MC34704_RESERVED10_REG, /* 0x10 */ 27 MC34704_RESERVED11_REG, /* 0x11 */ 28 MC34704_RESERVED12_REG, /* 0x12 */ 29 MC34704_FSW2SET_REG, /* 0x13 */ 30 MC34704_RESERVED14_REG, /* 0x14 */ 31 MC34704_REG8SET1_REG, /* 0x15 */ 32 MC34704_REG8SET2_REG, /* 0x16 */ 33 MC34704_REG8SET3_REG, /* 0x17 */ 34 MC34704_FAULTS_REG, /* 0x18 */ 35 MC34704_I2CSET1, /* 0x19 */ 36 MC34704_NUM_OF_REGS, 37 }; 38 39 /* GENERAL2 register fields */ 40 #define ONOFFE (1 << 0) 41 #define ONOFFD (1 << 1) 42 #define ONOFFA (1 << 3) 43 #define ALLOFF (1 << 4) 44 45 #endif /* __MC34704_H__ */ 46