xref: /openbmc/u-boot/include/mc13892.h (revision c4f07be2)
1 /*
2  * (C) Copyright 2010
3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4  *
5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 
26 
27 #ifndef __MC13892_H__
28 #define __MC13892_H__
29 
30 /* REG_CHARGE */
31 
32 #define VCHRG0		(1 << 0)
33 #define VCHRG1		(1 << 1)
34 #define VCHRG2		(1 << 2)
35 #define ICHRG0		(1 << 3)
36 #define ICHRG1		(1 << 4)
37 #define ICHRG2		(1 << 5)
38 #define ICHRG3		(1 << 6)
39 #define TREN		(1 << 7)
40 #define ACKLPB		(1 << 8)
41 #define THCHKB		(1 << 9)
42 #define FETOVRD		(1 << 10)
43 #define FETCTRL		(1 << 11)
44 #define RVRSMODE	(1 << 13)
45 #define PLIM0		(1 << 15)
46 #define PLIM1		(1 << 16)
47 #define PLIMDIS		(1 << 17)
48 #define CHRGLEDEN	(1 << 18)
49 #define CHGTMRRST	(1 << 19)
50 #define CHGRESTART	(1 << 20)
51 #define CHGAUTOB	(1 << 21)
52 #define CYCLB		(1 << 22)
53 #define CHGAUTOVIB	(1 << 23)
54 
55 /* REG_SETTING_0/1 */
56 #define VO_1_20V	0
57 #define VO_1_30V	1
58 #define VO_1_50V	2
59 #define VO_1_80V	3
60 #define VO_1_10V	4
61 #define VO_2_00V	5
62 #define VO_2_77V	6
63 #define VO_2_40V	7
64 
65 #define VIOL		2
66 #define VDIG		4
67 #define VGEN		6
68 
69 /* SWxMode for Normal/Standby Mode */
70 #define SWMODE_OFF_OFF		0
71 #define SWMODE_PWM_OFF		1
72 #define SWMODE_PWMPS_OFF	2
73 #define SWMODE_PFM_OFF		3
74 #define SWMODE_AUTO_OFF		4
75 #define SWMODE_PWM_PWM		5
76 #define SWMODE_PWM_AUTO		6
77 #define SWMODE_AUTO_AUTO	8
78 #define SWMODE_PWM_PWMPS	9
79 #define SWMODE_PWMS_PWMPS	10
80 #define SWMODE_PWMS_AUTO	11
81 #define SWMODE_AUTO_PFM		12
82 #define SWMODE_PWM_PFM		13
83 #define SWMODE_PWMS_PFM		14
84 #define SWMODE_PFM_PFM		15
85 #define SWMODE_MASK		0x0F
86 
87 #define SWMODE1_SHIFT		0
88 #define SWMODE2_SHIFT		10
89 #define SWMODE3_SHIFT		0
90 #define SWMODE4_SHIFT		8
91 
92 /* Fields in REG_SETTING_1 */
93 #define VVIDEO_2_7	(0 << 2)
94 #define VVIDEO_2_775	(1 << 2)
95 #define VVIDEO_2_5	(2 << 2)
96 #define VVIDEO_2_6	(3 << 2)
97 #define VVIDEO_MASK	(3 << 2)
98 #define VAUDIO_2_3	(0 << 4)
99 #define VAUDIO_2_5	(1 << 4)
100 #define VAUDIO_2_775	(2 << 4)
101 #define VAUDIO_3_0	(3 << 4)
102 #define VAUDIO_MASK	(3 << 4)
103 #define VSD_1_8		(0 << 6)
104 #define VSD_2_0		(1 << 6)
105 #define VSD_2_6		(2 << 6)
106 #define VSD_2_7		(3 << 6)
107 #define VSD_2_8		(4 << 6)
108 #define VSD_2_9		(5 << 6)
109 #define VSD_3_0		(6 << 6)
110 #define VSD_3_15	(7 << 6)
111 #define VSD_MASK	(7 << 6)
112 #define VGEN1_1_2	0
113 #define VGEN1_1_5	1
114 #define VGEN1_2_775	2
115 #define VGEN1_3_15	3
116 #define VGEN1_MASK	3
117 #define VGEN2_1_2	(0 << 6)
118 #define VGEN2_1_5	(1 << 6)
119 #define VGEN2_1_6	(2 << 6)
120 #define VGEN2_1_8	(3 << 6)
121 #define VGEN2_2_7	(4 << 6)
122 #define VGEN2_2_8	(5 << 6)
123 #define VGEN2_3_0	(6 << 6)
124 #define VGEN2_3_15	(7 << 6)
125 #define VGEN2_MASK	(7 << 6)
126 
127 /* Fields in REG_SETTING_1 */
128 #define VGEN3_1_8	(0 << 14)
129 #define VGEN3_2_9	(1 << 14)
130 #define VGEN3_MASK	(1 << 14)
131 #define VDIG_1_05	(0 << 4)
132 #define VDIG_1_25	(1 << 4)
133 #define VDIG_1_65	(2 << 4)
134 #define VDIG_1_8	(3 << 4)
135 #define VDIG_MASK	(3 << 4)
136 #define VCAM_2_5	(0 << 16)
137 #define VCAM_2_6	(1 << 16)
138 #define VCAM_2_75	(2 << 16)
139 #define VCAM_3_0	(3 << 16)
140 #define VCAM_MASK	(3 << 16)
141 
142 /* Reg Mode 1 */
143 #define VGEN3EN		(1 << 0)
144 #define VGEN3STBY	(1 << 1)
145 #define VGEN3MODE	(1 << 2)
146 #define VGEN3CONFIG	(1 << 3)
147 #define VCAMEN		(1 << 6)
148 #define VCAMSTBY	(1 << 7)
149 #define VCAMMODE	(1 << 8)
150 #define VCAMCONFIG	(1 << 9)
151 #define VVIDEOEN	(1 << 12)
152 #define VIDEOSTBY	(1 << 13)
153 #define VVIDEOMODE	(1 << 14)
154 #define VAUDIOEN	(1 << 15)
155 #define VAUDIOSTBY	(1 << 16)
156 #define VSDEN		(1 << 18)
157 #define VSDSTBY		(1 << 19)
158 #define VSDMODE		(1 << 20)
159 
160 /* Reg Power Control 2*/
161 #define WDIRESET	(1 << 12)
162 
163 /* SWx Output Volts */
164 #define SWX_OUT_MASK	0x1F
165 #define SWX_OUT_1_25	0x1A
166 #define SWX_OUT_1_30    0X1C
167 
168 /* Buck Switchers (SW1,2,3,4) Output Voltage */
169 /*
170  * NOTE: These values are for SWxHI = 0,
171  * SWxHI = 1 adds 0.5V to the desired voltage
172  */
173 #define SWx_0_600V	0
174 #define SWx_0_625V	1
175 #define SWx_0_650V	2
176 #define SWx_0_675V	3
177 #define SWx_0_700V	4
178 #define SWx_0_725V	5
179 #define SWx_0_750V	6
180 #define SWx_0_775V	7
181 #define SWx_0_800V	8
182 #define SWx_0_825V	9
183 #define SWx_0_850V	10
184 #define SWx_0_875V	11
185 #define SWx_0_900V	12
186 #define SWx_0_925V	13
187 #define SWx_0_950V	14
188 #define SWx_0_975V	15
189 #define SWx_1_000V	16
190 #define SWx_1_025V	17
191 #define SWx_1_050V	18
192 #define SWx_1_075V	19
193 #define SWx_1_100V	20
194 #define SWx_1_125V	21
195 #define SWx_1_150V	22
196 #define SWx_1_175V	23
197 #define SWx_1_200V	24
198 #define SWx_1_225V	25
199 #define SWx_1_250V	26
200 #define SWx_1_275V	27
201 #define SWx_1_300V	28
202 #define SWx_1_325V	29
203 #define SWx_1_350V	30
204 #define SWx_1_375V	31
205 #define SWx_VOLT_MASK	0x1F
206 
207 #endif
208