1 /*********************************************************************** 2 * 3 * Copyright (C) 2004 by FS Forth-Systeme GmbH. 4 * All rights reserved. 5 * 6 * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $ 7 * @Author: Markus Pietrek 8 * @References: [1] NS9750 Hardware Reference, December 2003 9 * [2] Intel LXT971 Datasheet #249414 Rev. 02 10 * [3] NS7520 Linux Ethernet Driver 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __LXT971A_H__ 16 #define __LXT971A_H__ 17 18 /* PHY definitions (LXT971A) [2] */ 19 #define PHY_LXT971_PORT_CFG (0x10) 20 #define PHY_LXT971_STAT2 (0x11) 21 #define PHY_LXT971_INT_ENABLE (0x12) 22 #define PHY_LXT971_INT_STATUS (0x13) 23 #define PHY_LXT971_LED_CFG (0x14) 24 #define PHY_LXT971_DIG_CFG (0x1A) 25 #define PHY_LXT971_TX_CTRL (0x1E) 26 27 /* PORT_CFG Port Configuration Register Bit Fields */ 28 #define PHY_LXT971_PORT_CFG_RES1 (0x8000) 29 #define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000) 30 #define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000) 31 #define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000) 32 #define PHY_LXT971_PORT_CFG_RES2 (0x0800) 33 #define PHY_LXT971_PORT_CFG_JABBER (0x0400) 34 #define PHY_LXT971_PORT_CFG_SQE (0x0200) 35 #define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100) 36 #define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080) 37 #define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040) 38 #define PHY_LXT971_PORT_CFG_PRE_EN (0x0020) 39 #define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018) 40 #define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010) 41 #define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001) 42 #define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000) 43 #define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004) 44 #define PHY_LXT971_PORT_CFG_ALT_NP (0x0002) 45 #define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001) 46 47 /* STAT2 Status Register #2 Bit Fields */ 48 #define PHY_LXT971_STAT2_RES1 (0x8000) 49 #define PHY_LXT971_STAT2_100BTX (0x4000) 50 #define PHY_LXT971_STAT2_TX_STATUS (0x2000) 51 #define PHY_LXT971_STAT2_RX_STATUS (0x1000) 52 #define PHY_LXT971_STAT2_COL_STATUS (0x0800) 53 #define PHY_LXT971_STAT2_LINK (0x0400) 54 #define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200) 55 #define PHY_LXT971_STAT2_AUTO_NEG (0x0100) 56 #define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080) 57 #define PHY_LXT971_STAT2_RES2 (0x0040) 58 #define PHY_LXT971_STAT2_POLARITY (0x0020) 59 #define PHY_LXT971_STAT2_PAUSE (0x0010) 60 #define PHY_LXT971_STAT2_ERROR (0x0008) 61 #define PHY_LXT971_STAT2_RES3 (0x0007) 62 63 /* INT_ENABLE Interrupt Enable Register Bit Fields */ 64 #define PHY_LXT971_INT_ENABLE_RES1 (0xFF00) 65 #define PHY_LXT971_INT_ENABLE_ANMSK (0x0080) 66 #define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040) 67 #define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020) 68 #define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010) 69 #define PHY_LXT971_INT_ENABLE_RES2 (0x000C) 70 #define PHY_LXT971_INT_ENABLE_INTEN (0x0002) 71 #define PHY_LXT971_INT_ENABLE_TINT (0x0001) 72 73 /* INT_STATUS Interrupt Status Register Bit Fields */ 74 #define PHY_LXT971_INT_STATUS_RES1 (0xFF00) 75 #define PHY_LXT971_INT_STATUS_ANDONE (0x0080) 76 #define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040) 77 #define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020) 78 #define PHY_LXT971_INT_STATUS_LINKCHG (0x0010) 79 #define PHY_LXT971_INT_STATUS_RES2 (0x0008) 80 #define PHY_LXT971_INT_STATUS_MDINT (0x0004) 81 #define PHY_LXT971_INT_STATUS_RES3 (0x0003) 82 83 /* LED_CFG Interrupt LED Configuration Register Bit Fields */ 84 #define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C) 85 #define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008) 86 #define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004) 87 #define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C) 88 #define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C) 89 #define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008) 90 #define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004) 91 #define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000) 92 #define PHY_LXT971_LED_CFG_PULSE_STR (0x0002) 93 #define PHY_LXT971_LED_CFG_RES1 (0x0001) 94 95 /* only one of these values must be shifted for each SHIFT_LED? */ 96 #define PHY_LXT971_LED_CFG_UNUSED1 (0x000F) 97 #define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E) 98 #define PHY_LXT971_LED_CFG_LINK_ACT (0x000D) 99 #define PHY_LXT971_LED_CFG_LINK_RX (0x000C) 100 #define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B) 101 #define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A) 102 #define PHY_LXT971_LED_CFG_TEST_OFF (0x0009) 103 #define PHY_LXT971_LED_CFG_TEST_ON (0x0008) 104 #define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007) 105 #define PHY_LXT971_LED_CFG_UNUSED2 (0x0006) 106 #define PHY_LXT971_LED_CFG_DUPLEX (0x0005) 107 #define PHY_LXT971_LED_CFG_LINK (0x0004) 108 #define PHY_LXT971_LED_CFG_COLLISION (0x0003) 109 #define PHY_LXT971_LED_CFG_RECEIVE (0x0002) 110 #define PHY_LXT971_LED_CFG_TRANSMIT (0x0001) 111 #define PHY_LXT971_LED_CFG_SPEED (0x0000) 112 113 /* DIG_CFG Digitial Configuration Register Bit Fields */ 114 #define PHY_LXT971_DIG_CFG_RES1 (0xF000) 115 #define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800) 116 #define PHY_LXT971_DIG_CFG_RES2 (0x0400) 117 #define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200) 118 #define PHY_LXT971_DIG_CFG_RES3 (0x01FF) 119 120 #define PHY_LXT971_MDIO_MAX_CLK (8000000) 121 #define PHY_MDIO_MAX_CLK (2500000) 122 123 /* TX_CTRL Transmit Control Register Bit Fields 124 documentation is buggy for this register, therefore setting not included */ 125 126 typedef enum 127 { 128 PHY_NONE = 0x0000, /* no PHY detected yet */ 129 PHY_LXT971A = 0x0013 130 } PhyType; 131 132 #endif /* __LXT971A_H__ */ 133