xref: /openbmc/u-boot/include/lxt971a.h (revision 2a046ff5)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /***********************************************************************
3  *
4  * Copyright (C) 2004 by FS Forth-Systeme GmbH.
5  * All rights reserved.
6  *
7  * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
8  * @Author: Markus Pietrek
9  * @References: [1] NS9750 Hardware Reference, December 2003
10  *              [2] Intel LXT971 Datasheet #249414 Rev. 02
11  *              [3] NS7520 Linux Ethernet Driver
12  */
13 
14 #ifndef __LXT971A_H__
15 #define __LXT971A_H__
16 
17 /* PHY definitions (LXT971A) [2] */
18 #define PHY_LXT971_PORT_CFG		(0x10)
19 #define PHY_LXT971_STAT2		(0x11)
20 #define PHY_LXT971_INT_ENABLE		(0x12)
21 #define PHY_LXT971_INT_STATUS		(0x13)
22 #define PHY_LXT971_LED_CFG		(0x14)
23 #define PHY_LXT971_DIG_CFG		(0x1A)
24 #define PHY_LXT971_TX_CTRL		(0x1E)
25 
26 /* PORT_CFG Port Configuration Register Bit Fields */
27 #define PHY_LXT971_PORT_CFG_RES1        (0x8000)
28 #define PHY_LXT971_PORT_CFG_FORCE_LNK   (0x4000)
29 #define PHY_LXT971_PORT_CFG_TX_DISABLE  (0x2000)
30 #define PHY_LXT971_PORT_CFG_BYPASS_SCR  (0x1000)
31 #define PHY_LXT971_PORT_CFG_RES2        (0x0800)
32 #define PHY_LXT971_PORT_CFG_JABBER      (0x0400)
33 #define PHY_LXT971_PORT_CFG_SQE	        (0x0200)
34 #define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
35 #define PHY_LXT971_PORT_CFG_CRS_SEL     (0x0080)
36 #define PHY_LXT971_PORT_CFG_SLEEP_MODE  (0x0040)
37 #define PHY_LXT971_PORT_CFG_PRE_EN      (0x0020)
38 #define PHY_LXT971_PORT_CFG_SLEEP_T_MA  (0x0018)
39 #define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
40 #define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
41 #define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
42 #define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
43 #define PHY_LXT971_PORT_CFG_ALT_NP      (0x0002)
44 #define PHY_LXT971_PORT_CFG_FIBER_SEL   (0x0001)
45 
46 /* STAT2 Status Register #2 Bit Fields */
47 #define PHY_LXT971_STAT2_RES1		(0x8000)
48 #define PHY_LXT971_STAT2_100BTX		(0x4000)
49 #define PHY_LXT971_STAT2_TX_STATUS	(0x2000)
50 #define PHY_LXT971_STAT2_RX_STATUS	(0x1000)
51 #define PHY_LXT971_STAT2_COL_STATUS	(0x0800)
52 #define PHY_LXT971_STAT2_LINK		(0x0400)
53 #define PHY_LXT971_STAT2_DUPLEX_MODE	(0x0200)
54 #define PHY_LXT971_STAT2_AUTO_NEG	(0x0100)
55 #define PHY_LXT971_STAT2_AUTO_NEG_COMP	(0x0080)
56 #define PHY_LXT971_STAT2_RES2		(0x0040)
57 #define PHY_LXT971_STAT2_POLARITY	(0x0020)
58 #define PHY_LXT971_STAT2_PAUSE		(0x0010)
59 #define PHY_LXT971_STAT2_ERROR		(0x0008)
60 #define PHY_LXT971_STAT2_RES3		(0x0007)
61 
62 /* INT_ENABLE Interrupt Enable Register Bit Fields */
63 #define PHY_LXT971_INT_ENABLE_RES1      (0xFF00)
64 #define PHY_LXT971_INT_ENABLE_ANMSK     (0x0080)
65 #define PHY_LXT971_INT_ENABLE_SPEEDMSK  (0x0040)
66 #define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
67 #define PHY_LXT971_INT_ENABLE_LINKMSK   (0x0010)
68 #define PHY_LXT971_INT_ENABLE_RES2      (0x000C)
69 #define PHY_LXT971_INT_ENABLE_INTEN     (0x0002)
70 #define PHY_LXT971_INT_ENABLE_TINT      (0x0001)
71 
72 /* INT_STATUS Interrupt Status Register Bit Fields */
73 #define PHY_LXT971_INT_STATUS_RES1      (0xFF00)
74 #define PHY_LXT971_INT_STATUS_ANDONE    (0x0080)
75 #define PHY_LXT971_INT_STATUS_SPEEDCHG  (0x0040)
76 #define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
77 #define PHY_LXT971_INT_STATUS_LINKCHG   (0x0010)
78 #define PHY_LXT971_INT_STATUS_RES2      (0x0008)
79 #define PHY_LXT971_INT_STATUS_MDINT     (0x0004)
80 #define PHY_LXT971_INT_STATUS_RES3      (0x0003)
81 
82 /* LED_CFG Interrupt LED Configuration Register Bit Fields */
83 #define PHY_LXT971_LED_CFG_SHIFT_LED1   (0x000C)
84 #define PHY_LXT971_LED_CFG_SHIFT_LED2   (0x0008)
85 #define PHY_LXT971_LED_CFG_SHIFT_LED3   (0x0004)
86 #define PHY_LXT971_LED_CFG_LEDFREQ_MA	(0x000C)
87 #define PHY_LXT971_LED_CFG_LEDFREQ_RES	(0x000C)
88 #define PHY_LXT971_LED_CFG_LEDFREQ_100	(0x0008)
89 #define PHY_LXT971_LED_CFG_LEDFREQ_60	(0x0004)
90 #define PHY_LXT971_LED_CFG_LEDFREQ_30	(0x0000)
91 #define PHY_LXT971_LED_CFG_PULSE_STR    (0x0002)
92 #define PHY_LXT971_LED_CFG_RES1         (0x0001)
93 
94 /* only one of these values must be shifted for each SHIFT_LED?  */
95 #define PHY_LXT971_LED_CFG_UNUSED1      (0x000F)
96 #define PHY_LXT971_LED_CFG_DUPLEX_COL   (0x000E)
97 #define PHY_LXT971_LED_CFG_LINK_ACT     (0x000D)
98 #define PHY_LXT971_LED_CFG_LINK_RX      (0x000C)
99 #define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
100 #define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
101 #define PHY_LXT971_LED_CFG_TEST_OFF     (0x0009)
102 #define PHY_LXT971_LED_CFG_TEST_ON      (0x0008)
103 #define PHY_LXT971_LED_CFG_RX_OR_TX     (0x0007)
104 #define PHY_LXT971_LED_CFG_UNUSED2      (0x0006)
105 #define PHY_LXT971_LED_CFG_DUPLEX       (0x0005)
106 #define PHY_LXT971_LED_CFG_LINK	        (0x0004)
107 #define PHY_LXT971_LED_CFG_COLLISION    (0x0003)
108 #define PHY_LXT971_LED_CFG_RECEIVE      (0x0002)
109 #define PHY_LXT971_LED_CFG_TRANSMIT     (0x0001)
110 #define PHY_LXT971_LED_CFG_SPEED        (0x0000)
111 
112 /* DIG_CFG Digitial Configuration Register Bit Fields */
113 #define PHY_LXT971_DIG_CFG_RES1		(0xF000)
114 #define PHY_LXT971_DIG_CFG_MII_DRIVE	(0x0800)
115 #define PHY_LXT971_DIG_CFG_RES2		(0x0400)
116 #define PHY_LXT971_DIG_CFG_SHOW_SYMBOL	(0x0200)
117 #define PHY_LXT971_DIG_CFG_RES3		(0x01FF)
118 
119 #define PHY_LXT971_MDIO_MAX_CLK		(8000000)
120 #define PHY_MDIO_MAX_CLK		(2500000)
121 
122 /* TX_CTRL Transmit Control Register Bit Fields
123    documentation is buggy for this register, therefore setting not included */
124 
125 typedef enum
126 {
127 	PHY_NONE    = 0x0000, /* no PHY detected yet */
128 	PHY_LXT971A = 0x0013
129 } PhyType;
130 
131 #endif /* __LXT971A_H__ */
132