1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Inc, <www.ti.com> 4 * 5 * Author: Dan Murphy <dmurphy@ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _ASM_ARCH_XHCI_OMAP_H_ 11 #define _ASM_ARCH_XHCI_OMAP_H_ 12 13 #ifdef CONFIG_TARGET_DRA7XX_EVM 14 #define OMAP_XHCI_BASE 0x488d0000 15 #define OMAP_OCP1_SCP_BASE 0x4A081000 16 #define OMAP_OTG_WRAPPER_BASE 0x488c0000 17 #elif defined CONFIG_TARGET_AM57XX_EVM 18 #define OMAP_XHCI_BASE 0x48890000 19 #define OMAP_OCP1_SCP_BASE 0x4A084c00 20 #define OMAP_OTG_WRAPPER_BASE 0x48880000 21 #elif defined CONFIG_AM43XX 22 #define OMAP_XHCI_BASE 0x483d0000 23 #define OMAP_OCP1_SCP_BASE 0x483E8000 24 #define OMAP_OTG_WRAPPER_BASE 0x483dc100 25 #else 26 /* Default to the OMAP5 XHCI defines */ 27 #define OMAP_XHCI_BASE 0x4a030000 28 #define OMAP_OCP1_SCP_BASE 0x4a084c00 29 #define OMAP_OTG_WRAPPER_BASE 0x4A020000 30 #endif 31 32 /* Phy register MACRO definitions */ 33 #define PLL_REGM_MASK 0x001FFE00 34 #define PLL_REGM_SHIFT 0x9 35 #define PLL_REGM_F_MASK 0x0003FFFF 36 #define PLL_REGM_F_SHIFT 0x0 37 #define PLL_REGN_MASK 0x000001FE 38 #define PLL_REGN_SHIFT 0x1 39 #define PLL_SELFREQDCO_MASK 0x0000000E 40 #define PLL_SELFREQDCO_SHIFT 0x1 41 #define PLL_SD_MASK 0x0003FC00 42 #define PLL_SD_SHIFT 0x9 43 #define SET_PLL_GO 0x1 44 #define PLL_TICOPWDN 0x10000 45 #define PLL_LOCK 0x2 46 #define PLL_IDLE 0x1 47 48 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 49 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 50 #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) 51 #define USB3_PHY_RX_POWERON (1 << 14) 52 #define USB3_PHY_TX_POWERON (1 << 15) 53 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 54 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 55 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 56 57 /* USBOTGSS_WRAPPER definitions */ 58 #define USBOTGSS_WRAPRESET (1 << 17) 59 #define USBOTGSS_DMADISABLE (1 << 16) 60 #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) 61 #define USBOTGSS_STANDBYMODE_SMRT (1 << 5) 62 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 63 #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) 64 #define USBOTGSS_IDLEMODE_SMRT (1 << 3) 65 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 66 67 /* USBOTGSS_IRQENABLE_SET_0 bit */ 68 #define USBOTGSS_COREIRQ_EN (1 << 0) 69 70 /* USBOTGSS_IRQENABLE_SET_1 bits */ 71 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) 72 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) 73 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) 74 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) 75 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) 76 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) 77 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) 78 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) 79 #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) 80 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) 81 82 /* 83 * USBOTGSS_WRAPPER registers 84 */ 85 struct omap_dwc_wrapper { 86 u32 revision; 87 88 u32 reserve_1[3]; 89 90 u32 sysconfig; /* offset of 0x10 */ 91 92 u32 reserve_2[3]; 93 u16 reserve_3; 94 95 u32 irqstatus_raw_0; /* offset of 0x24 */ 96 u32 irqstatus_0; 97 u32 irqenable_set_0; 98 u32 irqenable_clr_0; 99 100 u32 irqstatus_raw_1; /* offset of 0x34 */ 101 u32 irqstatus_1; 102 u32 irqenable_set_1; 103 u32 irqenable_clr_1; 104 105 u32 reserve_4[15]; 106 107 u32 utmi_otg_ctrl; /* offset of 0x80 */ 108 u32 utmi_otg_status; 109 110 u32 reserve_5[30]; 111 112 u32 mram_offset; /* offset of 0x100 */ 113 u32 fladj; 114 u32 dbg_config; 115 u32 dbg_data; 116 u32 dev_ebc_en; 117 }; 118 119 /* XHCI PHY register structure */ 120 struct omap_usb3_phy { 121 u32 reserve1; 122 u32 pll_status; 123 u32 pll_go; 124 u32 pll_config_1; 125 u32 pll_config_2; 126 u32 pll_config_3; 127 u32 pll_ssc_config_1; 128 u32 pll_ssc_config_2; 129 u32 pll_config_4; 130 }; 131 132 struct omap_xhci { 133 struct omap_dwc_wrapper *otg_wrapper; 134 struct omap_usb3_phy *usb3_phy; 135 struct xhci_hccr *hcd; 136 struct dwc3 *dwc3_reg; 137 }; 138 139 /* USB PHY functions */ 140 void omap_enable_phy(struct omap_xhci *omap); 141 void omap_reset_usb_phy(struct dwc3 *dwc3_reg); 142 void usb_phy_power(int on); 143 144 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */ 145