1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Inc, <www.ti.com> 4 * 5 * Author: Dan Murphy <dmurphy@ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _ASM_ARCH_XHCI_OMAP_H_ 11 #define _ASM_ARCH_XHCI_OMAP_H_ 12 13 #ifdef CONFIG_DRA7XX 14 #if CONFIG_USB_XHCI_DRA7XX_INDEX == 1 15 #define OMAP_XHCI_BASE 0x488d0000 16 #define OMAP_OCP1_SCP_BASE 0x4A081000 17 #define OMAP_OTG_WRAPPER_BASE 0x488c0000 18 #elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0 19 #define OMAP_XHCI_BASE 0x48890000 20 #define OMAP_OCP1_SCP_BASE 0x4A084c00 21 #define OMAP_OTG_WRAPPER_BASE 0x48880000 22 #endif /* CONFIG_USB_XHCI_DRA7XX_INDEX == 1 */ 23 #elif defined CONFIG_AM43XX 24 #define OMAP_XHCI_BASE 0x483d0000 25 #define OMAP_OCP1_SCP_BASE 0x483E8000 26 #define OMAP_OTG_WRAPPER_BASE 0x483dc100 27 #else 28 /* Default to the OMAP5 XHCI defines */ 29 #define OMAP_XHCI_BASE 0x4a030000 30 #define OMAP_OCP1_SCP_BASE 0x4a084c00 31 #define OMAP_OTG_WRAPPER_BASE 0x4A020000 32 #endif 33 34 /* Phy register MACRO definitions */ 35 #define PLL_REGM_MASK 0x001FFE00 36 #define PLL_REGM_SHIFT 0x9 37 #define PLL_REGM_F_MASK 0x0003FFFF 38 #define PLL_REGM_F_SHIFT 0x0 39 #define PLL_REGN_MASK 0x000001FE 40 #define PLL_REGN_SHIFT 0x1 41 #define PLL_SELFREQDCO_MASK 0x0000000E 42 #define PLL_SELFREQDCO_SHIFT 0x1 43 #define PLL_SD_MASK 0x0003FC00 44 #define PLL_SD_SHIFT 0x9 45 #define SET_PLL_GO 0x1 46 #define PLL_TICOPWDN 0x10000 47 #define PLL_LOCK 0x2 48 #define PLL_IDLE 0x1 49 50 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 51 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 52 #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) 53 #define USB3_PHY_RX_POWERON (1 << 14) 54 #define USB3_PHY_TX_POWERON (1 << 15) 55 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 56 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 57 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 58 59 /* USBOTGSS_WRAPPER definitions */ 60 #define USBOTGSS_WRAPRESET (1 << 17) 61 #define USBOTGSS_DMADISABLE (1 << 16) 62 #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) 63 #define USBOTGSS_STANDBYMODE_SMRT (1 << 5) 64 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 65 #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) 66 #define USBOTGSS_IDLEMODE_SMRT (1 << 3) 67 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 68 69 /* USBOTGSS_IRQENABLE_SET_0 bit */ 70 #define USBOTGSS_COREIRQ_EN (1 << 0) 71 72 /* USBOTGSS_IRQENABLE_SET_1 bits */ 73 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) 74 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) 75 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) 76 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) 77 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) 78 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) 79 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) 80 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) 81 #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) 82 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) 83 84 /* 85 * USBOTGSS_WRAPPER registers 86 */ 87 struct omap_dwc_wrapper { 88 u32 revision; 89 90 u32 reserve_1[3]; 91 92 u32 sysconfig; /* offset of 0x10 */ 93 94 u32 reserve_2[3]; 95 u16 reserve_3; 96 97 u32 irqstatus_raw_0; /* offset of 0x24 */ 98 u32 irqstatus_0; 99 u32 irqenable_set_0; 100 u32 irqenable_clr_0; 101 102 u32 irqstatus_raw_1; /* offset of 0x34 */ 103 u32 irqstatus_1; 104 u32 irqenable_set_1; 105 u32 irqenable_clr_1; 106 107 u32 reserve_4[15]; 108 109 u32 utmi_otg_ctrl; /* offset of 0x80 */ 110 u32 utmi_otg_status; 111 112 u32 reserve_5[30]; 113 114 u32 mram_offset; /* offset of 0x100 */ 115 u32 fladj; 116 u32 dbg_config; 117 u32 dbg_data; 118 u32 dev_ebc_en; 119 }; 120 121 /* XHCI PHY register structure */ 122 struct omap_usb3_phy { 123 u32 reserve1; 124 u32 pll_status; 125 u32 pll_go; 126 u32 pll_config_1; 127 u32 pll_config_2; 128 u32 pll_config_3; 129 u32 pll_ssc_config_1; 130 u32 pll_ssc_config_2; 131 u32 pll_config_4; 132 }; 133 134 struct omap_xhci { 135 struct omap_dwc_wrapper *otg_wrapper; 136 struct omap_usb3_phy *usb3_phy; 137 struct xhci_hccr *hcd; 138 struct dwc3 *dwc3_reg; 139 }; 140 141 /* USB PHY functions */ 142 void omap_enable_phy(struct omap_xhci *omap); 143 void omap_reset_usb_phy(struct dwc3 *dwc3_reg); 144 void usb_phy_power(int on); 145 146 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */ 147