1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Inc, <www.ti.com> 4 * 5 * Author: Dan Murphy <dmurphy@ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _ASM_ARCH_XHCI_OMAP_H_ 11 #define _ASM_ARCH_XHCI_OMAP_H_ 12 13 #ifdef CONFIG_DRA7XX 14 #define OMAP_XHCI_BASE 0x488d0000 15 #define OMAP_OCP1_SCP_BASE 0x4A081000 16 #define OMAP_OTG_WRAPPER_BASE 0x488c0000 17 #elif defined CONFIG_AM43XX 18 #define OMAP_XHCI_BASE 0x483d0000 19 #define OMAP_OCP1_SCP_BASE 0x483E8000 20 #define OMAP_OTG_WRAPPER_BASE 0x483dc100 21 #else 22 /* Default to the OMAP5 XHCI defines */ 23 #define OMAP_XHCI_BASE 0x4a030000 24 #define OMAP_OCP1_SCP_BASE 0x4a084c00 25 #define OMAP_OTG_WRAPPER_BASE 0x4A020000 26 #endif 27 28 /* Phy register MACRO definitions */ 29 #define PLL_REGM_MASK 0x001FFE00 30 #define PLL_REGM_SHIFT 0x9 31 #define PLL_REGM_F_MASK 0x0003FFFF 32 #define PLL_REGM_F_SHIFT 0x0 33 #define PLL_REGN_MASK 0x000001FE 34 #define PLL_REGN_SHIFT 0x1 35 #define PLL_SELFREQDCO_MASK 0x0000000E 36 #define PLL_SELFREQDCO_SHIFT 0x1 37 #define PLL_SD_MASK 0x0003FC00 38 #define PLL_SD_SHIFT 0x9 39 #define SET_PLL_GO 0x1 40 #define PLL_TICOPWDN 0x10000 41 #define PLL_LOCK 0x2 42 #define PLL_IDLE 0x1 43 44 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 45 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 46 #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) 47 #define USB3_PHY_RX_POWERON (1 << 14) 48 #define USB3_PHY_TX_POWERON (1 << 15) 49 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 50 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 51 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 52 53 /* USBOTGSS_WRAPPER definitions */ 54 #define USBOTGSS_WRAPRESET (1 << 17) 55 #define USBOTGSS_DMADISABLE (1 << 16) 56 #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) 57 #define USBOTGSS_STANDBYMODE_SMRT (1 << 5) 58 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 59 #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) 60 #define USBOTGSS_IDLEMODE_SMRT (1 << 3) 61 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 62 63 /* USBOTGSS_IRQENABLE_SET_0 bit */ 64 #define USBOTGSS_COREIRQ_EN (1 << 0) 65 66 /* USBOTGSS_IRQENABLE_SET_1 bits */ 67 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) 68 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) 69 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) 70 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) 71 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) 72 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) 73 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) 74 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) 75 #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) 76 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) 77 78 /* 79 * USBOTGSS_WRAPPER registers 80 */ 81 struct omap_dwc_wrapper { 82 u32 revision; 83 84 u32 reserve_1[3]; 85 86 u32 sysconfig; /* offset of 0x10 */ 87 88 u32 reserve_2[3]; 89 u16 reserve_3; 90 91 u32 irqstatus_raw_0; /* offset of 0x24 */ 92 u32 irqstatus_0; 93 u32 irqenable_set_0; 94 u32 irqenable_clr_0; 95 96 u32 irqstatus_raw_1; /* offset of 0x34 */ 97 u32 irqstatus_1; 98 u32 irqenable_set_1; 99 u32 irqenable_clr_1; 100 101 u32 reserve_4[15]; 102 103 u32 utmi_otg_ctrl; /* offset of 0x80 */ 104 u32 utmi_otg_status; 105 106 u32 reserve_5[30]; 107 108 u32 mram_offset; /* offset of 0x100 */ 109 u32 fladj; 110 u32 dbg_config; 111 u32 dbg_data; 112 u32 dev_ebc_en; 113 }; 114 115 /* XHCI PHY register structure */ 116 struct omap_usb3_phy { 117 u32 reserve1; 118 u32 pll_status; 119 u32 pll_go; 120 u32 pll_config_1; 121 u32 pll_config_2; 122 u32 pll_config_3; 123 u32 pll_ssc_config_1; 124 u32 pll_ssc_config_2; 125 u32 pll_config_4; 126 }; 127 128 struct omap_xhci { 129 struct omap_dwc_wrapper *otg_wrapper; 130 struct omap_usb3_phy *usb3_phy; 131 struct xhci_hccr *hcd; 132 struct dwc3 *dwc3_reg; 133 }; 134 135 /* USB PHY functions */ 136 void omap_enable_phy(struct omap_xhci *omap); 137 void omap_reset_usb_phy(struct dwc3 *dwc3_reg); 138 void usb_phy_power(int on); 139 140 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */ 141