1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 * 5 * FSL USB HOST xHCI Controller 6 * 7 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 8 */ 9 10 #ifndef _ASM_ARCH_XHCI_FSL_H_ 11 #define _ASM_ARCH_XHCI_FSL_H_ 12 13 /* Default to the FSL XHCI defines */ 14 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 15 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 16 #define USB3_PHY_PARTIAL_RX_POWERON BIT(6) 17 #define USB3_PHY_RX_POWERON BIT(14) 18 #define USB3_PHY_TX_POWERON BIT(15) 19 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 20 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 21 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 22 #define USB3_ENABLE_BEAT_BURST 0xF 23 #define USB3_ENABLE_BEAT_BURST_MASK 0xFF 24 #define USB3_SET_BEAT_BURST_LIMIT 0xF00 25 26 /* USBOTGSS_WRAPPER definitions */ 27 #define USBOTGSS_WRAPRESET BIT(17) 28 #define USBOTGSS_DMADISABLE BIT(16) 29 #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) 30 #define USBOTGSS_STANDBYMODE_SMRT BIT(5) 31 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 32 #define USBOTGSS_IDLEMODE_NOIDLE BIT(2) 33 #define USBOTGSS_IDLEMODE_SMRT BIT(3) 34 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 35 36 /* USBOTGSS_IRQENABLE_SET_0 bit */ 37 #define USBOTGSS_COREIRQ_EN BIT(1) 38 39 /* USBOTGSS_IRQENABLE_SET_1 bits */ 40 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) 41 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) 42 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) 43 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) 44 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) 45 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) 46 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) 47 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) 48 #define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) 49 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) 50 51 struct fsl_xhci { 52 struct xhci_hccr *hcd; 53 struct dwc3 *dwc3_reg; 54 }; 55 56 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) 57 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR 58 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 59 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 60 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) 61 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR 62 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR 63 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 64 #elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 65 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR 66 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR 67 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR 68 #endif 69 70 #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ 71 CONFIG_SYS_FSL_XHCI_USB2_ADDR, \ 72 CONFIG_SYS_FSL_XHCI_USB3_ADDR} 73 #endif /* _ASM_ARCH_XHCI_FSL_H_ */ 74