1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * FSL USB HOST xHCI Controller 5 * 6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _ASM_ARCH_XHCI_FSL_H_ 12 #define _ASM_ARCH_XHCI_FSL_H_ 13 14 /* Default to the FSL XHCI defines */ 15 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 16 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 17 #define USB3_PHY_PARTIAL_RX_POWERON BIT(6) 18 #define USB3_PHY_RX_POWERON BIT(14) 19 #define USB3_PHY_TX_POWERON BIT(15) 20 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 21 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 22 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 23 #define USB3_ENABLE_BEAT_BURST 0xF 24 #define USB3_ENABLE_BEAT_BURST_MASK 0xFF 25 #define USB3_SET_BEAT_BURST_LIMIT 0xF00 26 27 /* USBOTGSS_WRAPPER definitions */ 28 #define USBOTGSS_WRAPRESET BIT(17) 29 #define USBOTGSS_DMADISABLE BIT(16) 30 #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) 31 #define USBOTGSS_STANDBYMODE_SMRT BIT(5) 32 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 33 #define USBOTGSS_IDLEMODE_NOIDLE BIT(2) 34 #define USBOTGSS_IDLEMODE_SMRT BIT(3) 35 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 36 37 /* USBOTGSS_IRQENABLE_SET_0 bit */ 38 #define USBOTGSS_COREIRQ_EN BIT(1) 39 40 /* USBOTGSS_IRQENABLE_SET_1 bits */ 41 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) 42 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) 43 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) 44 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) 45 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) 46 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) 47 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) 48 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) 49 #define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) 50 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) 51 52 struct fsl_xhci { 53 struct xhci_hccr *hcd; 54 struct dwc3 *dwc3_reg; 55 }; 56 57 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) 58 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR 59 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 60 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 61 #elif defined(CONFIG_ARCH_LS2080A) 62 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR 63 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR 64 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 65 #elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 66 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR 67 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR 68 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR 69 #endif 70 71 #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ 72 CONFIG_SYS_FSL_XHCI_USB2_ADDR, \ 73 CONFIG_SYS_FSL_XHCI_USB3_ADDR} 74 #endif /* _ASM_ARCH_XHCI_FSL_H_ */ 75