1 /* include/linux/usb/dwc3.h 2 * 3 * Copyright (c) 2012 Samsung Electronics Co. Ltd 4 * 5 * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __DWC3_H_ 11 #define __DWC3_H_ 12 13 /* Global constants */ 14 #define DWC3_ENDPOINTS_NUM 32 15 16 #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE 17 #define DWC3_EVENT_TYPE_MASK 0xfe 18 19 #define DWC3_EVENT_TYPE_DEV 0 20 #define DWC3_EVENT_TYPE_CARKIT 3 21 #define DWC3_EVENT_TYPE_I2C 4 22 23 #define DWC3_DEVICE_EVENT_DISCONNECT 0 24 #define DWC3_DEVICE_EVENT_RESET 1 25 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 26 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 27 #define DWC3_DEVICE_EVENT_WAKEUP 4 28 #define DWC3_DEVICE_EVENT_EOPF 6 29 #define DWC3_DEVICE_EVENT_SOF 7 30 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 31 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 32 #define DWC3_DEVICE_EVENT_OVERFLOW 11 33 34 #define DWC3_GEVNTCOUNT_MASK 0xfffc 35 #define DWC3_GSNPSID_MASK 0xffff0000 36 #define DWC3_GSNPSID_SHIFT 16 37 #define DWC3_GSNPSREV_MASK 0xffff 38 39 #define DWC3_REVISION_MASK 0xffff 40 41 #define DWC3_REG_OFFSET 0xC100 42 43 struct g_event_buffer { 44 u32 g_evntadrlo; 45 u32 g_evntadrhi; 46 u32 g_evntsiz; 47 u32 g_evntcount; 48 }; 49 50 struct d_physical_endpoint { 51 u32 d_depcmdpar2; 52 u32 d_depcmdpar1; 53 u32 d_depcmdpar0; 54 u32 d_depcmd; 55 }; 56 57 struct dwc3 { /* offset: 0xC100 */ 58 u32 g_sbuscfg0; 59 u32 g_sbuscfg1; 60 u32 g_txthrcfg; 61 u32 g_rxthrcfg; 62 u32 g_ctl; 63 64 u32 reserved1; 65 66 u32 g_sts; 67 68 u32 reserved2; 69 70 u32 g_snpsid; 71 u32 g_gpio; 72 u32 g_uid; 73 u32 g_uctl; 74 u64 g_buserraddr; 75 u64 g_prtbimap; 76 77 u32 g_hwparams0; 78 u32 g_hwparams1; 79 u32 g_hwparams2; 80 u32 g_hwparams3; 81 u32 g_hwparams4; 82 u32 g_hwparams5; 83 u32 g_hwparams6; 84 u32 g_hwparams7; 85 86 u32 g_dbgfifospace; 87 u32 g_dbgltssm; 88 u32 g_dbglnmcc; 89 u32 g_dbgbmu; 90 u32 g_dbglspmux; 91 u32 g_dbglsp; 92 u32 g_dbgepinfo0; 93 u32 g_dbgepinfo1; 94 95 u64 g_prtbimap_hs; 96 u64 g_prtbimap_fs; 97 98 u32 reserved3[28]; 99 100 u32 g_usb2phycfg[16]; 101 u32 g_usb2i2cctl[16]; 102 u32 g_usb2phyacc[16]; 103 u32 g_usb3pipectl[16]; 104 105 u32 g_txfifosiz[32]; 106 u32 g_rxfifosiz[32]; 107 108 struct g_event_buffer g_evnt_buf[32]; 109 110 u32 g_hwparams8; 111 112 u32 reserved4[11]; 113 114 u32 g_fladj; 115 116 u32 reserved5[51]; 117 118 u32 d_cfg; 119 u32 d_ctl; 120 u32 d_evten; 121 u32 d_sts; 122 u32 d_gcmdpar; 123 u32 d_gcmd; 124 125 u32 reserved6[2]; 126 127 u32 d_alepena; 128 129 u32 reserved7[55]; 130 131 struct d_physical_endpoint d_phy_ep_cmd[32]; 132 133 u32 reserved8[128]; 134 135 u32 o_cfg; 136 u32 o_ctl; 137 u32 o_evt; 138 u32 o_evten; 139 u32 o_sts; 140 141 u32 reserved9[3]; 142 143 u32 adp_cfg; 144 u32 adp_ctl; 145 u32 adp_evt; 146 u32 adp_evten; 147 148 u32 bc_cfg; 149 150 u32 reserved10; 151 152 u32 bc_evt; 153 u32 bc_evten; 154 }; 155 156 /* Global Configuration Register */ 157 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 158 #define DWC3_GCTL_U2RSTECN (1 << 16) 159 #define DWC3_GCTL_RAMCLKSEL(x) \ 160 (((x) & DWC3_GCTL_CLK_MASK) << 6) 161 #define DWC3_GCTL_CLK_BUS (0) 162 #define DWC3_GCTL_CLK_PIPE (1) 163 #define DWC3_GCTL_CLK_PIPEHALF (2) 164 #define DWC3_GCTL_CLK_MASK (3) 165 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 166 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 167 #define DWC3_GCTL_PRTCAP_HOST 1 168 #define DWC3_GCTL_PRTCAP_DEVICE 2 169 #define DWC3_GCTL_PRTCAP_OTG 3 170 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 171 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 172 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 173 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 174 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 175 176 /* Global HWPARAMS1 Register */ 177 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 178 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 179 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 180 181 /* Global USB2 PHY Configuration Register */ 182 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 183 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) 184 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) 185 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 186 #define DWC3_GUSB2PHYCFG_PHYIF (1 << 3) 187 188 /* Global USB2 PHY Configuration Mask */ 189 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) 190 191 /* Global USB2 PHY Configuration Offset */ 192 #define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10 193 194 #define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ 195 DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) 196 #define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ 197 DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) 198 199 /* Global USB3 PIPE Control Register */ 200 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 201 #define DWC3_GUSB3PIPECTL_DISRXDETP3 (1 << 28) 202 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 203 204 /* Global TX Fifo Size Register */ 205 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 206 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 207 208 /* Device Control Register */ 209 #define DWC3_DCTL_RUN_STOP (1 << 31) 210 #define DWC3_DCTL_CSFTRST (1 << 30) 211 #define DWC3_DCTL_LSFTRST (1 << 29) 212 213 /* Global Frame Length Adjustment Register */ 214 #define GFLADJ_30MHZ_REG_SEL (1 << 7) 215 #define GFLADJ_30MHZ(n) ((n) & 0x3f) 216 #define GFLADJ_30MHZ_DEFAULT 0x20 217 218 #ifdef CONFIG_USB_XHCI_DWC3 219 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode); 220 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg); 221 int dwc3_core_init(struct dwc3 *dwc3_reg); 222 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val); 223 #endif 224 #endif /* __DWC3_H_ */ 225