1*f3fcf92dSVipin KUMAR /* 2*f3fcf92dSVipin KUMAR * (C) Copyright 2009 3*f3fcf92dSVipin KUMAR * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4*f3fcf92dSVipin KUMAR * 5*f3fcf92dSVipin KUMAR * See file CREDITS for list of people who contributed to this 6*f3fcf92dSVipin KUMAR * project. 7*f3fcf92dSVipin KUMAR * 8*f3fcf92dSVipin KUMAR * This program is free software; you can redistribute it and/or 9*f3fcf92dSVipin KUMAR * modify it under the terms of the GNU General Public License as 10*f3fcf92dSVipin KUMAR * published by the Free Software Foundation; either version 2 of 11*f3fcf92dSVipin KUMAR * the License, or (at your option) any later version. 12*f3fcf92dSVipin KUMAR * 13*f3fcf92dSVipin KUMAR * This program is distributed in the hope that it will be useful, 14*f3fcf92dSVipin KUMAR * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*f3fcf92dSVipin KUMAR * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*f3fcf92dSVipin KUMAR * GNU General Public License for more details. 17*f3fcf92dSVipin KUMAR * 18*f3fcf92dSVipin KUMAR * You should have received a copy of the GNU General Public License 19*f3fcf92dSVipin KUMAR * along with this program; if not, write to the Free Software 20*f3fcf92dSVipin KUMAR * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*f3fcf92dSVipin KUMAR * MA 02111-1307 USA 22*f3fcf92dSVipin KUMAR */ 23*f3fcf92dSVipin KUMAR 24*f3fcf92dSVipin KUMAR #ifndef ST_SMI_H 25*f3fcf92dSVipin KUMAR #define ST_SMI_H 26*f3fcf92dSVipin KUMAR 27*f3fcf92dSVipin KUMAR /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ 28*f3fcf92dSVipin KUMAR /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ 29*f3fcf92dSVipin KUMAR 30*f3fcf92dSVipin KUMAR #define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE 31*f3fcf92dSVipin KUMAR #define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE 32*f3fcf92dSVipin KUMAR 33*f3fcf92dSVipin KUMAR #define SMIBANK0_BASE (FLASH_START_ADDRESS) 34*f3fcf92dSVipin KUMAR #define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) 35*f3fcf92dSVipin KUMAR #define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) 36*f3fcf92dSVipin KUMAR #define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) 37*f3fcf92dSVipin KUMAR 38*f3fcf92dSVipin KUMAR #define BANK0 0 39*f3fcf92dSVipin KUMAR #define BANK1 1 40*f3fcf92dSVipin KUMAR #define BANK2 2 41*f3fcf92dSVipin KUMAR #define BANK3 3 42*f3fcf92dSVipin KUMAR 43*f3fcf92dSVipin KUMAR struct smi_regs { 44*f3fcf92dSVipin KUMAR u32 smi_cr1; 45*f3fcf92dSVipin KUMAR u32 smi_cr2; 46*f3fcf92dSVipin KUMAR u32 smi_sr; 47*f3fcf92dSVipin KUMAR u32 smi_tr; 48*f3fcf92dSVipin KUMAR u32 smi_rr; 49*f3fcf92dSVipin KUMAR }; 50*f3fcf92dSVipin KUMAR 51*f3fcf92dSVipin KUMAR /* CONTROL REG 1 */ 52*f3fcf92dSVipin KUMAR #define BANK_EN 0x0000000F /* enables all banks */ 53*f3fcf92dSVipin KUMAR #define DSEL_TIME 0x00000060 /* Deselect time */ 54*f3fcf92dSVipin KUMAR #define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ 55*f3fcf92dSVipin KUMAR #define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ 56*f3fcf92dSVipin KUMAR #define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ 57*f3fcf92dSVipin KUMAR #define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ 58*f3fcf92dSVipin KUMAR #define SW_MODE 0x10000000 /* enables SW Mode */ 59*f3fcf92dSVipin KUMAR #define WB_MODE 0x20000000 /* Write Burst Mode */ 60*f3fcf92dSVipin KUMAR #define FAST_MODE 0x00008000 /* Fast Mode */ 61*f3fcf92dSVipin KUMAR #define HOLD1 0x00010000 62*f3fcf92dSVipin KUMAR 63*f3fcf92dSVipin KUMAR /* CONTROL REG 2 */ 64*f3fcf92dSVipin KUMAR #define RD_STATUS_REG 0x00000400 /* reads status reg */ 65*f3fcf92dSVipin KUMAR #define WE 0x00000800 /* Write Enable */ 66*f3fcf92dSVipin KUMAR #define BANK0_SEL 0x00000000 /* Select Banck0 */ 67*f3fcf92dSVipin KUMAR #define BANK1_SEL 0x00001000 /* Select Banck1 */ 68*f3fcf92dSVipin KUMAR #define BANK2_SEL 0x00002000 /* Select Banck2 */ 69*f3fcf92dSVipin KUMAR #define BANK3_SEL 0x00003000 /* Select Banck3 */ 70*f3fcf92dSVipin KUMAR #define BANKSEL_SHIFT 12 71*f3fcf92dSVipin KUMAR #define SEND 0x00000080 /* Send data */ 72*f3fcf92dSVipin KUMAR #define TX_LEN_1 0x00000001 /* data length = 1 byte */ 73*f3fcf92dSVipin KUMAR #define TX_LEN_2 0x00000002 /* data length = 2 byte */ 74*f3fcf92dSVipin KUMAR #define TX_LEN_3 0x00000003 /* data length = 3 byte */ 75*f3fcf92dSVipin KUMAR #define TX_LEN_4 0x00000004 /* data length = 4 byte */ 76*f3fcf92dSVipin KUMAR #define RX_LEN_1 0x00000010 /* data length = 1 byte */ 77*f3fcf92dSVipin KUMAR #define RX_LEN_2 0x00000020 /* data length = 2 byte */ 78*f3fcf92dSVipin KUMAR #define RX_LEN_3 0x00000030 /* data length = 3 byte */ 79*f3fcf92dSVipin KUMAR #define RX_LEN_4 0x00000040 /* data length = 4 byte */ 80*f3fcf92dSVipin KUMAR #define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ 81*f3fcf92dSVipin KUMAR #define WCIE 0x00000200 /* WCF Interrupt Enable */ 82*f3fcf92dSVipin KUMAR 83*f3fcf92dSVipin KUMAR /* STATUS_REG */ 84*f3fcf92dSVipin KUMAR #define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ 85*f3fcf92dSVipin KUMAR #define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ 86*f3fcf92dSVipin KUMAR #define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ 87*f3fcf92dSVipin KUMAR #define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ 88*f3fcf92dSVipin KUMAR #define RSR 0x00000005 /* Read Status regiser */ 89*f3fcf92dSVipin KUMAR #define TFF 0x00000100 /* Transfer Finished FLag */ 90*f3fcf92dSVipin KUMAR #define WCF 0x00000200 /* Transfer Finished FLag */ 91*f3fcf92dSVipin KUMAR #define ERF1 0x00000400 /* Error Flag 1 */ 92*f3fcf92dSVipin KUMAR #define ERF2 0x00000800 /* Error Flag 2 */ 93*f3fcf92dSVipin KUMAR #define WM0 0x00001000 /* WM Bank 0 */ 94*f3fcf92dSVipin KUMAR #define WM1 0x00002000 /* WM Bank 1 */ 95*f3fcf92dSVipin KUMAR #define WM2 0x00004000 /* WM Bank 2 */ 96*f3fcf92dSVipin KUMAR #define WM3 0x00008000 /* WM Bank 3 */ 97*f3fcf92dSVipin KUMAR #define WM_SHIFT 12 98*f3fcf92dSVipin KUMAR 99*f3fcf92dSVipin KUMAR /* TR REG */ 100*f3fcf92dSVipin KUMAR #define READ_ID 0x0000009F /* Read Identification */ 101*f3fcf92dSVipin KUMAR #define BULK_ERASE 0x000000C7 /* BULK erase */ 102*f3fcf92dSVipin KUMAR #define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ 103*f3fcf92dSVipin KUMAR #define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ 104*f3fcf92dSVipin KUMAR 105*f3fcf92dSVipin KUMAR struct flash_dev { 106*f3fcf92dSVipin KUMAR u32 density; 107*f3fcf92dSVipin KUMAR ulong size; 108*f3fcf92dSVipin KUMAR ushort sector_count; 109*f3fcf92dSVipin KUMAR }; 110*f3fcf92dSVipin KUMAR 111*f3fcf92dSVipin KUMAR #define SFLASH_PAGE_SIZE 0x100 /* flash page size */ 112*f3fcf92dSVipin KUMAR #define XFER_FINISH_TOUT 2 /* xfer finish timeout */ 113*f3fcf92dSVipin KUMAR #define WMODE_TOUT 2 /* write enable timeout */ 114*f3fcf92dSVipin KUMAR 115*f3fcf92dSVipin KUMAR extern void smi_init(void); 116*f3fcf92dSVipin KUMAR 117*f3fcf92dSVipin KUMAR #endif 118