1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 */ 8 #ifndef __LINUX_MTD_SPINAND_H 9 #define __LINUX_MTD_SPINAND_H 10 11 #ifndef __UBOOT__ 12 #include <linux/mutex.h> 13 #include <linux/bitops.h> 14 #include <linux/device.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/nand.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spi/spi-mem.h> 19 #else 20 #include <common.h> 21 #include <spi.h> 22 #include <spi-mem.h> 23 #include <linux/mtd/nand.h> 24 #endif 25 26 /** 27 * Standard SPI NAND flash operations 28 */ 29 30 #define SPINAND_RESET_OP \ 31 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \ 32 SPI_MEM_OP_NO_ADDR, \ 33 SPI_MEM_OP_NO_DUMMY, \ 34 SPI_MEM_OP_NO_DATA) 35 36 #define SPINAND_WR_EN_DIS_OP(enable) \ 37 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ 38 SPI_MEM_OP_NO_ADDR, \ 39 SPI_MEM_OP_NO_DUMMY, \ 40 SPI_MEM_OP_NO_DATA) 41 42 #define SPINAND_READID_OP(ndummy, buf, len) \ 43 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ 44 SPI_MEM_OP_NO_ADDR, \ 45 SPI_MEM_OP_DUMMY(ndummy, 1), \ 46 SPI_MEM_OP_DATA_IN(len, buf, 1)) 47 48 #define SPINAND_SET_FEATURE_OP(reg, valptr) \ 49 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ 50 SPI_MEM_OP_ADDR(1, reg, 1), \ 51 SPI_MEM_OP_NO_DUMMY, \ 52 SPI_MEM_OP_DATA_OUT(1, valptr, 1)) 53 54 #define SPINAND_GET_FEATURE_OP(reg, valptr) \ 55 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \ 56 SPI_MEM_OP_ADDR(1, reg, 1), \ 57 SPI_MEM_OP_NO_DUMMY, \ 58 SPI_MEM_OP_DATA_IN(1, valptr, 1)) 59 60 #define SPINAND_BLK_ERASE_OP(addr) \ 61 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \ 62 SPI_MEM_OP_ADDR(3, addr, 1), \ 63 SPI_MEM_OP_NO_DUMMY, \ 64 SPI_MEM_OP_NO_DATA) 65 66 #define SPINAND_PAGE_READ_OP(addr) \ 67 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \ 68 SPI_MEM_OP_ADDR(3, addr, 1), \ 69 SPI_MEM_OP_NO_DUMMY, \ 70 SPI_MEM_OP_NO_DATA) 71 72 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \ 73 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ 74 SPI_MEM_OP_ADDR(2, addr, 1), \ 75 SPI_MEM_OP_DUMMY(ndummy, 1), \ 76 SPI_MEM_OP_DATA_IN(len, buf, 1)) 77 78 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ 79 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 80 SPI_MEM_OP_ADDR(2, addr, 1), \ 81 SPI_MEM_OP_DUMMY(ndummy, 1), \ 82 SPI_MEM_OP_DATA_IN(len, buf, 2)) 83 84 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ 85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 86 SPI_MEM_OP_ADDR(2, addr, 1), \ 87 SPI_MEM_OP_DUMMY(ndummy, 1), \ 88 SPI_MEM_OP_DATA_IN(len, buf, 4)) 89 90 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ 91 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 92 SPI_MEM_OP_ADDR(2, addr, 2), \ 93 SPI_MEM_OP_DUMMY(ndummy, 2), \ 94 SPI_MEM_OP_DATA_IN(len, buf, 2)) 95 96 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \ 97 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 98 SPI_MEM_OP_ADDR(2, addr, 4), \ 99 SPI_MEM_OP_DUMMY(ndummy, 4), \ 100 SPI_MEM_OP_DATA_IN(len, buf, 4)) 101 102 #define SPINAND_PROG_EXEC_OP(addr) \ 103 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ 104 SPI_MEM_OP_ADDR(3, addr, 1), \ 105 SPI_MEM_OP_NO_DUMMY, \ 106 SPI_MEM_OP_NO_DATA) 107 108 #define SPINAND_PROG_LOAD(reset, addr, buf, len) \ 109 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \ 110 SPI_MEM_OP_ADDR(2, addr, 1), \ 111 SPI_MEM_OP_NO_DUMMY, \ 112 SPI_MEM_OP_DATA_OUT(len, buf, 1)) 113 114 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \ 115 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \ 116 SPI_MEM_OP_ADDR(2, addr, 1), \ 117 SPI_MEM_OP_NO_DUMMY, \ 118 SPI_MEM_OP_DATA_OUT(len, buf, 4)) 119 120 /** 121 * Standard SPI NAND flash commands 122 */ 123 #define SPINAND_CMD_PROG_LOAD_X4 0x32 124 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34 125 126 /* feature register */ 127 #define REG_BLOCK_LOCK 0xa0 128 #define BL_ALL_UNLOCKED 0x00 129 130 /* configuration register */ 131 #define REG_CFG 0xb0 132 #define CFG_OTP_ENABLE BIT(6) 133 #define CFG_ECC_ENABLE BIT(4) 134 #define CFG_QUAD_ENABLE BIT(0) 135 136 /* status register */ 137 #define REG_STATUS 0xc0 138 #define STATUS_BUSY BIT(0) 139 #define STATUS_ERASE_FAILED BIT(2) 140 #define STATUS_PROG_FAILED BIT(3) 141 #define STATUS_ECC_MASK GENMASK(5, 4) 142 #define STATUS_ECC_NO_BITFLIPS (0 << 4) 143 #define STATUS_ECC_HAS_BITFLIPS (1 << 4) 144 #define STATUS_ECC_UNCOR_ERROR (2 << 4) 145 146 struct spinand_op; 147 struct spinand_device; 148 149 #define SPINAND_MAX_ID_LEN 4 150 151 /** 152 * struct spinand_id - SPI NAND id structure 153 * @data: buffer containing the id bytes. Currently 4 bytes large, but can 154 * be extended if required 155 * @len: ID length 156 * 157 * struct_spinand_id->data contains all bytes returned after a READ_ID command, 158 * including dummy bytes if the chip does not emit ID bytes right after the 159 * READ_ID command. The responsibility to extract real ID bytes is left to 160 * struct_manufacurer_ops->detect(). 161 */ 162 struct spinand_id { 163 u8 data[SPINAND_MAX_ID_LEN]; 164 int len; 165 }; 166 167 /** 168 * struct manufacurer_ops - SPI NAND manufacturer specific operations 169 * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed 170 * the core calls the struct_manufacurer_ops->detect() hook of each 171 * registered manufacturer until one of them return 1. Note that 172 * the first thing to check in this hook is that the manufacturer ID 173 * in struct_spinand_device->id matches the manufacturer whose 174 * ->detect() hook has been called. Should return 1 if there's a 175 * match, 0 if the manufacturer ID does not match and a negative 176 * error code otherwise. When true is returned, the core assumes 177 * that properties of the NAND chip (spinand->base.memorg and 178 * spinand->base.eccreq) have been filled 179 * @init: initialize a SPI NAND device 180 * @cleanup: cleanup a SPI NAND device 181 * 182 * Each SPI NAND manufacturer driver should implement this interface so that 183 * NAND chips coming from this vendor can be detected and initialized properly. 184 */ 185 struct spinand_manufacturer_ops { 186 int (*detect)(struct spinand_device *spinand); 187 int (*init)(struct spinand_device *spinand); 188 void (*cleanup)(struct spinand_device *spinand); 189 }; 190 191 /** 192 * struct spinand_manufacturer - SPI NAND manufacturer instance 193 * @id: manufacturer ID 194 * @name: manufacturer name 195 * @ops: manufacturer operations 196 */ 197 struct spinand_manufacturer { 198 u8 id; 199 char *name; 200 const struct spinand_manufacturer_ops *ops; 201 }; 202 203 /* SPI NAND manufacturers */ 204 extern const struct spinand_manufacturer macronix_spinand_manufacturer; 205 extern const struct spinand_manufacturer micron_spinand_manufacturer; 206 extern const struct spinand_manufacturer winbond_spinand_manufacturer; 207 208 /** 209 * struct spinand_op_variants - SPI NAND operation variants 210 * @ops: the list of variants for a given operation 211 * @nops: the number of variants 212 * 213 * Some operations like read-from-cache/write-to-cache have several variants 214 * depending on the number of IO lines you use to transfer data or address 215 * cycles. This structure is a way to describe the different variants supported 216 * by a chip and let the core pick the best one based on the SPI mem controller 217 * capabilities. 218 */ 219 struct spinand_op_variants { 220 const struct spi_mem_op *ops; 221 unsigned int nops; 222 }; 223 224 #define SPINAND_OP_VARIANTS(name, ...) \ 225 const struct spinand_op_variants name = { \ 226 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \ 227 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \ 228 sizeof(struct spi_mem_op), \ 229 } 230 231 /** 232 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND 233 * chip 234 * @get_status: get the ECC status. Should return a positive number encoding 235 * the number of corrected bitflips if correction was possible or 236 * -EBADMSG if there are uncorrectable errors. I can also return 237 * other negative error codes if the error is not caused by 238 * uncorrectable bitflips 239 * @ooblayout: the OOB layout used by the on-die ECC implementation 240 */ 241 struct spinand_ecc_info { 242 int (*get_status)(struct spinand_device *spinand, u8 status); 243 const struct mtd_ooblayout_ops *ooblayout; 244 }; 245 246 #define SPINAND_HAS_QE_BIT BIT(0) 247 248 /** 249 * struct spinand_info - Structure used to describe SPI NAND chips 250 * @model: model name 251 * @devid: device ID 252 * @flags: OR-ing of the SPINAND_XXX flags 253 * @memorg: memory organization 254 * @eccreq: ECC requirements 255 * @eccinfo: on-die ECC info 256 * @op_variants: operations variants 257 * @op_variants.read_cache: variants of the read-cache operation 258 * @op_variants.write_cache: variants of the write-cache operation 259 * @op_variants.update_cache: variants of the update-cache operation 260 * @select_target: function used to select a target/die. Required only for 261 * multi-die chips 262 * 263 * Each SPI NAND manufacturer driver should have a spinand_info table 264 * describing all the chips supported by the driver. 265 */ 266 struct spinand_info { 267 const char *model; 268 u8 devid; 269 u32 flags; 270 struct nand_memory_organization memorg; 271 struct nand_ecc_req eccreq; 272 struct spinand_ecc_info eccinfo; 273 struct { 274 const struct spinand_op_variants *read_cache; 275 const struct spinand_op_variants *write_cache; 276 const struct spinand_op_variants *update_cache; 277 } op_variants; 278 int (*select_target)(struct spinand_device *spinand, 279 unsigned int target); 280 }; 281 282 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ 283 { \ 284 .read_cache = __read, \ 285 .write_cache = __write, \ 286 .update_cache = __update, \ 287 } 288 289 #define SPINAND_ECCINFO(__ooblayout, __get_status) \ 290 .eccinfo = { \ 291 .ooblayout = __ooblayout, \ 292 .get_status = __get_status, \ 293 } 294 295 #define SPINAND_SELECT_TARGET(__func) \ 296 .select_target = __func, 297 298 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ 299 __flags, ...) \ 300 { \ 301 .model = __model, \ 302 .devid = __id, \ 303 .memorg = __memorg, \ 304 .eccreq = __eccreq, \ 305 .op_variants = __op_variants, \ 306 .flags = __flags, \ 307 __VA_ARGS__ \ 308 } 309 310 /** 311 * struct spinand_device - SPI NAND device instance 312 * @base: NAND device instance 313 * @slave: pointer to the SPI slave object 314 * @lock: lock used to serialize accesses to the NAND 315 * @id: NAND ID as returned by READ_ID 316 * @flags: NAND flags 317 * @op_templates: various SPI mem op templates 318 * @op_templates.read_cache: read cache op template 319 * @op_templates.write_cache: write cache op template 320 * @op_templates.update_cache: update cache op template 321 * @select_target: select a specific target/die. Usually called before sending 322 * a command addressing a page or an eraseblock embedded in 323 * this die. Only required if your chip exposes several dies 324 * @cur_target: currently selected target/die 325 * @eccinfo: on-die ECC information 326 * @cfg_cache: config register cache. One entry per die 327 * @databuf: bounce buffer for data 328 * @oobbuf: bounce buffer for OOB data 329 * @scratchbuf: buffer used for everything but page accesses. This is needed 330 * because the spi-mem interface explicitly requests that buffers 331 * passed in spi_mem_op be DMA-able, so we can't based the bufs on 332 * the stack 333 * @manufacturer: SPI NAND manufacturer information 334 * @priv: manufacturer private data 335 */ 336 struct spinand_device { 337 struct nand_device base; 338 #ifndef __UBOOT__ 339 struct spi_mem *spimem; 340 struct mutex lock; 341 #else 342 struct spi_slave *slave; 343 #endif 344 struct spinand_id id; 345 u32 flags; 346 347 struct { 348 const struct spi_mem_op *read_cache; 349 const struct spi_mem_op *write_cache; 350 const struct spi_mem_op *update_cache; 351 } op_templates; 352 353 int (*select_target)(struct spinand_device *spinand, 354 unsigned int target); 355 unsigned int cur_target; 356 357 struct spinand_ecc_info eccinfo; 358 359 u8 *cfg_cache; 360 u8 *databuf; 361 u8 *oobbuf; 362 u8 *scratchbuf; 363 const struct spinand_manufacturer *manufacturer; 364 void *priv; 365 }; 366 367 /** 368 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance 369 * @mtd: MTD instance 370 * 371 * Return: the SPI NAND device attached to @mtd. 372 */ 373 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd) 374 { 375 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base); 376 } 377 378 /** 379 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device 380 * @spinand: SPI NAND device 381 * 382 * Return: the MTD device embedded in @spinand. 383 */ 384 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand) 385 { 386 return nanddev_to_mtd(&spinand->base); 387 } 388 389 /** 390 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object 391 * @nand: NAND object 392 * 393 * Return: the SPI NAND device embedding @nand. 394 */ 395 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand) 396 { 397 return container_of(nand, struct spinand_device, base); 398 } 399 400 /** 401 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object 402 * @spinand: SPI NAND device 403 * 404 * Return: the NAND device embedded in @spinand. 405 */ 406 static inline struct nand_device * 407 spinand_to_nand(struct spinand_device *spinand) 408 { 409 return &spinand->base; 410 } 411 412 /** 413 * spinand_set_of_node - Attach a DT node to a SPI NAND device 414 * @spinand: SPI NAND device 415 * @np: DT node 416 * 417 * Attach a DT node to a SPI NAND device. 418 */ 419 static inline void spinand_set_of_node(struct spinand_device *spinand, 420 const struct device_node *np) 421 { 422 nanddev_set_of_node(&spinand->base, np); 423 } 424 425 int spinand_match_and_init(struct spinand_device *dev, 426 const struct spinand_info *table, 427 unsigned int table_size, u8 devid); 428 429 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); 430 int spinand_select_target(struct spinand_device *spinand, unsigned int target); 431 432 #endif /* __LINUX_MTD_SPINAND_H */ 433