1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2014 Freescale Semiconductor, Inc. 4 * Synced from Linux v4.19 5 */ 6 7 #ifndef __LINUX_MTD_SPI_NOR_H 8 #define __LINUX_MTD_SPI_NOR_H 9 10 #include <linux/bitops.h> 11 #include <linux/mtd/cfi.h> 12 #include <linux/mtd/mtd.h> 13 14 /* 15 * Manufacturer IDs 16 * 17 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. 18 * Sometimes these are the same as CFI IDs, but sometimes they aren't. 19 */ 20 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL 21 #define SNOR_MFR_GIGADEVICE 0xc8 22 #define SNOR_MFR_INTEL CFI_MFR_INTEL 23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */ 24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */ 25 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX 26 #define SNOR_MFR_SPANSION CFI_MFR_AMD 27 #define SNOR_MFR_SST CFI_MFR_SST 28 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ 29 30 /* 31 * Note on opcode nomenclature: some opcodes have a format like 32 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number 33 * of I/O lines used for the opcode, address, and data (respectively). The 34 * FUNCTION has an optional suffix of '4', to represent an opcode which 35 * requires a 4-byte (32-bit) address. 36 */ 37 38 /* Flash opcodes. */ 39 #define SPINOR_OP_WREN 0x06 /* Write enable */ 40 #define SPINOR_OP_RDSR 0x05 /* Read status register */ 41 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ 42 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ 43 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ 44 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ 45 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ 46 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ 47 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ 48 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ 49 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ 50 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ 51 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */ 52 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ 53 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ 54 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ 55 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ 56 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 57 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ 58 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ 59 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ 60 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ 61 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ 62 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ 63 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ 64 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ 65 66 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ 67 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ 68 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */ 69 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */ 70 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ 71 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ 72 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ 73 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ 74 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ 75 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ 76 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ 77 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ 78 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ 79 80 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ 81 #define SPINOR_OP_READ_1_1_1_DTR 0x0d 82 #define SPINOR_OP_READ_1_2_2_DTR 0xbd 83 #define SPINOR_OP_READ_1_4_4_DTR 0xed 84 85 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e 86 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe 87 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee 88 89 /* Used for SST flashes only. */ 90 #define SPINOR_OP_BP 0x02 /* Byte program */ 91 #define SPINOR_OP_WRDI 0x04 /* Write disable */ 92 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ 93 94 /* Used for S3AN flashes only */ 95 #define SPINOR_OP_XSE 0x50 /* Sector erase */ 96 #define SPINOR_OP_XPP 0x82 /* Page program */ 97 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */ 98 99 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ 100 #define XSR_RDY BIT(7) /* Ready */ 101 102 /* Used for Macronix and Winbond flashes. */ 103 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ 104 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ 105 106 /* Used for Spansion flashes only. */ 107 #define SPINOR_OP_BRWR 0x17 /* Bank register write */ 108 #define SPINOR_OP_BRRD 0x16 /* Bank register read */ 109 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ 110 111 /* Used for Micron flashes only. */ 112 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ 113 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ 114 115 /* Status Register bits. */ 116 #define SR_WIP BIT(0) /* Write in progress */ 117 #define SR_WEL BIT(1) /* Write enable latch */ 118 /* meaning of other SR_* bits may differ between vendors */ 119 #define SR_BP0 BIT(2) /* Block protect 0 */ 120 #define SR_BP1 BIT(3) /* Block protect 1 */ 121 #define SR_BP2 BIT(4) /* Block protect 2 */ 122 #define SR_TB BIT(5) /* Top/Bottom protect */ 123 #define SR_SRWD BIT(7) /* SR write protect */ 124 /* Spansion/Cypress specific status bits */ 125 #define SR_E_ERR BIT(5) 126 #define SR_P_ERR BIT(6) 127 128 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ 129 130 /* Enhanced Volatile Configuration Register bits */ 131 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ 132 133 /* Flag Status Register bits */ 134 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ 135 #define FSR_E_ERR BIT(5) /* Erase operation status */ 136 #define FSR_P_ERR BIT(4) /* Program operation status */ 137 #define FSR_PT_ERR BIT(1) /* Protection error bit */ 138 139 /* Configuration Register bits. */ 140 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ 141 142 /* Status Register 2 bits. */ 143 #define SR2_QUAD_EN_BIT7 BIT(7) 144 145 /* Supported SPI protocols */ 146 #define SNOR_PROTO_INST_MASK GENMASK(23, 16) 147 #define SNOR_PROTO_INST_SHIFT 16 148 #define SNOR_PROTO_INST(_nbits) \ 149 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \ 150 SNOR_PROTO_INST_MASK) 151 152 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8) 153 #define SNOR_PROTO_ADDR_SHIFT 8 154 #define SNOR_PROTO_ADDR(_nbits) \ 155 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \ 156 SNOR_PROTO_ADDR_MASK) 157 158 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0) 159 #define SNOR_PROTO_DATA_SHIFT 0 160 #define SNOR_PROTO_DATA(_nbits) \ 161 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \ 162 SNOR_PROTO_DATA_MASK) 163 164 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ 165 166 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ 167 (SNOR_PROTO_INST(_inst_nbits) | \ 168 SNOR_PROTO_ADDR(_addr_nbits) | \ 169 SNOR_PROTO_DATA(_data_nbits)) 170 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \ 171 (SNOR_PROTO_IS_DTR | \ 172 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)) 173 174 enum spi_nor_protocol { 175 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1), 176 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2), 177 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4), 178 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8), 179 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2), 180 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4), 181 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8), 182 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2), 183 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4), 184 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8), 185 186 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1), 187 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2), 188 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4), 189 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8), 190 }; 191 192 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) 193 { 194 return !!(proto & SNOR_PROTO_IS_DTR); 195 } 196 197 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) 198 { 199 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >> 200 SNOR_PROTO_INST_SHIFT; 201 } 202 203 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto) 204 { 205 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >> 206 SNOR_PROTO_ADDR_SHIFT; 207 } 208 209 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto) 210 { 211 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >> 212 SNOR_PROTO_DATA_SHIFT; 213 } 214 215 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto) 216 { 217 return spi_nor_get_protocol_data_nbits(proto); 218 } 219 220 #define SPI_NOR_MAX_CMD_SIZE 8 221 enum spi_nor_ops { 222 SPI_NOR_OPS_READ = 0, 223 SPI_NOR_OPS_WRITE, 224 SPI_NOR_OPS_ERASE, 225 SPI_NOR_OPS_LOCK, 226 SPI_NOR_OPS_UNLOCK, 227 }; 228 229 enum spi_nor_option_flags { 230 SNOR_F_USE_FSR = BIT(0), 231 SNOR_F_HAS_SR_TB = BIT(1), 232 SNOR_F_NO_OP_CHIP_ERASE = BIT(2), 233 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3), 234 SNOR_F_READY_XSR_RDY = BIT(4), 235 SNOR_F_USE_CLSR = BIT(5), 236 SNOR_F_BROKEN_RESET = BIT(6), 237 }; 238 239 /** 240 * struct flash_info - Forward declaration of a structure used internally by 241 * spi_nor_scan() 242 */ 243 struct flash_info; 244 245 /* TODO: Remove, once all users of spi_flash interface are moved to MTD */ 246 #define spi_flash spi_nor 247 248 /** 249 * struct spi_nor - Structure for defining a the SPI NOR layer 250 * @mtd: point to a mtd_info structure 251 * @lock: the lock for the read/write/erase/lock/unlock operations 252 * @dev: point to a spi device, or a spi nor controller device. 253 * @info: spi-nor part JDEC MFR id and other info 254 * @page_size: the page size of the SPI NOR 255 * @addr_width: number of address bytes 256 * @erase_opcode: the opcode for erasing a sector 257 * @read_opcode: the read opcode 258 * @read_dummy: the dummy needed by the read operation 259 * @program_opcode: the program opcode 260 * @bank_read_cmd: Bank read cmd 261 * @bank_write_cmd: Bank write cmd 262 * @bank_curr: Current flash bank 263 * @sst_write_second: used by the SST write operation 264 * @flags: flag options for the current SPI-NOR (SNOR_F_*) 265 * @read_proto: the SPI protocol for read operations 266 * @write_proto: the SPI protocol for write operations 267 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations 268 * @cmd_buf: used by the write_reg 269 * @prepare: [OPTIONAL] do some preparations for the 270 * read/write/erase/lock/unlock operations 271 * @unprepare: [OPTIONAL] do some post work after the 272 * read/write/erase/lock/unlock operations 273 * @read_reg: [DRIVER-SPECIFIC] read out the register 274 * @write_reg: [DRIVER-SPECIFIC] write data to the register 275 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR 276 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR 277 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR 278 * at the offset @offs; if not provided by the driver, 279 * spi-nor will send the erase opcode via write_reg() 280 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR 281 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR 282 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is 283 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode 284 * completely locked 285 * @priv: the private data 286 */ 287 struct spi_nor { 288 struct mtd_info mtd; 289 struct udevice *dev; 290 struct spi_slave *spi; 291 const struct flash_info *info; 292 u32 page_size; 293 u8 addr_width; 294 u8 erase_opcode; 295 u8 read_opcode; 296 u8 read_dummy; 297 u8 program_opcode; 298 #ifdef CONFIG_SPI_FLASH_BAR 299 u8 bank_read_cmd; 300 u8 bank_write_cmd; 301 u8 bank_curr; 302 #endif 303 enum spi_nor_protocol read_proto; 304 enum spi_nor_protocol write_proto; 305 enum spi_nor_protocol reg_proto; 306 bool sst_write_second; 307 u32 flags; 308 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; 309 310 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); 311 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); 312 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 313 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 314 315 ssize_t (*read)(struct spi_nor *nor, loff_t from, 316 size_t len, u_char *read_buf); 317 ssize_t (*write)(struct spi_nor *nor, loff_t to, 318 size_t len, const u_char *write_buf); 319 int (*erase)(struct spi_nor *nor, loff_t offs); 320 321 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 322 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 323 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 324 int (*quad_enable)(struct spi_nor *nor); 325 326 void *priv; 327 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */ 328 const char *name; 329 u32 size; 330 u32 sector_size; 331 u32 erase_size; 332 }; 333 334 static inline void spi_nor_set_flash_node(struct spi_nor *nor, 335 const struct device_node *np) 336 { 337 mtd_set_of_node(&nor->mtd, np); 338 } 339 340 static inline const struct 341 device_node *spi_nor_get_flash_node(struct spi_nor *nor) 342 { 343 return mtd_get_of_node(&nor->mtd); 344 } 345 346 /** 347 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies 348 * supported by the SPI controller (bus master). 349 * @mask: the bitmask listing all the supported hw capabilies 350 */ 351 struct spi_nor_hwcaps { 352 u32 mask; 353 }; 354 355 /* 356 *(Fast) Read capabilities. 357 * MUST be ordered by priority: the higher bit position, the higher priority. 358 * As a matter of performances, it is relevant to use Octo SPI protocols first, 359 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly 360 * (Slow) Read. 361 */ 362 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) 363 #define SNOR_HWCAPS_READ BIT(0) 364 #define SNOR_HWCAPS_READ_FAST BIT(1) 365 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) 366 367 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) 368 #define SNOR_HWCAPS_READ_1_1_2 BIT(3) 369 #define SNOR_HWCAPS_READ_1_2_2 BIT(4) 370 #define SNOR_HWCAPS_READ_2_2_2 BIT(5) 371 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) 372 373 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) 374 #define SNOR_HWCAPS_READ_1_1_4 BIT(7) 375 #define SNOR_HWCAPS_READ_1_4_4 BIT(8) 376 #define SNOR_HWCAPS_READ_4_4_4 BIT(9) 377 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) 378 379 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11) 380 #define SNOR_HWCAPS_READ_1_1_8 BIT(11) 381 #define SNOR_HWCAPS_READ_1_8_8 BIT(12) 382 #define SNOR_HWCAPS_READ_8_8_8 BIT(13) 383 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) 384 385 /* 386 * Page Program capabilities. 387 * MUST be ordered by priority: the higher bit position, the higher priority. 388 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the 389 * legacy SPI 1-1-1 protocol. 390 * Note that Dual Page Programs are not supported because there is no existing 391 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory 392 * implements such commands. 393 */ 394 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) 395 #define SNOR_HWCAPS_PP BIT(16) 396 397 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) 398 #define SNOR_HWCAPS_PP_1_1_4 BIT(17) 399 #define SNOR_HWCAPS_PP_1_4_4 BIT(18) 400 #define SNOR_HWCAPS_PP_4_4_4 BIT(19) 401 402 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20) 403 #define SNOR_HWCAPS_PP_1_1_8 BIT(20) 404 #define SNOR_HWCAPS_PP_1_8_8 BIT(21) 405 #define SNOR_HWCAPS_PP_8_8_8 BIT(22) 406 407 /** 408 * spi_nor_scan() - scan the SPI NOR 409 * @nor: the spi_nor structure 410 * 411 * The drivers can use this function to scan the SPI NOR. 412 * In the scanning, it will try to get all the necessary information to 413 * fill the mtd_info{} and the spi_nor{}. 414 * 415 * Return: 0 for success, others for failure. 416 */ 417 int spi_nor_scan(struct spi_nor *nor); 418 419 #endif 420