1 /* 2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 3 * Steven J. Hill <sjhill@realitydiluted.com> 4 * Thomas Gleixner <tglx@linutronix.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 * Info: 9 * Contains standard defines and IDs for NAND flash devices 10 * 11 * Changelog: 12 * See git changelog. 13 */ 14 #ifndef __LINUX_MTD_RAWNAND_H 15 #define __LINUX_MTD_RAWNAND_H 16 17 #include <config.h> 18 19 #include <linux/compat.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/flashchip.h> 22 #include <linux/mtd/bbm.h> 23 #include <asm/cache.h> 24 25 struct mtd_info; 26 struct nand_flash_dev; 27 struct device_node; 28 29 /* Scan and identify a NAND device */ 30 int nand_scan(struct mtd_info *mtd, int max_chips); 31 /* 32 * Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type. 34 */ 35 int nand_scan_ident(struct mtd_info *mtd, int max_chips, 36 struct nand_flash_dev *table); 37 int nand_scan_tail(struct mtd_info *mtd); 38 39 /* Free resources held by the NAND device */ 40 void nand_release(struct mtd_info *mtd); 41 42 /* Internal helper for board drivers which need to override command function */ 43 void nand_wait_ready(struct mtd_info *mtd); 44 45 /* 46 * This constant declares the max. oobsize / page, which 47 * is supported now. If you add a chip with bigger oobsize/page 48 * adjust this accordingly. 49 */ 50 #define NAND_MAX_OOBSIZE 1664 51 #define NAND_MAX_PAGESIZE 16384 52 53 /* 54 * Constants for hardware specific CLE/ALE/NCE function 55 * 56 * These are bits which can be or'ed to set/clear multiple 57 * bits in one go. 58 */ 59 /* Select the chip by setting nCE to low */ 60 #define NAND_NCE 0x01 61 /* Select the command latch by setting CLE to high */ 62 #define NAND_CLE 0x02 63 /* Select the address latch by setting ALE to high */ 64 #define NAND_ALE 0x04 65 66 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 67 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 68 #define NAND_CTRL_CHANGE 0x80 69 70 /* 71 * Standard NAND flash commands 72 */ 73 #define NAND_CMD_READ0 0 74 #define NAND_CMD_READ1 1 75 #define NAND_CMD_RNDOUT 5 76 #define NAND_CMD_PAGEPROG 0x10 77 #define NAND_CMD_READOOB 0x50 78 #define NAND_CMD_ERASE1 0x60 79 #define NAND_CMD_STATUS 0x70 80 #define NAND_CMD_SEQIN 0x80 81 #define NAND_CMD_RNDIN 0x85 82 #define NAND_CMD_READID 0x90 83 #define NAND_CMD_ERASE2 0xd0 84 #define NAND_CMD_PARAM 0xec 85 #define NAND_CMD_GET_FEATURES 0xee 86 #define NAND_CMD_SET_FEATURES 0xef 87 #define NAND_CMD_RESET 0xff 88 89 #define NAND_CMD_LOCK 0x2a 90 #define NAND_CMD_UNLOCK1 0x23 91 #define NAND_CMD_UNLOCK2 0x24 92 93 /* Extended commands for large page devices */ 94 #define NAND_CMD_READSTART 0x30 95 #define NAND_CMD_RNDOUTSTART 0xE0 96 #define NAND_CMD_CACHEDPROG 0x15 97 98 /* Extended commands for AG-AND device */ 99 /* 100 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 101 * there is no way to distinguish that from NAND_CMD_READ0 102 * until the remaining sequence of commands has been completed 103 * so add a high order bit and mask it off in the command. 104 */ 105 #define NAND_CMD_DEPLETE1 0x100 106 #define NAND_CMD_DEPLETE2 0x38 107 #define NAND_CMD_STATUS_MULTI 0x71 108 #define NAND_CMD_STATUS_ERROR 0x72 109 /* multi-bank error status (banks 0-3) */ 110 #define NAND_CMD_STATUS_ERROR0 0x73 111 #define NAND_CMD_STATUS_ERROR1 0x74 112 #define NAND_CMD_STATUS_ERROR2 0x75 113 #define NAND_CMD_STATUS_ERROR3 0x76 114 #define NAND_CMD_STATUS_RESET 0x7f 115 #define NAND_CMD_STATUS_CLEAR 0xff 116 117 #define NAND_CMD_NONE -1 118 119 /* Status bits */ 120 #define NAND_STATUS_FAIL 0x01 121 #define NAND_STATUS_FAIL_N1 0x02 122 #define NAND_STATUS_TRUE_READY 0x20 123 #define NAND_STATUS_READY 0x40 124 #define NAND_STATUS_WP 0x80 125 126 #define NAND_DATA_IFACE_CHECK_ONLY -1 127 128 /* 129 * Constants for ECC_MODES 130 */ 131 typedef enum { 132 NAND_ECC_NONE, 133 NAND_ECC_SOFT, 134 NAND_ECC_HW, 135 NAND_ECC_HW_SYNDROME, 136 NAND_ECC_HW_OOB_FIRST, 137 NAND_ECC_SOFT_BCH, 138 } nand_ecc_modes_t; 139 140 /* 141 * Constants for Hardware ECC 142 */ 143 /* Reset Hardware ECC for read */ 144 #define NAND_ECC_READ 0 145 /* Reset Hardware ECC for write */ 146 #define NAND_ECC_WRITE 1 147 /* Enable Hardware ECC before syndrome is read back from flash */ 148 #define NAND_ECC_READSYN 2 149 150 /* 151 * Enable generic NAND 'page erased' check. This check is only done when 152 * ecc.correct() returns -EBADMSG. 153 * Set this flag if your implementation does not fix bitflips in erased 154 * pages and you want to rely on the default implementation. 155 */ 156 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 157 #define NAND_ECC_MAXIMIZE BIT(1) 158 /* 159 * If your controller already sends the required NAND commands when 160 * reading or writing a page, then the framework is not supposed to 161 * send READ0 and SEQIN/PAGEPROG respectively. 162 */ 163 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 164 165 /* Bit mask for flags passed to do_nand_read_ecc */ 166 #define NAND_GET_DEVICE 0x80 167 168 169 /* 170 * Option constants for bizarre disfunctionality and real 171 * features. 172 */ 173 /* Buswidth is 16 bit */ 174 #define NAND_BUSWIDTH_16 0x00000002 175 /* Device supports partial programming without padding */ 176 #define NAND_NO_PADDING 0x00000004 177 /* Chip has cache program function */ 178 #define NAND_CACHEPRG 0x00000008 179 /* Chip has copy back function */ 180 #define NAND_COPYBACK 0x00000010 181 /* 182 * Chip requires ready check on read (for auto-incremented sequential read). 183 * True only for small page devices; large page devices do not support 184 * autoincrement. 185 */ 186 #define NAND_NEED_READRDY 0x00000100 187 188 /* Chip does not allow subpage writes */ 189 #define NAND_NO_SUBPAGE_WRITE 0x00000200 190 191 /* Device is one of 'new' xD cards that expose fake nand command set */ 192 #define NAND_BROKEN_XD 0x00000400 193 194 /* Device behaves just like nand, but is readonly */ 195 #define NAND_ROM 0x00000800 196 197 /* Device supports subpage reads */ 198 #define NAND_SUBPAGE_READ 0x00001000 199 200 /* 201 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 202 * patterns. 203 */ 204 #define NAND_NEED_SCRAMBLING 0x00002000 205 206 /* Device needs 3rd row address cycle */ 207 #define NAND_ROW_ADDR_3 0x00004000 208 209 /* Options valid for Samsung large page devices */ 210 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 211 212 /* Macros to identify the above */ 213 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 214 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 215 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 216 217 /* Non chip related options */ 218 /* This option skips the bbt scan during initialization. */ 219 #define NAND_SKIP_BBTSCAN 0x00010000 220 /* 221 * This option is defined if the board driver allocates its own buffers 222 * (e.g. because it needs them DMA-coherent). 223 */ 224 #define NAND_OWN_BUFFERS 0x00020000 225 /* Chip may not exist, so silence any errors in scan */ 226 #define NAND_SCAN_SILENT_NODEV 0x00040000 227 /* 228 * Autodetect nand buswidth with readid/onfi. 229 * This suppose the driver will configure the hardware in 8 bits mode 230 * when calling nand_scan_ident, and update its configuration 231 * before calling nand_scan_tail. 232 */ 233 #define NAND_BUSWIDTH_AUTO 0x00080000 234 /* 235 * This option could be defined by controller drivers to protect against 236 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 237 */ 238 #define NAND_USE_BOUNCE_BUFFER 0x00100000 239 240 /* Options set by nand scan */ 241 /* bbt has already been read */ 242 #define NAND_BBT_SCANNED 0x40000000 243 /* Nand scan has allocated controller struct */ 244 #define NAND_CONTROLLER_ALLOC 0x80000000 245 246 /* Cell info constants */ 247 #define NAND_CI_CHIPNR_MSK 0x03 248 #define NAND_CI_CELLTYPE_MSK 0x0C 249 #define NAND_CI_CELLTYPE_SHIFT 2 250 251 /* Keep gcc happy */ 252 struct nand_chip; 253 254 /* ONFI features */ 255 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 256 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 257 258 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 259 #define ONFI_TIMING_MODE_0 (1 << 0) 260 #define ONFI_TIMING_MODE_1 (1 << 1) 261 #define ONFI_TIMING_MODE_2 (1 << 2) 262 #define ONFI_TIMING_MODE_3 (1 << 3) 263 #define ONFI_TIMING_MODE_4 (1 << 4) 264 #define ONFI_TIMING_MODE_5 (1 << 5) 265 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 266 267 /* ONFI feature address */ 268 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 269 270 /* Vendor-specific feature address (Micron) */ 271 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 272 273 /* ONFI subfeature parameters length */ 274 #define ONFI_SUBFEATURE_PARAM_LEN 4 275 276 /* ONFI optional commands SET/GET FEATURES supported? */ 277 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 278 279 struct nand_onfi_params { 280 /* rev info and features block */ 281 /* 'O' 'N' 'F' 'I' */ 282 u8 sig[4]; 283 __le16 revision; 284 __le16 features; 285 __le16 opt_cmd; 286 u8 reserved0[2]; 287 __le16 ext_param_page_length; /* since ONFI 2.1 */ 288 u8 num_of_param_pages; /* since ONFI 2.1 */ 289 u8 reserved1[17]; 290 291 /* manufacturer information block */ 292 char manufacturer[12]; 293 char model[20]; 294 u8 jedec_id; 295 __le16 date_code; 296 u8 reserved2[13]; 297 298 /* memory organization block */ 299 __le32 byte_per_page; 300 __le16 spare_bytes_per_page; 301 __le32 data_bytes_per_ppage; 302 __le16 spare_bytes_per_ppage; 303 __le32 pages_per_block; 304 __le32 blocks_per_lun; 305 u8 lun_count; 306 u8 addr_cycles; 307 u8 bits_per_cell; 308 __le16 bb_per_lun; 309 __le16 block_endurance; 310 u8 guaranteed_good_blocks; 311 __le16 guaranteed_block_endurance; 312 u8 programs_per_page; 313 u8 ppage_attr; 314 u8 ecc_bits; 315 u8 interleaved_bits; 316 u8 interleaved_ops; 317 u8 reserved3[13]; 318 319 /* electrical parameter block */ 320 u8 io_pin_capacitance_max; 321 __le16 async_timing_mode; 322 __le16 program_cache_timing_mode; 323 __le16 t_prog; 324 __le16 t_bers; 325 __le16 t_r; 326 __le16 t_ccs; 327 __le16 src_sync_timing_mode; 328 u8 src_ssync_features; 329 __le16 clk_pin_capacitance_typ; 330 __le16 io_pin_capacitance_typ; 331 __le16 input_pin_capacitance_typ; 332 u8 input_pin_capacitance_max; 333 u8 driver_strength_support; 334 __le16 t_int_r; 335 __le16 t_adl; 336 u8 reserved4[8]; 337 338 /* vendor */ 339 __le16 vendor_revision; 340 u8 vendor[88]; 341 342 __le16 crc; 343 } __packed; 344 345 #define ONFI_CRC_BASE 0x4F4E 346 347 /* Extended ECC information Block Definition (since ONFI 2.1) */ 348 struct onfi_ext_ecc_info { 349 u8 ecc_bits; 350 u8 codeword_size; 351 __le16 bb_per_lun; 352 __le16 block_endurance; 353 u8 reserved[2]; 354 } __packed; 355 356 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 357 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 358 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 359 struct onfi_ext_section { 360 u8 type; 361 u8 length; 362 } __packed; 363 364 #define ONFI_EXT_SECTION_MAX 8 365 366 /* Extended Parameter Page Definition (since ONFI 2.1) */ 367 struct onfi_ext_param_page { 368 __le16 crc; 369 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 370 u8 reserved0[10]; 371 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 372 373 /* 374 * The actual size of the Extended Parameter Page is in 375 * @ext_param_page_length of nand_onfi_params{}. 376 * The following are the variable length sections. 377 * So we do not add any fields below. Please see the ONFI spec. 378 */ 379 } __packed; 380 381 struct nand_onfi_vendor_micron { 382 u8 two_plane_read; 383 u8 read_cache; 384 u8 read_unique_id; 385 u8 dq_imped; 386 u8 dq_imped_num_settings; 387 u8 dq_imped_feat_addr; 388 u8 rb_pulldown_strength; 389 u8 rb_pulldown_strength_feat_addr; 390 u8 rb_pulldown_strength_num_settings; 391 u8 otp_mode; 392 u8 otp_page_start; 393 u8 otp_data_prot_addr; 394 u8 otp_num_pages; 395 u8 otp_feat_addr; 396 u8 read_retry_options; 397 u8 reserved[72]; 398 u8 param_revision; 399 } __packed; 400 401 struct jedec_ecc_info { 402 u8 ecc_bits; 403 u8 codeword_size; 404 __le16 bb_per_lun; 405 __le16 block_endurance; 406 u8 reserved[2]; 407 } __packed; 408 409 /* JEDEC features */ 410 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 411 412 struct nand_jedec_params { 413 /* rev info and features block */ 414 /* 'J' 'E' 'S' 'D' */ 415 u8 sig[4]; 416 __le16 revision; 417 __le16 features; 418 u8 opt_cmd[3]; 419 __le16 sec_cmd; 420 u8 num_of_param_pages; 421 u8 reserved0[18]; 422 423 /* manufacturer information block */ 424 char manufacturer[12]; 425 char model[20]; 426 u8 jedec_id[6]; 427 u8 reserved1[10]; 428 429 /* memory organization block */ 430 __le32 byte_per_page; 431 __le16 spare_bytes_per_page; 432 u8 reserved2[6]; 433 __le32 pages_per_block; 434 __le32 blocks_per_lun; 435 u8 lun_count; 436 u8 addr_cycles; 437 u8 bits_per_cell; 438 u8 programs_per_page; 439 u8 multi_plane_addr; 440 u8 multi_plane_op_attr; 441 u8 reserved3[38]; 442 443 /* electrical parameter block */ 444 __le16 async_sdr_speed_grade; 445 __le16 toggle_ddr_speed_grade; 446 __le16 sync_ddr_speed_grade; 447 u8 async_sdr_features; 448 u8 toggle_ddr_features; 449 u8 sync_ddr_features; 450 __le16 t_prog; 451 __le16 t_bers; 452 __le16 t_r; 453 __le16 t_r_multi_plane; 454 __le16 t_ccs; 455 __le16 io_pin_capacitance_typ; 456 __le16 input_pin_capacitance_typ; 457 __le16 clk_pin_capacitance_typ; 458 u8 driver_strength_support; 459 __le16 t_adl; 460 u8 reserved4[36]; 461 462 /* ECC and endurance block */ 463 u8 guaranteed_good_blocks; 464 __le16 guaranteed_block_endurance; 465 struct jedec_ecc_info ecc_info[4]; 466 u8 reserved5[29]; 467 468 /* reserved */ 469 u8 reserved6[148]; 470 471 /* vendor */ 472 __le16 vendor_rev_num; 473 u8 reserved7[88]; 474 475 /* CRC for Parameter Page */ 476 __le16 crc; 477 } __packed; 478 479 /** 480 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 481 * @lock: protection lock 482 * @active: the mtd device which holds the controller currently 483 * @wq: wait queue to sleep on if a NAND operation is in 484 * progress used instead of the per chip wait queue 485 * when a hw controller is available. 486 */ 487 struct nand_hw_control { 488 spinlock_t lock; 489 struct nand_chip *active; 490 }; 491 492 /** 493 * struct nand_ecc_step_info - ECC step information of ECC engine 494 * @stepsize: data bytes per ECC step 495 * @strengths: array of supported strengths 496 * @nstrengths: number of supported strengths 497 */ 498 struct nand_ecc_step_info { 499 int stepsize; 500 const int *strengths; 501 int nstrengths; 502 }; 503 504 /** 505 * struct nand_ecc_caps - capability of ECC engine 506 * @stepinfos: array of ECC step information 507 * @nstepinfos: number of ECC step information 508 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 509 */ 510 struct nand_ecc_caps { 511 const struct nand_ecc_step_info *stepinfos; 512 int nstepinfos; 513 int (*calc_ecc_bytes)(int step_size, int strength); 514 }; 515 516 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 517 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 518 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 519 static const struct nand_ecc_step_info __name##_stepinfo = { \ 520 .stepsize = __step, \ 521 .strengths = __name##_strengths, \ 522 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 523 }; \ 524 static const struct nand_ecc_caps __name = { \ 525 .stepinfos = &__name##_stepinfo, \ 526 .nstepinfos = 1, \ 527 .calc_ecc_bytes = __calc, \ 528 } 529 530 /** 531 * struct nand_ecc_ctrl - Control structure for ECC 532 * @mode: ECC mode 533 * @steps: number of ECC steps per page 534 * @size: data bytes per ECC step 535 * @bytes: ECC bytes per step 536 * @strength: max number of correctible bits per ECC step 537 * @total: total number of ECC bytes per page 538 * @prepad: padding information for syndrome based ECC generators 539 * @postpad: padding information for syndrome based ECC generators 540 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 541 * @layout: ECC layout control struct pointer 542 * @priv: pointer to private ECC control data 543 * @hwctl: function to control hardware ECC generator. Must only 544 * be provided if an hardware ECC is available 545 * @calculate: function for ECC calculation or readback from ECC hardware 546 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 547 * Should return a positive number representing the number of 548 * corrected bitflips, -EBADMSG if the number of bitflips exceed 549 * ECC strength, or any other error code if the error is not 550 * directly related to correction. 551 * If -EBADMSG is returned the input buffers should be left 552 * untouched. 553 * @read_page_raw: function to read a raw page without ECC. This function 554 * should hide the specific layout used by the ECC 555 * controller and always return contiguous in-band and 556 * out-of-band data even if they're not stored 557 * contiguously on the NAND chip (e.g. 558 * NAND_ECC_HW_SYNDROME interleaves in-band and 559 * out-of-band data). 560 * @write_page_raw: function to write a raw page without ECC. This function 561 * should hide the specific layout used by the ECC 562 * controller and consider the passed data as contiguous 563 * in-band and out-of-band data. ECC controller is 564 * responsible for doing the appropriate transformations 565 * to adapt to its specific layout (e.g. 566 * NAND_ECC_HW_SYNDROME interleaves in-band and 567 * out-of-band data). 568 * @read_page: function to read a page according to the ECC generator 569 * requirements; returns maximum number of bitflips corrected in 570 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 571 * @read_subpage: function to read parts of the page covered by ECC; 572 * returns same as read_page() 573 * @write_subpage: function to write parts of the page covered by ECC. 574 * @write_page: function to write a page according to the ECC generator 575 * requirements. 576 * @write_oob_raw: function to write chip OOB data without ECC 577 * @read_oob_raw: function to read chip OOB data without ECC 578 * @read_oob: function to read chip OOB data 579 * @write_oob: function to write chip OOB data 580 */ 581 struct nand_ecc_ctrl { 582 nand_ecc_modes_t mode; 583 int steps; 584 int size; 585 int bytes; 586 int total; 587 int strength; 588 int prepad; 589 int postpad; 590 unsigned int options; 591 struct nand_ecclayout *layout; 592 void *priv; 593 void (*hwctl)(struct mtd_info *mtd, int mode); 594 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 595 uint8_t *ecc_code); 596 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 597 uint8_t *calc_ecc); 598 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 599 uint8_t *buf, int oob_required, int page); 600 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 601 const uint8_t *buf, int oob_required, int page); 602 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 603 uint8_t *buf, int oob_required, int page); 604 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 605 uint32_t offs, uint32_t len, uint8_t *buf, int page); 606 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 607 uint32_t offset, uint32_t data_len, 608 const uint8_t *data_buf, int oob_required, int page); 609 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 610 const uint8_t *buf, int oob_required, int page); 611 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 612 int page); 613 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 614 int page); 615 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 616 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 617 int page); 618 }; 619 620 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 621 { 622 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 623 } 624 625 /** 626 * struct nand_buffers - buffer structure for read/write 627 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 628 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 629 * @databuf: buffer pointer for data, size is (page size + oobsize). 630 * 631 * Do not change the order of buffers. databuf and oobrbuf must be in 632 * consecutive order. 633 */ 634 struct nand_buffers { 635 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 636 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 637 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 638 ARCH_DMA_MINALIGN)]; 639 }; 640 641 /** 642 * struct nand_sdr_timings - SDR NAND chip timings 643 * 644 * This struct defines the timing requirements of a SDR NAND chip. 645 * These information can be found in every NAND datasheets and the timings 646 * meaning are described in the ONFI specifications: 647 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 648 * Parameters) 649 * 650 * All these timings are expressed in picoseconds. 651 * 652 * @tBERS_max: Block erase time 653 * @tCCS_min: Change column setup time 654 * @tPROG_max: Page program time 655 * @tR_max: Page read time 656 * @tALH_min: ALE hold time 657 * @tADL_min: ALE to data loading time 658 * @tALS_min: ALE setup time 659 * @tAR_min: ALE to RE# delay 660 * @tCEA_max: CE# access time 661 * @tCEH_min: CE# high hold time 662 * @tCH_min: CE# hold time 663 * @tCHZ_max: CE# high to output hi-Z 664 * @tCLH_min: CLE hold time 665 * @tCLR_min: CLE to RE# delay 666 * @tCLS_min: CLE setup time 667 * @tCOH_min: CE# high to output hold 668 * @tCS_min: CE# setup time 669 * @tDH_min: Data hold time 670 * @tDS_min: Data setup time 671 * @tFEAT_max: Busy time for Set Features and Get Features 672 * @tIR_min: Output hi-Z to RE# low 673 * @tITC_max: Interface and Timing Mode Change time 674 * @tRC_min: RE# cycle time 675 * @tREA_max: RE# access time 676 * @tREH_min: RE# high hold time 677 * @tRHOH_min: RE# high to output hold 678 * @tRHW_min: RE# high to WE# low 679 * @tRHZ_max: RE# high to output hi-Z 680 * @tRLOH_min: RE# low to output hold 681 * @tRP_min: RE# pulse width 682 * @tRR_min: Ready to RE# low (data only) 683 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 684 * rising edge of R/B#. 685 * @tWB_max: WE# high to SR[6] low 686 * @tWC_min: WE# cycle time 687 * @tWH_min: WE# high hold time 688 * @tWHR_min: WE# high to RE# low 689 * @tWP_min: WE# pulse width 690 * @tWW_min: WP# transition to WE# low 691 */ 692 struct nand_sdr_timings { 693 u64 tBERS_max; 694 u32 tCCS_min; 695 u64 tPROG_max; 696 u64 tR_max; 697 u32 tALH_min; 698 u32 tADL_min; 699 u32 tALS_min; 700 u32 tAR_min; 701 u32 tCEA_max; 702 u32 tCEH_min; 703 u32 tCH_min; 704 u32 tCHZ_max; 705 u32 tCLH_min; 706 u32 tCLR_min; 707 u32 tCLS_min; 708 u32 tCOH_min; 709 u32 tCS_min; 710 u32 tDH_min; 711 u32 tDS_min; 712 u32 tFEAT_max; 713 u32 tIR_min; 714 u32 tITC_max; 715 u32 tRC_min; 716 u32 tREA_max; 717 u32 tREH_min; 718 u32 tRHOH_min; 719 u32 tRHW_min; 720 u32 tRHZ_max; 721 u32 tRLOH_min; 722 u32 tRP_min; 723 u32 tRR_min; 724 u64 tRST_max; 725 u32 tWB_max; 726 u32 tWC_min; 727 u32 tWH_min; 728 u32 tWHR_min; 729 u32 tWP_min; 730 u32 tWW_min; 731 }; 732 733 /** 734 * enum nand_data_interface_type - NAND interface timing type 735 * @NAND_SDR_IFACE: Single Data Rate interface 736 */ 737 enum nand_data_interface_type { 738 NAND_SDR_IFACE, 739 }; 740 741 /** 742 * struct nand_data_interface - NAND interface timing 743 * @type: type of the timing 744 * @timings: The timing, type according to @type 745 */ 746 struct nand_data_interface { 747 enum nand_data_interface_type type; 748 union { 749 struct nand_sdr_timings sdr; 750 } timings; 751 }; 752 753 /** 754 * nand_get_sdr_timings - get SDR timing from data interface 755 * @conf: The data interface 756 */ 757 static inline const struct nand_sdr_timings * 758 nand_get_sdr_timings(const struct nand_data_interface *conf) 759 { 760 if (conf->type != NAND_SDR_IFACE) 761 return ERR_PTR(-EINVAL); 762 763 return &conf->timings.sdr; 764 } 765 766 /** 767 * struct nand_chip - NAND Private Flash Chip Data 768 * @mtd: MTD device registered to the MTD framework 769 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 770 * flash device 771 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 772 * flash device. 773 * @flash_node: [BOARDSPECIFIC] device node describing this instance 774 * @read_byte: [REPLACEABLE] read one byte from the chip 775 * @read_word: [REPLACEABLE] read one word from the chip 776 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 777 * low 8 I/O lines 778 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 779 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 780 * @select_chip: [REPLACEABLE] select chip nr 781 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 782 * @block_markbad: [REPLACEABLE] mark a block bad 783 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 784 * ALE/CLE/nCE. Also used to write command and address 785 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 786 * device ready/busy line. If set to NULL no access to 787 * ready/busy is available and the ready/busy information 788 * is read from the chip status register. 789 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 790 * commands to the chip. 791 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 792 * ready. 793 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 794 * setting the read-retry mode. Mostly needed for MLC NAND. 795 * @ecc: [BOARDSPECIFIC] ECC control structure 796 * @buffers: buffer structure for read/write 797 * @buf_align: minimum buffer alignment required by a platform 798 * @hwcontrol: platform-specific hardware control structure 799 * @erase: [REPLACEABLE] erase function 800 * @scan_bbt: [REPLACEABLE] function to scan bad block table 801 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 802 * data from array to read regs (tR). 803 * @state: [INTERN] the current state of the NAND device 804 * @oob_poi: "poison value buffer," used for laying out OOB data 805 * before writing 806 * @page_shift: [INTERN] number of address bits in a page (column 807 * address bits). 808 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 809 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 810 * @chip_shift: [INTERN] number of address bits in one chip 811 * @options: [BOARDSPECIFIC] various chip options. They can partly 812 * be set to inform nand_scan about special functionality. 813 * See the defines for further explanation. 814 * @bbt_options: [INTERN] bad block specific options. All options used 815 * here must come from bbm.h. By default, these options 816 * will be copied to the appropriate nand_bbt_descr's. 817 * @badblockpos: [INTERN] position of the bad block marker in the oob 818 * area. 819 * @badblockbits: [INTERN] minimum number of set bits in a good block's 820 * bad block marker position; i.e., BBM == 11110111b is 821 * not bad when badblockbits == 7 822 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 823 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 824 * Minimum amount of bit errors per @ecc_step_ds guaranteed 825 * to be correctable. If unknown, set to zero. 826 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 827 * also from the datasheet. It is the recommended ECC step 828 * size, if known; if unknown, set to zero. 829 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 830 * set to the actually used ONFI mode if the chip is 831 * ONFI compliant or deduced from the datasheet if 832 * the NAND chip is not ONFI compliant. 833 * @numchips: [INTERN] number of physical chips 834 * @chipsize: [INTERN] the size of one chip for multichip arrays 835 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 836 * @pagebuf: [INTERN] holds the pagenumber which is currently in 837 * data_buf. 838 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 839 * currently in data_buf. 840 * @subpagesize: [INTERN] holds the subpagesize 841 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 842 * non 0 if ONFI supported. 843 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 844 * non 0 if JEDEC supported. 845 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 846 * supported, 0 otherwise. 847 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 848 * supported, 0 otherwise. 849 * @read_retries: [INTERN] the number of read retry modes supported 850 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 851 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 852 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 853 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 854 * means the configuration should not be applied but 855 * only checked. 856 * @bbt: [INTERN] bad block table pointer 857 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 858 * lookup. 859 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 860 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 861 * bad block scan. 862 * @controller: [REPLACEABLE] a pointer to a hardware controller 863 * structure which is shared among multiple independent 864 * devices. 865 * @priv: [OPTIONAL] pointer to private chip data 866 * @write_page: [REPLACEABLE] High-level page write function 867 */ 868 869 struct nand_chip { 870 struct mtd_info mtd; 871 void __iomem *IO_ADDR_R; 872 void __iomem *IO_ADDR_W; 873 874 int flash_node; 875 876 uint8_t (*read_byte)(struct mtd_info *mtd); 877 u16 (*read_word)(struct mtd_info *mtd); 878 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 879 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 880 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 881 void (*select_chip)(struct mtd_info *mtd, int chip); 882 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 883 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 884 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 885 int (*dev_ready)(struct mtd_info *mtd); 886 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 887 int page_addr); 888 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 889 int (*erase)(struct mtd_info *mtd, int page); 890 int (*scan_bbt)(struct mtd_info *mtd); 891 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 892 uint32_t offset, int data_len, const uint8_t *buf, 893 int oob_required, int page, int raw); 894 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 895 int feature_addr, uint8_t *subfeature_para); 896 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 897 int feature_addr, uint8_t *subfeature_para); 898 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 899 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 900 const struct nand_data_interface *conf); 901 902 903 int chip_delay; 904 unsigned int options; 905 unsigned int bbt_options; 906 907 int page_shift; 908 int phys_erase_shift; 909 int bbt_erase_shift; 910 int chip_shift; 911 int numchips; 912 uint64_t chipsize; 913 int pagemask; 914 int pagebuf; 915 unsigned int pagebuf_bitflips; 916 int subpagesize; 917 uint8_t bits_per_cell; 918 uint16_t ecc_strength_ds; 919 uint16_t ecc_step_ds; 920 int onfi_timing_mode_default; 921 int badblockpos; 922 int badblockbits; 923 924 int onfi_version; 925 int jedec_version; 926 struct nand_onfi_params onfi_params; 927 struct nand_jedec_params jedec_params; 928 929 struct nand_data_interface *data_interface; 930 931 int read_retries; 932 933 flstate_t state; 934 935 uint8_t *oob_poi; 936 struct nand_hw_control *controller; 937 struct nand_ecclayout *ecclayout; 938 939 struct nand_ecc_ctrl ecc; 940 struct nand_buffers *buffers; 941 unsigned long buf_align; 942 struct nand_hw_control hwcontrol; 943 944 uint8_t *bbt; 945 struct nand_bbt_descr *bbt_td; 946 struct nand_bbt_descr *bbt_md; 947 948 struct nand_bbt_descr *badblock_pattern; 949 950 void *priv; 951 }; 952 953 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 954 { 955 return container_of(mtd, struct nand_chip, mtd); 956 } 957 958 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 959 { 960 return &chip->mtd; 961 } 962 963 static inline void *nand_get_controller_data(struct nand_chip *chip) 964 { 965 return chip->priv; 966 } 967 968 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 969 { 970 chip->priv = priv; 971 } 972 973 /* 974 * NAND Flash Manufacturer ID Codes 975 */ 976 #define NAND_MFR_TOSHIBA 0x98 977 #define NAND_MFR_SAMSUNG 0xec 978 #define NAND_MFR_FUJITSU 0x04 979 #define NAND_MFR_NATIONAL 0x8f 980 #define NAND_MFR_RENESAS 0x07 981 #define NAND_MFR_STMICRO 0x20 982 #define NAND_MFR_HYNIX 0xad 983 #define NAND_MFR_MICRON 0x2c 984 #define NAND_MFR_AMD 0x01 985 #define NAND_MFR_MACRONIX 0xc2 986 #define NAND_MFR_EON 0x92 987 #define NAND_MFR_SANDISK 0x45 988 #define NAND_MFR_INTEL 0x89 989 #define NAND_MFR_ATO 0x9b 990 991 /* The maximum expected count of bytes in the NAND ID sequence */ 992 #define NAND_MAX_ID_LEN 8 993 994 /* 995 * A helper for defining older NAND chips where the second ID byte fully 996 * defined the chip, including the geometry (chip size, eraseblock size, page 997 * size). All these chips have 512 bytes NAND page size. 998 */ 999 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1000 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1001 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1002 1003 /* 1004 * A helper for defining newer chips which report their page size and 1005 * eraseblock size via the extended ID bytes. 1006 * 1007 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1008 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1009 * device ID now only represented a particular total chip size (and voltage, 1010 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1011 * using the same device ID. 1012 */ 1013 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1014 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1015 .options = (opts) } 1016 1017 #define NAND_ECC_INFO(_strength, _step) \ 1018 { .strength_ds = (_strength), .step_ds = (_step) } 1019 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1020 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1021 1022 /** 1023 * struct nand_flash_dev - NAND Flash Device ID Structure 1024 * @name: a human-readable name of the NAND chip 1025 * @dev_id: the device ID (the second byte of the full chip ID array) 1026 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1027 * memory address as @id[0]) 1028 * @dev_id: device ID part of the full chip ID array (refers the same memory 1029 * address as @id[1]) 1030 * @id: full device ID array 1031 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1032 * well as the eraseblock size) is determined from the extended NAND 1033 * chip ID array) 1034 * @chipsize: total chip size in MiB 1035 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1036 * @options: stores various chip bit options 1037 * @id_len: The valid length of the @id. 1038 * @oobsize: OOB size 1039 * @ecc: ECC correctability and step information from the datasheet. 1040 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1041 * @ecc_strength_ds in nand_chip{}. 1042 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1043 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1044 * For example, the "4bit ECC for each 512Byte" can be set with 1045 * NAND_ECC_INFO(4, 512). 1046 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1047 * reset. Should be deduced from timings described 1048 * in the datasheet. 1049 * 1050 */ 1051 struct nand_flash_dev { 1052 char *name; 1053 union { 1054 struct { 1055 uint8_t mfr_id; 1056 uint8_t dev_id; 1057 }; 1058 uint8_t id[NAND_MAX_ID_LEN]; 1059 }; 1060 unsigned int pagesize; 1061 unsigned int chipsize; 1062 unsigned int erasesize; 1063 unsigned int options; 1064 uint16_t id_len; 1065 uint16_t oobsize; 1066 struct { 1067 uint16_t strength_ds; 1068 uint16_t step_ds; 1069 } ecc; 1070 int onfi_timing_mode_default; 1071 }; 1072 1073 /** 1074 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 1075 * @name: Manufacturer name 1076 * @id: manufacturer ID code of device. 1077 */ 1078 struct nand_manufacturers { 1079 int id; 1080 char *name; 1081 }; 1082 1083 extern struct nand_flash_dev nand_flash_ids[]; 1084 extern struct nand_manufacturers nand_manuf_ids[]; 1085 1086 int nand_default_bbt(struct mtd_info *mtd); 1087 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1088 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1089 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1090 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1091 int allowbbt); 1092 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1093 size_t *retlen, uint8_t *buf); 1094 1095 /* 1096 * Constants for oob configuration 1097 */ 1098 #define NAND_SMALL_BADBLOCK_POS 5 1099 #define NAND_LARGE_BADBLOCK_POS 0 1100 1101 /** 1102 * struct platform_nand_chip - chip level device structure 1103 * @nr_chips: max. number of chips to scan for 1104 * @chip_offset: chip number offset 1105 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1106 * @partitions: mtd partition list 1107 * @chip_delay: R/B delay value in us 1108 * @options: Option flags, e.g. 16bit buswidth 1109 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1110 * @part_probe_types: NULL-terminated array of probe types 1111 */ 1112 struct platform_nand_chip { 1113 int nr_chips; 1114 int chip_offset; 1115 int nr_partitions; 1116 struct mtd_partition *partitions; 1117 int chip_delay; 1118 unsigned int options; 1119 unsigned int bbt_options; 1120 const char **part_probe_types; 1121 }; 1122 1123 /* Keep gcc happy */ 1124 struct platform_device; 1125 1126 /** 1127 * struct platform_nand_ctrl - controller level device structure 1128 * @probe: platform specific function to probe/setup hardware 1129 * @remove: platform specific function to remove/teardown hardware 1130 * @hwcontrol: platform specific hardware control structure 1131 * @dev_ready: platform specific function to read ready/busy pin 1132 * @select_chip: platform specific chip select function 1133 * @cmd_ctrl: platform specific function for controlling 1134 * ALE/CLE/nCE. Also used to write command and address 1135 * @write_buf: platform specific function for write buffer 1136 * @read_buf: platform specific function for read buffer 1137 * @read_byte: platform specific function to read one byte from chip 1138 * @priv: private data to transport driver specific settings 1139 * 1140 * All fields are optional and depend on the hardware driver requirements 1141 */ 1142 struct platform_nand_ctrl { 1143 int (*probe)(struct platform_device *pdev); 1144 void (*remove)(struct platform_device *pdev); 1145 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1146 int (*dev_ready)(struct mtd_info *mtd); 1147 void (*select_chip)(struct mtd_info *mtd, int chip); 1148 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1149 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1150 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1151 unsigned char (*read_byte)(struct mtd_info *mtd); 1152 void *priv; 1153 }; 1154 1155 /** 1156 * struct platform_nand_data - container structure for platform-specific data 1157 * @chip: chip level chip structure 1158 * @ctrl: controller level device structure 1159 */ 1160 struct platform_nand_data { 1161 struct platform_nand_chip chip; 1162 struct platform_nand_ctrl ctrl; 1163 }; 1164 1165 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 1166 /* return the supported features. */ 1167 static inline int onfi_feature(struct nand_chip *chip) 1168 { 1169 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1170 } 1171 1172 /* return the supported asynchronous timing mode. */ 1173 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1174 { 1175 if (!chip->onfi_version) 1176 return ONFI_TIMING_MODE_UNKNOWN; 1177 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1178 } 1179 1180 /* return the supported synchronous timing mode. */ 1181 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1182 { 1183 if (!chip->onfi_version) 1184 return ONFI_TIMING_MODE_UNKNOWN; 1185 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1186 } 1187 #else 1188 static inline int onfi_feature(struct nand_chip *chip) 1189 { 1190 return 0; 1191 } 1192 1193 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1194 { 1195 return ONFI_TIMING_MODE_UNKNOWN; 1196 } 1197 1198 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1199 { 1200 return ONFI_TIMING_MODE_UNKNOWN; 1201 } 1202 #endif 1203 1204 int onfi_init_data_interface(struct nand_chip *chip, 1205 struct nand_data_interface *iface, 1206 enum nand_data_interface_type type, 1207 int timing_mode); 1208 1209 /* 1210 * Check if it is a SLC nand. 1211 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1212 * We do not distinguish the MLC and TLC now. 1213 */ 1214 static inline bool nand_is_slc(struct nand_chip *chip) 1215 { 1216 return chip->bits_per_cell == 1; 1217 } 1218 1219 /** 1220 * Check if the opcode's address should be sent only on the lower 8 bits 1221 * @command: opcode to check 1222 */ 1223 static inline int nand_opcode_8bits(unsigned int command) 1224 { 1225 switch (command) { 1226 case NAND_CMD_READID: 1227 case NAND_CMD_PARAM: 1228 case NAND_CMD_GET_FEATURES: 1229 case NAND_CMD_SET_FEATURES: 1230 return 1; 1231 default: 1232 break; 1233 } 1234 return 0; 1235 } 1236 1237 /* return the supported JEDEC features. */ 1238 static inline int jedec_feature(struct nand_chip *chip) 1239 { 1240 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1241 : 0; 1242 } 1243 1244 /* Standard NAND functions from nand_base.c */ 1245 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1246 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1247 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1248 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1249 uint8_t nand_read_byte(struct mtd_info *mtd); 1250 1251 /* get timing characteristics from ONFI timing mode. */ 1252 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1253 /* get data interface from ONFI timing mode 0, used after reset. */ 1254 const struct nand_data_interface *nand_get_default_data_interface(void); 1255 1256 int nand_check_erased_ecc_chunk(void *data, int datalen, 1257 void *ecc, int ecclen, 1258 void *extraoob, int extraooblen, 1259 int threshold); 1260 1261 int nand_check_ecc_caps(struct nand_chip *chip, 1262 const struct nand_ecc_caps *caps, int oobavail); 1263 1264 int nand_match_ecc_req(struct nand_chip *chip, 1265 const struct nand_ecc_caps *caps, int oobavail); 1266 1267 int nand_maximize_ecc(struct nand_chip *chip, 1268 const struct nand_ecc_caps *caps, int oobavail); 1269 1270 /* Reset and initialize a NAND device */ 1271 int nand_reset(struct nand_chip *chip, int chipnr); 1272 #endif /* __LINUX_MTD_RAWNAND_H */ 1273