1 /* 2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 3 * Steven J. Hill <sjhill@realitydiluted.com> 4 * Thomas Gleixner <tglx@linutronix.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 * Info: 9 * Contains standard defines and IDs for NAND flash devices 10 * 11 * Changelog: 12 * See git changelog. 13 */ 14 #ifndef __LINUX_MTD_RAWNAND_H 15 #define __LINUX_MTD_RAWNAND_H 16 17 #include <config.h> 18 19 #include <linux/compat.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/flashchip.h> 22 #include <linux/mtd/bbm.h> 23 24 struct mtd_info; 25 struct nand_flash_dev; 26 struct device_node; 27 28 /* Scan and identify a NAND device */ 29 int nand_scan(struct mtd_info *mtd, int max_chips); 30 /* 31 * Separate phases of nand_scan(), allowing board driver to intervene 32 * and override command or ECC setup according to flash type. 33 */ 34 int nand_scan_ident(struct mtd_info *mtd, int max_chips, 35 struct nand_flash_dev *table); 36 int nand_scan_tail(struct mtd_info *mtd); 37 38 /* Free resources held by the NAND device */ 39 void nand_release(struct mtd_info *mtd); 40 41 /* Internal helper for board drivers which need to override command function */ 42 void nand_wait_ready(struct mtd_info *mtd); 43 44 /* 45 * This constant declares the max. oobsize / page, which 46 * is supported now. If you add a chip with bigger oobsize/page 47 * adjust this accordingly. 48 */ 49 #define NAND_MAX_OOBSIZE 1664 50 #define NAND_MAX_PAGESIZE 16384 51 52 /* 53 * Constants for hardware specific CLE/ALE/NCE function 54 * 55 * These are bits which can be or'ed to set/clear multiple 56 * bits in one go. 57 */ 58 /* Select the chip by setting nCE to low */ 59 #define NAND_NCE 0x01 60 /* Select the command latch by setting CLE to high */ 61 #define NAND_CLE 0x02 62 /* Select the address latch by setting ALE to high */ 63 #define NAND_ALE 0x04 64 65 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 66 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 67 #define NAND_CTRL_CHANGE 0x80 68 69 /* 70 * Standard NAND flash commands 71 */ 72 #define NAND_CMD_READ0 0 73 #define NAND_CMD_READ1 1 74 #define NAND_CMD_RNDOUT 5 75 #define NAND_CMD_PAGEPROG 0x10 76 #define NAND_CMD_READOOB 0x50 77 #define NAND_CMD_ERASE1 0x60 78 #define NAND_CMD_STATUS 0x70 79 #define NAND_CMD_SEQIN 0x80 80 #define NAND_CMD_RNDIN 0x85 81 #define NAND_CMD_READID 0x90 82 #define NAND_CMD_ERASE2 0xd0 83 #define NAND_CMD_PARAM 0xec 84 #define NAND_CMD_GET_FEATURES 0xee 85 #define NAND_CMD_SET_FEATURES 0xef 86 #define NAND_CMD_RESET 0xff 87 88 #define NAND_CMD_LOCK 0x2a 89 #define NAND_CMD_UNLOCK1 0x23 90 #define NAND_CMD_UNLOCK2 0x24 91 92 /* Extended commands for large page devices */ 93 #define NAND_CMD_READSTART 0x30 94 #define NAND_CMD_RNDOUTSTART 0xE0 95 #define NAND_CMD_CACHEDPROG 0x15 96 97 /* Extended commands for AG-AND device */ 98 /* 99 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 100 * there is no way to distinguish that from NAND_CMD_READ0 101 * until the remaining sequence of commands has been completed 102 * so add a high order bit and mask it off in the command. 103 */ 104 #define NAND_CMD_DEPLETE1 0x100 105 #define NAND_CMD_DEPLETE2 0x38 106 #define NAND_CMD_STATUS_MULTI 0x71 107 #define NAND_CMD_STATUS_ERROR 0x72 108 /* multi-bank error status (banks 0-3) */ 109 #define NAND_CMD_STATUS_ERROR0 0x73 110 #define NAND_CMD_STATUS_ERROR1 0x74 111 #define NAND_CMD_STATUS_ERROR2 0x75 112 #define NAND_CMD_STATUS_ERROR3 0x76 113 #define NAND_CMD_STATUS_RESET 0x7f 114 #define NAND_CMD_STATUS_CLEAR 0xff 115 116 #define NAND_CMD_NONE -1 117 118 /* Status bits */ 119 #define NAND_STATUS_FAIL 0x01 120 #define NAND_STATUS_FAIL_N1 0x02 121 #define NAND_STATUS_TRUE_READY 0x20 122 #define NAND_STATUS_READY 0x40 123 #define NAND_STATUS_WP 0x80 124 125 #define NAND_DATA_IFACE_CHECK_ONLY -1 126 127 /* 128 * Constants for ECC_MODES 129 */ 130 typedef enum { 131 NAND_ECC_NONE, 132 NAND_ECC_SOFT, 133 NAND_ECC_HW, 134 NAND_ECC_HW_SYNDROME, 135 NAND_ECC_HW_OOB_FIRST, 136 NAND_ECC_SOFT_BCH, 137 } nand_ecc_modes_t; 138 139 /* 140 * Constants for Hardware ECC 141 */ 142 /* Reset Hardware ECC for read */ 143 #define NAND_ECC_READ 0 144 /* Reset Hardware ECC for write */ 145 #define NAND_ECC_WRITE 1 146 /* Enable Hardware ECC before syndrome is read back from flash */ 147 #define NAND_ECC_READSYN 2 148 149 /* 150 * Enable generic NAND 'page erased' check. This check is only done when 151 * ecc.correct() returns -EBADMSG. 152 * Set this flag if your implementation does not fix bitflips in erased 153 * pages and you want to rely on the default implementation. 154 */ 155 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 156 #define NAND_ECC_MAXIMIZE BIT(1) 157 /* 158 * If your controller already sends the required NAND commands when 159 * reading or writing a page, then the framework is not supposed to 160 * send READ0 and SEQIN/PAGEPROG respectively. 161 */ 162 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 163 164 /* Bit mask for flags passed to do_nand_read_ecc */ 165 #define NAND_GET_DEVICE 0x80 166 167 168 /* 169 * Option constants for bizarre disfunctionality and real 170 * features. 171 */ 172 /* Buswidth is 16 bit */ 173 #define NAND_BUSWIDTH_16 0x00000002 174 /* Device supports partial programming without padding */ 175 #define NAND_NO_PADDING 0x00000004 176 /* Chip has cache program function */ 177 #define NAND_CACHEPRG 0x00000008 178 /* Chip has copy back function */ 179 #define NAND_COPYBACK 0x00000010 180 /* 181 * Chip requires ready check on read (for auto-incremented sequential read). 182 * True only for small page devices; large page devices do not support 183 * autoincrement. 184 */ 185 #define NAND_NEED_READRDY 0x00000100 186 187 /* Chip does not allow subpage writes */ 188 #define NAND_NO_SUBPAGE_WRITE 0x00000200 189 190 /* Device is one of 'new' xD cards that expose fake nand command set */ 191 #define NAND_BROKEN_XD 0x00000400 192 193 /* Device behaves just like nand, but is readonly */ 194 #define NAND_ROM 0x00000800 195 196 /* Device supports subpage reads */ 197 #define NAND_SUBPAGE_READ 0x00001000 198 199 /* 200 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 201 * patterns. 202 */ 203 #define NAND_NEED_SCRAMBLING 0x00002000 204 205 /* Device needs 3rd row address cycle */ 206 #define NAND_ROW_ADDR_3 0x00004000 207 208 /* Options valid for Samsung large page devices */ 209 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 210 211 /* Macros to identify the above */ 212 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 213 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 214 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 215 216 /* Non chip related options */ 217 /* This option skips the bbt scan during initialization. */ 218 #define NAND_SKIP_BBTSCAN 0x00010000 219 /* 220 * This option is defined if the board driver allocates its own buffers 221 * (e.g. because it needs them DMA-coherent). 222 */ 223 #define NAND_OWN_BUFFERS 0x00020000 224 /* Chip may not exist, so silence any errors in scan */ 225 #define NAND_SCAN_SILENT_NODEV 0x00040000 226 /* 227 * Autodetect nand buswidth with readid/onfi. 228 * This suppose the driver will configure the hardware in 8 bits mode 229 * when calling nand_scan_ident, and update its configuration 230 * before calling nand_scan_tail. 231 */ 232 #define NAND_BUSWIDTH_AUTO 0x00080000 233 /* 234 * This option could be defined by controller drivers to protect against 235 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 236 */ 237 #define NAND_USE_BOUNCE_BUFFER 0x00100000 238 239 /* Options set by nand scan */ 240 /* bbt has already been read */ 241 #define NAND_BBT_SCANNED 0x40000000 242 /* Nand scan has allocated controller struct */ 243 #define NAND_CONTROLLER_ALLOC 0x80000000 244 245 /* Cell info constants */ 246 #define NAND_CI_CHIPNR_MSK 0x03 247 #define NAND_CI_CELLTYPE_MSK 0x0C 248 #define NAND_CI_CELLTYPE_SHIFT 2 249 250 /* Keep gcc happy */ 251 struct nand_chip; 252 253 /* ONFI features */ 254 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 255 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 256 257 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 258 #define ONFI_TIMING_MODE_0 (1 << 0) 259 #define ONFI_TIMING_MODE_1 (1 << 1) 260 #define ONFI_TIMING_MODE_2 (1 << 2) 261 #define ONFI_TIMING_MODE_3 (1 << 3) 262 #define ONFI_TIMING_MODE_4 (1 << 4) 263 #define ONFI_TIMING_MODE_5 (1 << 5) 264 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 265 266 /* ONFI feature address */ 267 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 268 269 /* Vendor-specific feature address (Micron) */ 270 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 271 272 /* ONFI subfeature parameters length */ 273 #define ONFI_SUBFEATURE_PARAM_LEN 4 274 275 /* ONFI optional commands SET/GET FEATURES supported? */ 276 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 277 278 struct nand_onfi_params { 279 /* rev info and features block */ 280 /* 'O' 'N' 'F' 'I' */ 281 u8 sig[4]; 282 __le16 revision; 283 __le16 features; 284 __le16 opt_cmd; 285 u8 reserved0[2]; 286 __le16 ext_param_page_length; /* since ONFI 2.1 */ 287 u8 num_of_param_pages; /* since ONFI 2.1 */ 288 u8 reserved1[17]; 289 290 /* manufacturer information block */ 291 char manufacturer[12]; 292 char model[20]; 293 u8 jedec_id; 294 __le16 date_code; 295 u8 reserved2[13]; 296 297 /* memory organization block */ 298 __le32 byte_per_page; 299 __le16 spare_bytes_per_page; 300 __le32 data_bytes_per_ppage; 301 __le16 spare_bytes_per_ppage; 302 __le32 pages_per_block; 303 __le32 blocks_per_lun; 304 u8 lun_count; 305 u8 addr_cycles; 306 u8 bits_per_cell; 307 __le16 bb_per_lun; 308 __le16 block_endurance; 309 u8 guaranteed_good_blocks; 310 __le16 guaranteed_block_endurance; 311 u8 programs_per_page; 312 u8 ppage_attr; 313 u8 ecc_bits; 314 u8 interleaved_bits; 315 u8 interleaved_ops; 316 u8 reserved3[13]; 317 318 /* electrical parameter block */ 319 u8 io_pin_capacitance_max; 320 __le16 async_timing_mode; 321 __le16 program_cache_timing_mode; 322 __le16 t_prog; 323 __le16 t_bers; 324 __le16 t_r; 325 __le16 t_ccs; 326 __le16 src_sync_timing_mode; 327 u8 src_ssync_features; 328 __le16 clk_pin_capacitance_typ; 329 __le16 io_pin_capacitance_typ; 330 __le16 input_pin_capacitance_typ; 331 u8 input_pin_capacitance_max; 332 u8 driver_strength_support; 333 __le16 t_int_r; 334 __le16 t_adl; 335 u8 reserved4[8]; 336 337 /* vendor */ 338 __le16 vendor_revision; 339 u8 vendor[88]; 340 341 __le16 crc; 342 } __packed; 343 344 #define ONFI_CRC_BASE 0x4F4E 345 346 /* Extended ECC information Block Definition (since ONFI 2.1) */ 347 struct onfi_ext_ecc_info { 348 u8 ecc_bits; 349 u8 codeword_size; 350 __le16 bb_per_lun; 351 __le16 block_endurance; 352 u8 reserved[2]; 353 } __packed; 354 355 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 356 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 357 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 358 struct onfi_ext_section { 359 u8 type; 360 u8 length; 361 } __packed; 362 363 #define ONFI_EXT_SECTION_MAX 8 364 365 /* Extended Parameter Page Definition (since ONFI 2.1) */ 366 struct onfi_ext_param_page { 367 __le16 crc; 368 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 369 u8 reserved0[10]; 370 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 371 372 /* 373 * The actual size of the Extended Parameter Page is in 374 * @ext_param_page_length of nand_onfi_params{}. 375 * The following are the variable length sections. 376 * So we do not add any fields below. Please see the ONFI spec. 377 */ 378 } __packed; 379 380 struct nand_onfi_vendor_micron { 381 u8 two_plane_read; 382 u8 read_cache; 383 u8 read_unique_id; 384 u8 dq_imped; 385 u8 dq_imped_num_settings; 386 u8 dq_imped_feat_addr; 387 u8 rb_pulldown_strength; 388 u8 rb_pulldown_strength_feat_addr; 389 u8 rb_pulldown_strength_num_settings; 390 u8 otp_mode; 391 u8 otp_page_start; 392 u8 otp_data_prot_addr; 393 u8 otp_num_pages; 394 u8 otp_feat_addr; 395 u8 read_retry_options; 396 u8 reserved[72]; 397 u8 param_revision; 398 } __packed; 399 400 struct jedec_ecc_info { 401 u8 ecc_bits; 402 u8 codeword_size; 403 __le16 bb_per_lun; 404 __le16 block_endurance; 405 u8 reserved[2]; 406 } __packed; 407 408 /* JEDEC features */ 409 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 410 411 struct nand_jedec_params { 412 /* rev info and features block */ 413 /* 'J' 'E' 'S' 'D' */ 414 u8 sig[4]; 415 __le16 revision; 416 __le16 features; 417 u8 opt_cmd[3]; 418 __le16 sec_cmd; 419 u8 num_of_param_pages; 420 u8 reserved0[18]; 421 422 /* manufacturer information block */ 423 char manufacturer[12]; 424 char model[20]; 425 u8 jedec_id[6]; 426 u8 reserved1[10]; 427 428 /* memory organization block */ 429 __le32 byte_per_page; 430 __le16 spare_bytes_per_page; 431 u8 reserved2[6]; 432 __le32 pages_per_block; 433 __le32 blocks_per_lun; 434 u8 lun_count; 435 u8 addr_cycles; 436 u8 bits_per_cell; 437 u8 programs_per_page; 438 u8 multi_plane_addr; 439 u8 multi_plane_op_attr; 440 u8 reserved3[38]; 441 442 /* electrical parameter block */ 443 __le16 async_sdr_speed_grade; 444 __le16 toggle_ddr_speed_grade; 445 __le16 sync_ddr_speed_grade; 446 u8 async_sdr_features; 447 u8 toggle_ddr_features; 448 u8 sync_ddr_features; 449 __le16 t_prog; 450 __le16 t_bers; 451 __le16 t_r; 452 __le16 t_r_multi_plane; 453 __le16 t_ccs; 454 __le16 io_pin_capacitance_typ; 455 __le16 input_pin_capacitance_typ; 456 __le16 clk_pin_capacitance_typ; 457 u8 driver_strength_support; 458 __le16 t_adl; 459 u8 reserved4[36]; 460 461 /* ECC and endurance block */ 462 u8 guaranteed_good_blocks; 463 __le16 guaranteed_block_endurance; 464 struct jedec_ecc_info ecc_info[4]; 465 u8 reserved5[29]; 466 467 /* reserved */ 468 u8 reserved6[148]; 469 470 /* vendor */ 471 __le16 vendor_rev_num; 472 u8 reserved7[88]; 473 474 /* CRC for Parameter Page */ 475 __le16 crc; 476 } __packed; 477 478 /** 479 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 480 * @lock: protection lock 481 * @active: the mtd device which holds the controller currently 482 * @wq: wait queue to sleep on if a NAND operation is in 483 * progress used instead of the per chip wait queue 484 * when a hw controller is available. 485 */ 486 struct nand_hw_control { 487 spinlock_t lock; 488 struct nand_chip *active; 489 }; 490 491 /** 492 * struct nand_ecc_step_info - ECC step information of ECC engine 493 * @stepsize: data bytes per ECC step 494 * @strengths: array of supported strengths 495 * @nstrengths: number of supported strengths 496 */ 497 struct nand_ecc_step_info { 498 int stepsize; 499 const int *strengths; 500 int nstrengths; 501 }; 502 503 /** 504 * struct nand_ecc_caps - capability of ECC engine 505 * @stepinfos: array of ECC step information 506 * @nstepinfos: number of ECC step information 507 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 508 */ 509 struct nand_ecc_caps { 510 const struct nand_ecc_step_info *stepinfos; 511 int nstepinfos; 512 int (*calc_ecc_bytes)(int step_size, int strength); 513 }; 514 515 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 516 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 517 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 518 static const struct nand_ecc_step_info __name##_stepinfo = { \ 519 .stepsize = __step, \ 520 .strengths = __name##_strengths, \ 521 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 522 }; \ 523 static const struct nand_ecc_caps __name = { \ 524 .stepinfos = &__name##_stepinfo, \ 525 .nstepinfos = 1, \ 526 .calc_ecc_bytes = __calc, \ 527 } 528 529 /** 530 * struct nand_ecc_ctrl - Control structure for ECC 531 * @mode: ECC mode 532 * @steps: number of ECC steps per page 533 * @size: data bytes per ECC step 534 * @bytes: ECC bytes per step 535 * @strength: max number of correctible bits per ECC step 536 * @total: total number of ECC bytes per page 537 * @prepad: padding information for syndrome based ECC generators 538 * @postpad: padding information for syndrome based ECC generators 539 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 540 * @layout: ECC layout control struct pointer 541 * @priv: pointer to private ECC control data 542 * @hwctl: function to control hardware ECC generator. Must only 543 * be provided if an hardware ECC is available 544 * @calculate: function for ECC calculation or readback from ECC hardware 545 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 546 * Should return a positive number representing the number of 547 * corrected bitflips, -EBADMSG if the number of bitflips exceed 548 * ECC strength, or any other error code if the error is not 549 * directly related to correction. 550 * If -EBADMSG is returned the input buffers should be left 551 * untouched. 552 * @read_page_raw: function to read a raw page without ECC. This function 553 * should hide the specific layout used by the ECC 554 * controller and always return contiguous in-band and 555 * out-of-band data even if they're not stored 556 * contiguously on the NAND chip (e.g. 557 * NAND_ECC_HW_SYNDROME interleaves in-band and 558 * out-of-band data). 559 * @write_page_raw: function to write a raw page without ECC. This function 560 * should hide the specific layout used by the ECC 561 * controller and consider the passed data as contiguous 562 * in-band and out-of-band data. ECC controller is 563 * responsible for doing the appropriate transformations 564 * to adapt to its specific layout (e.g. 565 * NAND_ECC_HW_SYNDROME interleaves in-band and 566 * out-of-band data). 567 * @read_page: function to read a page according to the ECC generator 568 * requirements; returns maximum number of bitflips corrected in 569 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 570 * @read_subpage: function to read parts of the page covered by ECC; 571 * returns same as read_page() 572 * @write_subpage: function to write parts of the page covered by ECC. 573 * @write_page: function to write a page according to the ECC generator 574 * requirements. 575 * @write_oob_raw: function to write chip OOB data without ECC 576 * @read_oob_raw: function to read chip OOB data without ECC 577 * @read_oob: function to read chip OOB data 578 * @write_oob: function to write chip OOB data 579 */ 580 struct nand_ecc_ctrl { 581 nand_ecc_modes_t mode; 582 int steps; 583 int size; 584 int bytes; 585 int total; 586 int strength; 587 int prepad; 588 int postpad; 589 unsigned int options; 590 struct nand_ecclayout *layout; 591 void *priv; 592 void (*hwctl)(struct mtd_info *mtd, int mode); 593 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 594 uint8_t *ecc_code); 595 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 596 uint8_t *calc_ecc); 597 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 598 uint8_t *buf, int oob_required, int page); 599 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 600 const uint8_t *buf, int oob_required, int page); 601 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 602 uint8_t *buf, int oob_required, int page); 603 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 604 uint32_t offs, uint32_t len, uint8_t *buf, int page); 605 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 606 uint32_t offset, uint32_t data_len, 607 const uint8_t *data_buf, int oob_required, int page); 608 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 609 const uint8_t *buf, int oob_required, int page); 610 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 611 int page); 612 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 613 int page); 614 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 615 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 616 int page); 617 }; 618 619 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 620 { 621 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 622 } 623 624 /** 625 * struct nand_buffers - buffer structure for read/write 626 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 627 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 628 * @databuf: buffer pointer for data, size is (page size + oobsize). 629 * 630 * Do not change the order of buffers. databuf and oobrbuf must be in 631 * consecutive order. 632 */ 633 struct nand_buffers { 634 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 635 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 636 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 637 ARCH_DMA_MINALIGN)]; 638 }; 639 640 /** 641 * struct nand_sdr_timings - SDR NAND chip timings 642 * 643 * This struct defines the timing requirements of a SDR NAND chip. 644 * These information can be found in every NAND datasheets and the timings 645 * meaning are described in the ONFI specifications: 646 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 647 * Parameters) 648 * 649 * All these timings are expressed in picoseconds. 650 * 651 * @tBERS_max: Block erase time 652 * @tCCS_min: Change column setup time 653 * @tPROG_max: Page program time 654 * @tR_max: Page read time 655 * @tALH_min: ALE hold time 656 * @tADL_min: ALE to data loading time 657 * @tALS_min: ALE setup time 658 * @tAR_min: ALE to RE# delay 659 * @tCEA_max: CE# access time 660 * @tCEH_min: CE# high hold time 661 * @tCH_min: CE# hold time 662 * @tCHZ_max: CE# high to output hi-Z 663 * @tCLH_min: CLE hold time 664 * @tCLR_min: CLE to RE# delay 665 * @tCLS_min: CLE setup time 666 * @tCOH_min: CE# high to output hold 667 * @tCS_min: CE# setup time 668 * @tDH_min: Data hold time 669 * @tDS_min: Data setup time 670 * @tFEAT_max: Busy time for Set Features and Get Features 671 * @tIR_min: Output hi-Z to RE# low 672 * @tITC_max: Interface and Timing Mode Change time 673 * @tRC_min: RE# cycle time 674 * @tREA_max: RE# access time 675 * @tREH_min: RE# high hold time 676 * @tRHOH_min: RE# high to output hold 677 * @tRHW_min: RE# high to WE# low 678 * @tRHZ_max: RE# high to output hi-Z 679 * @tRLOH_min: RE# low to output hold 680 * @tRP_min: RE# pulse width 681 * @tRR_min: Ready to RE# low (data only) 682 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 683 * rising edge of R/B#. 684 * @tWB_max: WE# high to SR[6] low 685 * @tWC_min: WE# cycle time 686 * @tWH_min: WE# high hold time 687 * @tWHR_min: WE# high to RE# low 688 * @tWP_min: WE# pulse width 689 * @tWW_min: WP# transition to WE# low 690 */ 691 struct nand_sdr_timings { 692 u64 tBERS_max; 693 u32 tCCS_min; 694 u64 tPROG_max; 695 u64 tR_max; 696 u32 tALH_min; 697 u32 tADL_min; 698 u32 tALS_min; 699 u32 tAR_min; 700 u32 tCEA_max; 701 u32 tCEH_min; 702 u32 tCH_min; 703 u32 tCHZ_max; 704 u32 tCLH_min; 705 u32 tCLR_min; 706 u32 tCLS_min; 707 u32 tCOH_min; 708 u32 tCS_min; 709 u32 tDH_min; 710 u32 tDS_min; 711 u32 tFEAT_max; 712 u32 tIR_min; 713 u32 tITC_max; 714 u32 tRC_min; 715 u32 tREA_max; 716 u32 tREH_min; 717 u32 tRHOH_min; 718 u32 tRHW_min; 719 u32 tRHZ_max; 720 u32 tRLOH_min; 721 u32 tRP_min; 722 u32 tRR_min; 723 u64 tRST_max; 724 u32 tWB_max; 725 u32 tWC_min; 726 u32 tWH_min; 727 u32 tWHR_min; 728 u32 tWP_min; 729 u32 tWW_min; 730 }; 731 732 /** 733 * enum nand_data_interface_type - NAND interface timing type 734 * @NAND_SDR_IFACE: Single Data Rate interface 735 */ 736 enum nand_data_interface_type { 737 NAND_SDR_IFACE, 738 }; 739 740 /** 741 * struct nand_data_interface - NAND interface timing 742 * @type: type of the timing 743 * @timings: The timing, type according to @type 744 */ 745 struct nand_data_interface { 746 enum nand_data_interface_type type; 747 union { 748 struct nand_sdr_timings sdr; 749 } timings; 750 }; 751 752 /** 753 * nand_get_sdr_timings - get SDR timing from data interface 754 * @conf: The data interface 755 */ 756 static inline const struct nand_sdr_timings * 757 nand_get_sdr_timings(const struct nand_data_interface *conf) 758 { 759 if (conf->type != NAND_SDR_IFACE) 760 return ERR_PTR(-EINVAL); 761 762 return &conf->timings.sdr; 763 } 764 765 /** 766 * struct nand_chip - NAND Private Flash Chip Data 767 * @mtd: MTD device registered to the MTD framework 768 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 769 * flash device 770 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 771 * flash device. 772 * @flash_node: [BOARDSPECIFIC] device node describing this instance 773 * @read_byte: [REPLACEABLE] read one byte from the chip 774 * @read_word: [REPLACEABLE] read one word from the chip 775 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 776 * low 8 I/O lines 777 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 778 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 779 * @select_chip: [REPLACEABLE] select chip nr 780 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 781 * @block_markbad: [REPLACEABLE] mark a block bad 782 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 783 * ALE/CLE/nCE. Also used to write command and address 784 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 785 * device ready/busy line. If set to NULL no access to 786 * ready/busy is available and the ready/busy information 787 * is read from the chip status register. 788 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 789 * commands to the chip. 790 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 791 * ready. 792 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 793 * setting the read-retry mode. Mostly needed for MLC NAND. 794 * @ecc: [BOARDSPECIFIC] ECC control structure 795 * @buffers: buffer structure for read/write 796 * @buf_align: minimum buffer alignment required by a platform 797 * @hwcontrol: platform-specific hardware control structure 798 * @erase: [REPLACEABLE] erase function 799 * @scan_bbt: [REPLACEABLE] function to scan bad block table 800 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 801 * data from array to read regs (tR). 802 * @state: [INTERN] the current state of the NAND device 803 * @oob_poi: "poison value buffer," used for laying out OOB data 804 * before writing 805 * @page_shift: [INTERN] number of address bits in a page (column 806 * address bits). 807 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 808 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 809 * @chip_shift: [INTERN] number of address bits in one chip 810 * @options: [BOARDSPECIFIC] various chip options. They can partly 811 * be set to inform nand_scan about special functionality. 812 * See the defines for further explanation. 813 * @bbt_options: [INTERN] bad block specific options. All options used 814 * here must come from bbm.h. By default, these options 815 * will be copied to the appropriate nand_bbt_descr's. 816 * @badblockpos: [INTERN] position of the bad block marker in the oob 817 * area. 818 * @badblockbits: [INTERN] minimum number of set bits in a good block's 819 * bad block marker position; i.e., BBM == 11110111b is 820 * not bad when badblockbits == 7 821 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 822 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 823 * Minimum amount of bit errors per @ecc_step_ds guaranteed 824 * to be correctable. If unknown, set to zero. 825 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 826 * also from the datasheet. It is the recommended ECC step 827 * size, if known; if unknown, set to zero. 828 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 829 * set to the actually used ONFI mode if the chip is 830 * ONFI compliant or deduced from the datasheet if 831 * the NAND chip is not ONFI compliant. 832 * @numchips: [INTERN] number of physical chips 833 * @chipsize: [INTERN] the size of one chip for multichip arrays 834 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 835 * @pagebuf: [INTERN] holds the pagenumber which is currently in 836 * data_buf. 837 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 838 * currently in data_buf. 839 * @subpagesize: [INTERN] holds the subpagesize 840 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 841 * non 0 if ONFI supported. 842 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 843 * non 0 if JEDEC supported. 844 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 845 * supported, 0 otherwise. 846 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 847 * supported, 0 otherwise. 848 * @read_retries: [INTERN] the number of read retry modes supported 849 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 850 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 851 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 852 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 853 * means the configuration should not be applied but 854 * only checked. 855 * @bbt: [INTERN] bad block table pointer 856 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 857 * lookup. 858 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 859 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 860 * bad block scan. 861 * @controller: [REPLACEABLE] a pointer to a hardware controller 862 * structure which is shared among multiple independent 863 * devices. 864 * @priv: [OPTIONAL] pointer to private chip data 865 * @write_page: [REPLACEABLE] High-level page write function 866 */ 867 868 struct nand_chip { 869 struct mtd_info mtd; 870 void __iomem *IO_ADDR_R; 871 void __iomem *IO_ADDR_W; 872 873 int flash_node; 874 875 uint8_t (*read_byte)(struct mtd_info *mtd); 876 u16 (*read_word)(struct mtd_info *mtd); 877 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 878 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 879 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 880 void (*select_chip)(struct mtd_info *mtd, int chip); 881 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 882 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 883 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 884 int (*dev_ready)(struct mtd_info *mtd); 885 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 886 int page_addr); 887 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 888 int (*erase)(struct mtd_info *mtd, int page); 889 int (*scan_bbt)(struct mtd_info *mtd); 890 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 891 uint32_t offset, int data_len, const uint8_t *buf, 892 int oob_required, int page, int raw); 893 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 894 int feature_addr, uint8_t *subfeature_para); 895 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 896 int feature_addr, uint8_t *subfeature_para); 897 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 898 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 899 const struct nand_data_interface *conf); 900 901 902 int chip_delay; 903 unsigned int options; 904 unsigned int bbt_options; 905 906 int page_shift; 907 int phys_erase_shift; 908 int bbt_erase_shift; 909 int chip_shift; 910 int numchips; 911 uint64_t chipsize; 912 int pagemask; 913 int pagebuf; 914 unsigned int pagebuf_bitflips; 915 int subpagesize; 916 uint8_t bits_per_cell; 917 uint16_t ecc_strength_ds; 918 uint16_t ecc_step_ds; 919 int onfi_timing_mode_default; 920 int badblockpos; 921 int badblockbits; 922 923 int onfi_version; 924 int jedec_version; 925 struct nand_onfi_params onfi_params; 926 struct nand_jedec_params jedec_params; 927 928 struct nand_data_interface *data_interface; 929 930 int read_retries; 931 932 flstate_t state; 933 934 uint8_t *oob_poi; 935 struct nand_hw_control *controller; 936 struct nand_ecclayout *ecclayout; 937 938 struct nand_ecc_ctrl ecc; 939 struct nand_buffers *buffers; 940 unsigned long buf_align; 941 struct nand_hw_control hwcontrol; 942 943 uint8_t *bbt; 944 struct nand_bbt_descr *bbt_td; 945 struct nand_bbt_descr *bbt_md; 946 947 struct nand_bbt_descr *badblock_pattern; 948 949 void *priv; 950 }; 951 952 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 953 { 954 return container_of(mtd, struct nand_chip, mtd); 955 } 956 957 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 958 { 959 return &chip->mtd; 960 } 961 962 static inline void *nand_get_controller_data(struct nand_chip *chip) 963 { 964 return chip->priv; 965 } 966 967 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 968 { 969 chip->priv = priv; 970 } 971 972 /* 973 * NAND Flash Manufacturer ID Codes 974 */ 975 #define NAND_MFR_TOSHIBA 0x98 976 #define NAND_MFR_SAMSUNG 0xec 977 #define NAND_MFR_FUJITSU 0x04 978 #define NAND_MFR_NATIONAL 0x8f 979 #define NAND_MFR_RENESAS 0x07 980 #define NAND_MFR_STMICRO 0x20 981 #define NAND_MFR_HYNIX 0xad 982 #define NAND_MFR_MICRON 0x2c 983 #define NAND_MFR_AMD 0x01 984 #define NAND_MFR_MACRONIX 0xc2 985 #define NAND_MFR_EON 0x92 986 #define NAND_MFR_SANDISK 0x45 987 #define NAND_MFR_INTEL 0x89 988 #define NAND_MFR_ATO 0x9b 989 990 /* The maximum expected count of bytes in the NAND ID sequence */ 991 #define NAND_MAX_ID_LEN 8 992 993 /* 994 * A helper for defining older NAND chips where the second ID byte fully 995 * defined the chip, including the geometry (chip size, eraseblock size, page 996 * size). All these chips have 512 bytes NAND page size. 997 */ 998 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 999 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1000 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1001 1002 /* 1003 * A helper for defining newer chips which report their page size and 1004 * eraseblock size via the extended ID bytes. 1005 * 1006 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1007 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1008 * device ID now only represented a particular total chip size (and voltage, 1009 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1010 * using the same device ID. 1011 */ 1012 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1013 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1014 .options = (opts) } 1015 1016 #define NAND_ECC_INFO(_strength, _step) \ 1017 { .strength_ds = (_strength), .step_ds = (_step) } 1018 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1019 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1020 1021 /** 1022 * struct nand_flash_dev - NAND Flash Device ID Structure 1023 * @name: a human-readable name of the NAND chip 1024 * @dev_id: the device ID (the second byte of the full chip ID array) 1025 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1026 * memory address as @id[0]) 1027 * @dev_id: device ID part of the full chip ID array (refers the same memory 1028 * address as @id[1]) 1029 * @id: full device ID array 1030 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1031 * well as the eraseblock size) is determined from the extended NAND 1032 * chip ID array) 1033 * @chipsize: total chip size in MiB 1034 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1035 * @options: stores various chip bit options 1036 * @id_len: The valid length of the @id. 1037 * @oobsize: OOB size 1038 * @ecc: ECC correctability and step information from the datasheet. 1039 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1040 * @ecc_strength_ds in nand_chip{}. 1041 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1042 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1043 * For example, the "4bit ECC for each 512Byte" can be set with 1044 * NAND_ECC_INFO(4, 512). 1045 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1046 * reset. Should be deduced from timings described 1047 * in the datasheet. 1048 * 1049 */ 1050 struct nand_flash_dev { 1051 char *name; 1052 union { 1053 struct { 1054 uint8_t mfr_id; 1055 uint8_t dev_id; 1056 }; 1057 uint8_t id[NAND_MAX_ID_LEN]; 1058 }; 1059 unsigned int pagesize; 1060 unsigned int chipsize; 1061 unsigned int erasesize; 1062 unsigned int options; 1063 uint16_t id_len; 1064 uint16_t oobsize; 1065 struct { 1066 uint16_t strength_ds; 1067 uint16_t step_ds; 1068 } ecc; 1069 int onfi_timing_mode_default; 1070 }; 1071 1072 /** 1073 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 1074 * @name: Manufacturer name 1075 * @id: manufacturer ID code of device. 1076 */ 1077 struct nand_manufacturers { 1078 int id; 1079 char *name; 1080 }; 1081 1082 extern struct nand_flash_dev nand_flash_ids[]; 1083 extern struct nand_manufacturers nand_manuf_ids[]; 1084 1085 int nand_default_bbt(struct mtd_info *mtd); 1086 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1087 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1088 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1089 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1090 int allowbbt); 1091 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1092 size_t *retlen, uint8_t *buf); 1093 1094 /* 1095 * Constants for oob configuration 1096 */ 1097 #define NAND_SMALL_BADBLOCK_POS 5 1098 #define NAND_LARGE_BADBLOCK_POS 0 1099 1100 /** 1101 * struct platform_nand_chip - chip level device structure 1102 * @nr_chips: max. number of chips to scan for 1103 * @chip_offset: chip number offset 1104 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1105 * @partitions: mtd partition list 1106 * @chip_delay: R/B delay value in us 1107 * @options: Option flags, e.g. 16bit buswidth 1108 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1109 * @part_probe_types: NULL-terminated array of probe types 1110 */ 1111 struct platform_nand_chip { 1112 int nr_chips; 1113 int chip_offset; 1114 int nr_partitions; 1115 struct mtd_partition *partitions; 1116 int chip_delay; 1117 unsigned int options; 1118 unsigned int bbt_options; 1119 const char **part_probe_types; 1120 }; 1121 1122 /* Keep gcc happy */ 1123 struct platform_device; 1124 1125 /** 1126 * struct platform_nand_ctrl - controller level device structure 1127 * @probe: platform specific function to probe/setup hardware 1128 * @remove: platform specific function to remove/teardown hardware 1129 * @hwcontrol: platform specific hardware control structure 1130 * @dev_ready: platform specific function to read ready/busy pin 1131 * @select_chip: platform specific chip select function 1132 * @cmd_ctrl: platform specific function for controlling 1133 * ALE/CLE/nCE. Also used to write command and address 1134 * @write_buf: platform specific function for write buffer 1135 * @read_buf: platform specific function for read buffer 1136 * @read_byte: platform specific function to read one byte from chip 1137 * @priv: private data to transport driver specific settings 1138 * 1139 * All fields are optional and depend on the hardware driver requirements 1140 */ 1141 struct platform_nand_ctrl { 1142 int (*probe)(struct platform_device *pdev); 1143 void (*remove)(struct platform_device *pdev); 1144 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1145 int (*dev_ready)(struct mtd_info *mtd); 1146 void (*select_chip)(struct mtd_info *mtd, int chip); 1147 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1148 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1149 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1150 unsigned char (*read_byte)(struct mtd_info *mtd); 1151 void *priv; 1152 }; 1153 1154 /** 1155 * struct platform_nand_data - container structure for platform-specific data 1156 * @chip: chip level chip structure 1157 * @ctrl: controller level device structure 1158 */ 1159 struct platform_nand_data { 1160 struct platform_nand_chip chip; 1161 struct platform_nand_ctrl ctrl; 1162 }; 1163 1164 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 1165 /* return the supported features. */ 1166 static inline int onfi_feature(struct nand_chip *chip) 1167 { 1168 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1169 } 1170 1171 /* return the supported asynchronous timing mode. */ 1172 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1173 { 1174 if (!chip->onfi_version) 1175 return ONFI_TIMING_MODE_UNKNOWN; 1176 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1177 } 1178 1179 /* return the supported synchronous timing mode. */ 1180 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1181 { 1182 if (!chip->onfi_version) 1183 return ONFI_TIMING_MODE_UNKNOWN; 1184 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1185 } 1186 #else 1187 static inline int onfi_feature(struct nand_chip *chip) 1188 { 1189 return 0; 1190 } 1191 1192 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1193 { 1194 return ONFI_TIMING_MODE_UNKNOWN; 1195 } 1196 1197 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1198 { 1199 return ONFI_TIMING_MODE_UNKNOWN; 1200 } 1201 #endif 1202 1203 int onfi_init_data_interface(struct nand_chip *chip, 1204 struct nand_data_interface *iface, 1205 enum nand_data_interface_type type, 1206 int timing_mode); 1207 1208 /* 1209 * Check if it is a SLC nand. 1210 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1211 * We do not distinguish the MLC and TLC now. 1212 */ 1213 static inline bool nand_is_slc(struct nand_chip *chip) 1214 { 1215 return chip->bits_per_cell == 1; 1216 } 1217 1218 /** 1219 * Check if the opcode's address should be sent only on the lower 8 bits 1220 * @command: opcode to check 1221 */ 1222 static inline int nand_opcode_8bits(unsigned int command) 1223 { 1224 switch (command) { 1225 case NAND_CMD_READID: 1226 case NAND_CMD_PARAM: 1227 case NAND_CMD_GET_FEATURES: 1228 case NAND_CMD_SET_FEATURES: 1229 return 1; 1230 default: 1231 break; 1232 } 1233 return 0; 1234 } 1235 1236 /* return the supported JEDEC features. */ 1237 static inline int jedec_feature(struct nand_chip *chip) 1238 { 1239 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1240 : 0; 1241 } 1242 1243 /* Standard NAND functions from nand_base.c */ 1244 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1245 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1246 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1247 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1248 uint8_t nand_read_byte(struct mtd_info *mtd); 1249 1250 /* get timing characteristics from ONFI timing mode. */ 1251 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1252 /* get data interface from ONFI timing mode 0, used after reset. */ 1253 const struct nand_data_interface *nand_get_default_data_interface(void); 1254 1255 int nand_check_erased_ecc_chunk(void *data, int datalen, 1256 void *ecc, int ecclen, 1257 void *extraoob, int extraooblen, 1258 int threshold); 1259 1260 int nand_check_ecc_caps(struct nand_chip *chip, 1261 const struct nand_ecc_caps *caps, int oobavail); 1262 1263 int nand_match_ecc_req(struct nand_chip *chip, 1264 const struct nand_ecc_caps *caps, int oobavail); 1265 1266 int nand_maximize_ecc(struct nand_chip *chip, 1267 const struct nand_ecc_caps *caps, int oobavail); 1268 1269 /* Reset and initialize a NAND device */ 1270 int nand_reset(struct nand_chip *chip, int chipnr); 1271 #endif /* __LINUX_MTD_RAWNAND_H */ 1272