1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 4 * Steven J. Hill <sjhill@realitydiluted.com> 5 * Thomas Gleixner <tglx@linutronix.de> 6 * 7 * Info: 8 * Contains standard defines and IDs for NAND flash devices 9 * 10 * Changelog: 11 * See git changelog. 12 */ 13 #ifndef __LINUX_MTD_RAWNAND_H 14 #define __LINUX_MTD_RAWNAND_H 15 16 #include <config.h> 17 18 #include <linux/compat.h> 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/flashchip.h> 21 #include <linux/mtd/bbm.h> 22 #include <asm/cache.h> 23 24 struct mtd_info; 25 struct nand_chip; 26 struct nand_flash_dev; 27 struct device_node; 28 29 /* Get the flash and manufacturer id and lookup if the type is supported. */ 30 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, 31 struct nand_chip *chip, 32 int *maf_id, int *dev_id, 33 struct nand_flash_dev *type); 34 35 /* Scan and identify a NAND device */ 36 int nand_scan(struct mtd_info *mtd, int max_chips); 37 /* 38 * Separate phases of nand_scan(), allowing board driver to intervene 39 * and override command or ECC setup according to flash type. 40 */ 41 int nand_scan_ident(struct mtd_info *mtd, int max_chips, 42 struct nand_flash_dev *table); 43 int nand_scan_tail(struct mtd_info *mtd); 44 45 /* Free resources held by the NAND device */ 46 void nand_release(struct mtd_info *mtd); 47 48 /* Internal helper for board drivers which need to override command function */ 49 void nand_wait_ready(struct mtd_info *mtd); 50 51 /* 52 * This constant declares the max. oobsize / page, which 53 * is supported now. If you add a chip with bigger oobsize/page 54 * adjust this accordingly. 55 */ 56 #define NAND_MAX_OOBSIZE 1664 57 #define NAND_MAX_PAGESIZE 16384 58 59 /* 60 * Constants for hardware specific CLE/ALE/NCE function 61 * 62 * These are bits which can be or'ed to set/clear multiple 63 * bits in one go. 64 */ 65 /* Select the chip by setting nCE to low */ 66 #define NAND_NCE 0x01 67 /* Select the command latch by setting CLE to high */ 68 #define NAND_CLE 0x02 69 /* Select the address latch by setting ALE to high */ 70 #define NAND_ALE 0x04 71 72 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 73 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 74 #define NAND_CTRL_CHANGE 0x80 75 76 /* 77 * Standard NAND flash commands 78 */ 79 #define NAND_CMD_READ0 0 80 #define NAND_CMD_READ1 1 81 #define NAND_CMD_RNDOUT 5 82 #define NAND_CMD_PAGEPROG 0x10 83 #define NAND_CMD_READOOB 0x50 84 #define NAND_CMD_ERASE1 0x60 85 #define NAND_CMD_STATUS 0x70 86 #define NAND_CMD_SEQIN 0x80 87 #define NAND_CMD_RNDIN 0x85 88 #define NAND_CMD_READID 0x90 89 #define NAND_CMD_ERASE2 0xd0 90 #define NAND_CMD_PARAM 0xec 91 #define NAND_CMD_GET_FEATURES 0xee 92 #define NAND_CMD_SET_FEATURES 0xef 93 #define NAND_CMD_RESET 0xff 94 95 #define NAND_CMD_LOCK 0x2a 96 #define NAND_CMD_UNLOCK1 0x23 97 #define NAND_CMD_UNLOCK2 0x24 98 99 /* Extended commands for large page devices */ 100 #define NAND_CMD_READSTART 0x30 101 #define NAND_CMD_RNDOUTSTART 0xE0 102 #define NAND_CMD_CACHEDPROG 0x15 103 104 /* Extended commands for AG-AND device */ 105 /* 106 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 107 * there is no way to distinguish that from NAND_CMD_READ0 108 * until the remaining sequence of commands has been completed 109 * so add a high order bit and mask it off in the command. 110 */ 111 #define NAND_CMD_DEPLETE1 0x100 112 #define NAND_CMD_DEPLETE2 0x38 113 #define NAND_CMD_STATUS_MULTI 0x71 114 #define NAND_CMD_STATUS_ERROR 0x72 115 /* multi-bank error status (banks 0-3) */ 116 #define NAND_CMD_STATUS_ERROR0 0x73 117 #define NAND_CMD_STATUS_ERROR1 0x74 118 #define NAND_CMD_STATUS_ERROR2 0x75 119 #define NAND_CMD_STATUS_ERROR3 0x76 120 #define NAND_CMD_STATUS_RESET 0x7f 121 #define NAND_CMD_STATUS_CLEAR 0xff 122 123 #define NAND_CMD_NONE -1 124 125 /* Status bits */ 126 #define NAND_STATUS_FAIL 0x01 127 #define NAND_STATUS_FAIL_N1 0x02 128 #define NAND_STATUS_TRUE_READY 0x20 129 #define NAND_STATUS_READY 0x40 130 #define NAND_STATUS_WP 0x80 131 132 #define NAND_DATA_IFACE_CHECK_ONLY -1 133 134 /* 135 * Constants for ECC_MODES 136 */ 137 typedef enum { 138 NAND_ECC_NONE, 139 NAND_ECC_SOFT, 140 NAND_ECC_HW, 141 NAND_ECC_HW_SYNDROME, 142 NAND_ECC_HW_OOB_FIRST, 143 NAND_ECC_SOFT_BCH, 144 } nand_ecc_modes_t; 145 146 enum nand_ecc_algo { 147 NAND_ECC_UNKNOWN, 148 NAND_ECC_HAMMING, 149 NAND_ECC_BCH, 150 }; 151 152 /* 153 * Constants for Hardware ECC 154 */ 155 /* Reset Hardware ECC for read */ 156 #define NAND_ECC_READ 0 157 /* Reset Hardware ECC for write */ 158 #define NAND_ECC_WRITE 1 159 /* Enable Hardware ECC before syndrome is read back from flash */ 160 #define NAND_ECC_READSYN 2 161 162 /* 163 * Enable generic NAND 'page erased' check. This check is only done when 164 * ecc.correct() returns -EBADMSG. 165 * Set this flag if your implementation does not fix bitflips in erased 166 * pages and you want to rely on the default implementation. 167 */ 168 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 169 #define NAND_ECC_MAXIMIZE BIT(1) 170 /* 171 * If your controller already sends the required NAND commands when 172 * reading or writing a page, then the framework is not supposed to 173 * send READ0 and SEQIN/PAGEPROG respectively. 174 */ 175 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 176 177 /* Bit mask for flags passed to do_nand_read_ecc */ 178 #define NAND_GET_DEVICE 0x80 179 180 181 /* 182 * Option constants for bizarre disfunctionality and real 183 * features. 184 */ 185 /* Buswidth is 16 bit */ 186 #define NAND_BUSWIDTH_16 0x00000002 187 /* Device supports partial programming without padding */ 188 #define NAND_NO_PADDING 0x00000004 189 /* Chip has cache program function */ 190 #define NAND_CACHEPRG 0x00000008 191 /* Chip has copy back function */ 192 #define NAND_COPYBACK 0x00000010 193 /* 194 * Chip requires ready check on read (for auto-incremented sequential read). 195 * True only for small page devices; large page devices do not support 196 * autoincrement. 197 */ 198 #define NAND_NEED_READRDY 0x00000100 199 200 /* Chip does not allow subpage writes */ 201 #define NAND_NO_SUBPAGE_WRITE 0x00000200 202 203 /* Device is one of 'new' xD cards that expose fake nand command set */ 204 #define NAND_BROKEN_XD 0x00000400 205 206 /* Device behaves just like nand, but is readonly */ 207 #define NAND_ROM 0x00000800 208 209 /* Device supports subpage reads */ 210 #define NAND_SUBPAGE_READ 0x00001000 211 212 /* 213 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 214 * patterns. 215 */ 216 #define NAND_NEED_SCRAMBLING 0x00002000 217 218 /* Device needs 3rd row address cycle */ 219 #define NAND_ROW_ADDR_3 0x00004000 220 221 /* Options valid for Samsung large page devices */ 222 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 223 224 /* Macros to identify the above */ 225 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 226 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 227 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 228 229 /* Non chip related options */ 230 /* This option skips the bbt scan during initialization. */ 231 #define NAND_SKIP_BBTSCAN 0x00010000 232 /* 233 * This option is defined if the board driver allocates its own buffers 234 * (e.g. because it needs them DMA-coherent). 235 */ 236 #define NAND_OWN_BUFFERS 0x00020000 237 /* Chip may not exist, so silence any errors in scan */ 238 #define NAND_SCAN_SILENT_NODEV 0x00040000 239 /* 240 * Autodetect nand buswidth with readid/onfi. 241 * This suppose the driver will configure the hardware in 8 bits mode 242 * when calling nand_scan_ident, and update its configuration 243 * before calling nand_scan_tail. 244 */ 245 #define NAND_BUSWIDTH_AUTO 0x00080000 246 /* 247 * This option could be defined by controller drivers to protect against 248 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 249 */ 250 #define NAND_USE_BOUNCE_BUFFER 0x00100000 251 252 /* Options set by nand scan */ 253 /* bbt has already been read */ 254 #define NAND_BBT_SCANNED 0x40000000 255 /* Nand scan has allocated controller struct */ 256 #define NAND_CONTROLLER_ALLOC 0x80000000 257 258 /* Cell info constants */ 259 #define NAND_CI_CHIPNR_MSK 0x03 260 #define NAND_CI_CELLTYPE_MSK 0x0C 261 #define NAND_CI_CELLTYPE_SHIFT 2 262 263 /* ONFI features */ 264 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 265 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 266 267 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 268 #define ONFI_TIMING_MODE_0 (1 << 0) 269 #define ONFI_TIMING_MODE_1 (1 << 1) 270 #define ONFI_TIMING_MODE_2 (1 << 2) 271 #define ONFI_TIMING_MODE_3 (1 << 3) 272 #define ONFI_TIMING_MODE_4 (1 << 4) 273 #define ONFI_TIMING_MODE_5 (1 << 5) 274 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 275 276 /* ONFI feature address */ 277 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 278 279 /* Vendor-specific feature address (Micron) */ 280 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 281 282 /* ONFI subfeature parameters length */ 283 #define ONFI_SUBFEATURE_PARAM_LEN 4 284 285 /* ONFI optional commands SET/GET FEATURES supported? */ 286 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 287 288 struct nand_onfi_params { 289 /* rev info and features block */ 290 /* 'O' 'N' 'F' 'I' */ 291 u8 sig[4]; 292 __le16 revision; 293 __le16 features; 294 __le16 opt_cmd; 295 u8 reserved0[2]; 296 __le16 ext_param_page_length; /* since ONFI 2.1 */ 297 u8 num_of_param_pages; /* since ONFI 2.1 */ 298 u8 reserved1[17]; 299 300 /* manufacturer information block */ 301 char manufacturer[12]; 302 char model[20]; 303 u8 jedec_id; 304 __le16 date_code; 305 u8 reserved2[13]; 306 307 /* memory organization block */ 308 __le32 byte_per_page; 309 __le16 spare_bytes_per_page; 310 __le32 data_bytes_per_ppage; 311 __le16 spare_bytes_per_ppage; 312 __le32 pages_per_block; 313 __le32 blocks_per_lun; 314 u8 lun_count; 315 u8 addr_cycles; 316 u8 bits_per_cell; 317 __le16 bb_per_lun; 318 __le16 block_endurance; 319 u8 guaranteed_good_blocks; 320 __le16 guaranteed_block_endurance; 321 u8 programs_per_page; 322 u8 ppage_attr; 323 u8 ecc_bits; 324 u8 interleaved_bits; 325 u8 interleaved_ops; 326 u8 reserved3[13]; 327 328 /* electrical parameter block */ 329 u8 io_pin_capacitance_max; 330 __le16 async_timing_mode; 331 __le16 program_cache_timing_mode; 332 __le16 t_prog; 333 __le16 t_bers; 334 __le16 t_r; 335 __le16 t_ccs; 336 __le16 src_sync_timing_mode; 337 u8 src_ssync_features; 338 __le16 clk_pin_capacitance_typ; 339 __le16 io_pin_capacitance_typ; 340 __le16 input_pin_capacitance_typ; 341 u8 input_pin_capacitance_max; 342 u8 driver_strength_support; 343 __le16 t_int_r; 344 __le16 t_adl; 345 u8 reserved4[8]; 346 347 /* vendor */ 348 __le16 vendor_revision; 349 u8 vendor[88]; 350 351 __le16 crc; 352 } __packed; 353 354 #define ONFI_CRC_BASE 0x4F4E 355 356 /* Extended ECC information Block Definition (since ONFI 2.1) */ 357 struct onfi_ext_ecc_info { 358 u8 ecc_bits; 359 u8 codeword_size; 360 __le16 bb_per_lun; 361 __le16 block_endurance; 362 u8 reserved[2]; 363 } __packed; 364 365 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 366 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 367 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 368 struct onfi_ext_section { 369 u8 type; 370 u8 length; 371 } __packed; 372 373 #define ONFI_EXT_SECTION_MAX 8 374 375 /* Extended Parameter Page Definition (since ONFI 2.1) */ 376 struct onfi_ext_param_page { 377 __le16 crc; 378 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 379 u8 reserved0[10]; 380 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 381 382 /* 383 * The actual size of the Extended Parameter Page is in 384 * @ext_param_page_length of nand_onfi_params{}. 385 * The following are the variable length sections. 386 * So we do not add any fields below. Please see the ONFI spec. 387 */ 388 } __packed; 389 390 struct nand_onfi_vendor_micron { 391 u8 two_plane_read; 392 u8 read_cache; 393 u8 read_unique_id; 394 u8 dq_imped; 395 u8 dq_imped_num_settings; 396 u8 dq_imped_feat_addr; 397 u8 rb_pulldown_strength; 398 u8 rb_pulldown_strength_feat_addr; 399 u8 rb_pulldown_strength_num_settings; 400 u8 otp_mode; 401 u8 otp_page_start; 402 u8 otp_data_prot_addr; 403 u8 otp_num_pages; 404 u8 otp_feat_addr; 405 u8 read_retry_options; 406 u8 reserved[72]; 407 u8 param_revision; 408 } __packed; 409 410 struct jedec_ecc_info { 411 u8 ecc_bits; 412 u8 codeword_size; 413 __le16 bb_per_lun; 414 __le16 block_endurance; 415 u8 reserved[2]; 416 } __packed; 417 418 /* JEDEC features */ 419 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 420 421 struct nand_jedec_params { 422 /* rev info and features block */ 423 /* 'J' 'E' 'S' 'D' */ 424 u8 sig[4]; 425 __le16 revision; 426 __le16 features; 427 u8 opt_cmd[3]; 428 __le16 sec_cmd; 429 u8 num_of_param_pages; 430 u8 reserved0[18]; 431 432 /* manufacturer information block */ 433 char manufacturer[12]; 434 char model[20]; 435 u8 jedec_id[6]; 436 u8 reserved1[10]; 437 438 /* memory organization block */ 439 __le32 byte_per_page; 440 __le16 spare_bytes_per_page; 441 u8 reserved2[6]; 442 __le32 pages_per_block; 443 __le32 blocks_per_lun; 444 u8 lun_count; 445 u8 addr_cycles; 446 u8 bits_per_cell; 447 u8 programs_per_page; 448 u8 multi_plane_addr; 449 u8 multi_plane_op_attr; 450 u8 reserved3[38]; 451 452 /* electrical parameter block */ 453 __le16 async_sdr_speed_grade; 454 __le16 toggle_ddr_speed_grade; 455 __le16 sync_ddr_speed_grade; 456 u8 async_sdr_features; 457 u8 toggle_ddr_features; 458 u8 sync_ddr_features; 459 __le16 t_prog; 460 __le16 t_bers; 461 __le16 t_r; 462 __le16 t_r_multi_plane; 463 __le16 t_ccs; 464 __le16 io_pin_capacitance_typ; 465 __le16 input_pin_capacitance_typ; 466 __le16 clk_pin_capacitance_typ; 467 u8 driver_strength_support; 468 __le16 t_adl; 469 u8 reserved4[36]; 470 471 /* ECC and endurance block */ 472 u8 guaranteed_good_blocks; 473 __le16 guaranteed_block_endurance; 474 struct jedec_ecc_info ecc_info[4]; 475 u8 reserved5[29]; 476 477 /* reserved */ 478 u8 reserved6[148]; 479 480 /* vendor */ 481 __le16 vendor_rev_num; 482 u8 reserved7[88]; 483 484 /* CRC for Parameter Page */ 485 __le16 crc; 486 } __packed; 487 488 /** 489 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 490 * @lock: protection lock 491 * @active: the mtd device which holds the controller currently 492 * @wq: wait queue to sleep on if a NAND operation is in 493 * progress used instead of the per chip wait queue 494 * when a hw controller is available. 495 */ 496 struct nand_hw_control { 497 spinlock_t lock; 498 struct nand_chip *active; 499 }; 500 501 /** 502 * struct nand_ecc_step_info - ECC step information of ECC engine 503 * @stepsize: data bytes per ECC step 504 * @strengths: array of supported strengths 505 * @nstrengths: number of supported strengths 506 */ 507 struct nand_ecc_step_info { 508 int stepsize; 509 const int *strengths; 510 int nstrengths; 511 }; 512 513 /** 514 * struct nand_ecc_caps - capability of ECC engine 515 * @stepinfos: array of ECC step information 516 * @nstepinfos: number of ECC step information 517 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 518 */ 519 struct nand_ecc_caps { 520 const struct nand_ecc_step_info *stepinfos; 521 int nstepinfos; 522 int (*calc_ecc_bytes)(int step_size, int strength); 523 }; 524 525 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 526 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 527 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 528 static const struct nand_ecc_step_info __name##_stepinfo = { \ 529 .stepsize = __step, \ 530 .strengths = __name##_strengths, \ 531 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 532 }; \ 533 static const struct nand_ecc_caps __name = { \ 534 .stepinfos = &__name##_stepinfo, \ 535 .nstepinfos = 1, \ 536 .calc_ecc_bytes = __calc, \ 537 } 538 539 /** 540 * struct nand_ecc_ctrl - Control structure for ECC 541 * @mode: ECC mode 542 * @algo: ECC algorithm 543 * @steps: number of ECC steps per page 544 * @size: data bytes per ECC step 545 * @bytes: ECC bytes per step 546 * @strength: max number of correctible bits per ECC step 547 * @total: total number of ECC bytes per page 548 * @prepad: padding information for syndrome based ECC generators 549 * @postpad: padding information for syndrome based ECC generators 550 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 551 * @layout: ECC layout control struct pointer 552 * @priv: pointer to private ECC control data 553 * @hwctl: function to control hardware ECC generator. Must only 554 * be provided if an hardware ECC is available 555 * @calculate: function for ECC calculation or readback from ECC hardware 556 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 557 * Should return a positive number representing the number of 558 * corrected bitflips, -EBADMSG if the number of bitflips exceed 559 * ECC strength, or any other error code if the error is not 560 * directly related to correction. 561 * If -EBADMSG is returned the input buffers should be left 562 * untouched. 563 * @read_page_raw: function to read a raw page without ECC. This function 564 * should hide the specific layout used by the ECC 565 * controller and always return contiguous in-band and 566 * out-of-band data even if they're not stored 567 * contiguously on the NAND chip (e.g. 568 * NAND_ECC_HW_SYNDROME interleaves in-band and 569 * out-of-band data). 570 * @write_page_raw: function to write a raw page without ECC. This function 571 * should hide the specific layout used by the ECC 572 * controller and consider the passed data as contiguous 573 * in-band and out-of-band data. ECC controller is 574 * responsible for doing the appropriate transformations 575 * to adapt to its specific layout (e.g. 576 * NAND_ECC_HW_SYNDROME interleaves in-band and 577 * out-of-band data). 578 * @read_page: function to read a page according to the ECC generator 579 * requirements; returns maximum number of bitflips corrected in 580 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 581 * @read_subpage: function to read parts of the page covered by ECC; 582 * returns same as read_page() 583 * @write_subpage: function to write parts of the page covered by ECC. 584 * @write_page: function to write a page according to the ECC generator 585 * requirements. 586 * @write_oob_raw: function to write chip OOB data without ECC 587 * @read_oob_raw: function to read chip OOB data without ECC 588 * @read_oob: function to read chip OOB data 589 * @write_oob: function to write chip OOB data 590 */ 591 struct nand_ecc_ctrl { 592 nand_ecc_modes_t mode; 593 enum nand_ecc_algo algo; 594 int steps; 595 int size; 596 int bytes; 597 int total; 598 int strength; 599 int prepad; 600 int postpad; 601 unsigned int options; 602 struct nand_ecclayout *layout; 603 void *priv; 604 void (*hwctl)(struct mtd_info *mtd, int mode); 605 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 606 uint8_t *ecc_code); 607 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 608 uint8_t *calc_ecc); 609 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 610 uint8_t *buf, int oob_required, int page); 611 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 612 const uint8_t *buf, int oob_required, int page); 613 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 614 uint8_t *buf, int oob_required, int page); 615 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 616 uint32_t offs, uint32_t len, uint8_t *buf, int page); 617 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 618 uint32_t offset, uint32_t data_len, 619 const uint8_t *data_buf, int oob_required, int page); 620 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 621 const uint8_t *buf, int oob_required, int page); 622 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 623 int page); 624 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 625 int page); 626 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 627 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 628 int page); 629 }; 630 631 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 632 { 633 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 634 } 635 636 /** 637 * struct nand_buffers - buffer structure for read/write 638 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 639 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 640 * @databuf: buffer pointer for data, size is (page size + oobsize). 641 * 642 * Do not change the order of buffers. databuf and oobrbuf must be in 643 * consecutive order. 644 */ 645 struct nand_buffers { 646 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 647 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 648 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 649 ARCH_DMA_MINALIGN)]; 650 }; 651 652 /** 653 * struct nand_sdr_timings - SDR NAND chip timings 654 * 655 * This struct defines the timing requirements of a SDR NAND chip. 656 * These information can be found in every NAND datasheets and the timings 657 * meaning are described in the ONFI specifications: 658 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 659 * Parameters) 660 * 661 * All these timings are expressed in picoseconds. 662 * 663 * @tBERS_max: Block erase time 664 * @tCCS_min: Change column setup time 665 * @tPROG_max: Page program time 666 * @tR_max: Page read time 667 * @tALH_min: ALE hold time 668 * @tADL_min: ALE to data loading time 669 * @tALS_min: ALE setup time 670 * @tAR_min: ALE to RE# delay 671 * @tCEA_max: CE# access time 672 * @tCEH_min: CE# high hold time 673 * @tCH_min: CE# hold time 674 * @tCHZ_max: CE# high to output hi-Z 675 * @tCLH_min: CLE hold time 676 * @tCLR_min: CLE to RE# delay 677 * @tCLS_min: CLE setup time 678 * @tCOH_min: CE# high to output hold 679 * @tCS_min: CE# setup time 680 * @tDH_min: Data hold time 681 * @tDS_min: Data setup time 682 * @tFEAT_max: Busy time for Set Features and Get Features 683 * @tIR_min: Output hi-Z to RE# low 684 * @tITC_max: Interface and Timing Mode Change time 685 * @tRC_min: RE# cycle time 686 * @tREA_max: RE# access time 687 * @tREH_min: RE# high hold time 688 * @tRHOH_min: RE# high to output hold 689 * @tRHW_min: RE# high to WE# low 690 * @tRHZ_max: RE# high to output hi-Z 691 * @tRLOH_min: RE# low to output hold 692 * @tRP_min: RE# pulse width 693 * @tRR_min: Ready to RE# low (data only) 694 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 695 * rising edge of R/B#. 696 * @tWB_max: WE# high to SR[6] low 697 * @tWC_min: WE# cycle time 698 * @tWH_min: WE# high hold time 699 * @tWHR_min: WE# high to RE# low 700 * @tWP_min: WE# pulse width 701 * @tWW_min: WP# transition to WE# low 702 */ 703 struct nand_sdr_timings { 704 u64 tBERS_max; 705 u32 tCCS_min; 706 u64 tPROG_max; 707 u64 tR_max; 708 u32 tALH_min; 709 u32 tADL_min; 710 u32 tALS_min; 711 u32 tAR_min; 712 u32 tCEA_max; 713 u32 tCEH_min; 714 u32 tCH_min; 715 u32 tCHZ_max; 716 u32 tCLH_min; 717 u32 tCLR_min; 718 u32 tCLS_min; 719 u32 tCOH_min; 720 u32 tCS_min; 721 u32 tDH_min; 722 u32 tDS_min; 723 u32 tFEAT_max; 724 u32 tIR_min; 725 u32 tITC_max; 726 u32 tRC_min; 727 u32 tREA_max; 728 u32 tREH_min; 729 u32 tRHOH_min; 730 u32 tRHW_min; 731 u32 tRHZ_max; 732 u32 tRLOH_min; 733 u32 tRP_min; 734 u32 tRR_min; 735 u64 tRST_max; 736 u32 tWB_max; 737 u32 tWC_min; 738 u32 tWH_min; 739 u32 tWHR_min; 740 u32 tWP_min; 741 u32 tWW_min; 742 }; 743 744 /** 745 * enum nand_data_interface_type - NAND interface timing type 746 * @NAND_SDR_IFACE: Single Data Rate interface 747 */ 748 enum nand_data_interface_type { 749 NAND_SDR_IFACE, 750 }; 751 752 /** 753 * struct nand_data_interface - NAND interface timing 754 * @type: type of the timing 755 * @timings: The timing, type according to @type 756 */ 757 struct nand_data_interface { 758 enum nand_data_interface_type type; 759 union { 760 struct nand_sdr_timings sdr; 761 } timings; 762 }; 763 764 /** 765 * nand_get_sdr_timings - get SDR timing from data interface 766 * @conf: The data interface 767 */ 768 static inline const struct nand_sdr_timings * 769 nand_get_sdr_timings(const struct nand_data_interface *conf) 770 { 771 if (conf->type != NAND_SDR_IFACE) 772 return ERR_PTR(-EINVAL); 773 774 return &conf->timings.sdr; 775 } 776 777 /** 778 * struct nand_chip - NAND Private Flash Chip Data 779 * @mtd: MTD device registered to the MTD framework 780 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 781 * flash device 782 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 783 * flash device. 784 * @flash_node: [BOARDSPECIFIC] device node describing this instance 785 * @read_byte: [REPLACEABLE] read one byte from the chip 786 * @read_word: [REPLACEABLE] read one word from the chip 787 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 788 * low 8 I/O lines 789 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 790 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 791 * @select_chip: [REPLACEABLE] select chip nr 792 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 793 * @block_markbad: [REPLACEABLE] mark a block bad 794 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 795 * ALE/CLE/nCE. Also used to write command and address 796 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 797 * device ready/busy line. If set to NULL no access to 798 * ready/busy is available and the ready/busy information 799 * is read from the chip status register. 800 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 801 * commands to the chip. 802 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 803 * ready. 804 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 805 * setting the read-retry mode. Mostly needed for MLC NAND. 806 * @ecc: [BOARDSPECIFIC] ECC control structure 807 * @buffers: buffer structure for read/write 808 * @buf_align: minimum buffer alignment required by a platform 809 * @hwcontrol: platform-specific hardware control structure 810 * @erase: [REPLACEABLE] erase function 811 * @scan_bbt: [REPLACEABLE] function to scan bad block table 812 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 813 * data from array to read regs (tR). 814 * @state: [INTERN] the current state of the NAND device 815 * @oob_poi: "poison value buffer," used for laying out OOB data 816 * before writing 817 * @page_shift: [INTERN] number of address bits in a page (column 818 * address bits). 819 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 820 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 821 * @chip_shift: [INTERN] number of address bits in one chip 822 * @options: [BOARDSPECIFIC] various chip options. They can partly 823 * be set to inform nand_scan about special functionality. 824 * See the defines for further explanation. 825 * @bbt_options: [INTERN] bad block specific options. All options used 826 * here must come from bbm.h. By default, these options 827 * will be copied to the appropriate nand_bbt_descr's. 828 * @badblockpos: [INTERN] position of the bad block marker in the oob 829 * area. 830 * @badblockbits: [INTERN] minimum number of set bits in a good block's 831 * bad block marker position; i.e., BBM == 11110111b is 832 * not bad when badblockbits == 7 833 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 834 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 835 * Minimum amount of bit errors per @ecc_step_ds guaranteed 836 * to be correctable. If unknown, set to zero. 837 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 838 * also from the datasheet. It is the recommended ECC step 839 * size, if known; if unknown, set to zero. 840 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 841 * set to the actually used ONFI mode if the chip is 842 * ONFI compliant or deduced from the datasheet if 843 * the NAND chip is not ONFI compliant. 844 * @numchips: [INTERN] number of physical chips 845 * @chipsize: [INTERN] the size of one chip for multichip arrays 846 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 847 * @pagebuf: [INTERN] holds the pagenumber which is currently in 848 * data_buf. 849 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 850 * currently in data_buf. 851 * @subpagesize: [INTERN] holds the subpagesize 852 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 853 * non 0 if ONFI supported. 854 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 855 * non 0 if JEDEC supported. 856 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 857 * supported, 0 otherwise. 858 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 859 * supported, 0 otherwise. 860 * @read_retries: [INTERN] the number of read retry modes supported 861 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 862 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 863 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 864 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 865 * means the configuration should not be applied but 866 * only checked. 867 * @bbt: [INTERN] bad block table pointer 868 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 869 * lookup. 870 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 871 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 872 * bad block scan. 873 * @controller: [REPLACEABLE] a pointer to a hardware controller 874 * structure which is shared among multiple independent 875 * devices. 876 * @priv: [OPTIONAL] pointer to private chip data 877 * @write_page: [REPLACEABLE] High-level page write function 878 */ 879 880 struct nand_chip { 881 struct mtd_info mtd; 882 void __iomem *IO_ADDR_R; 883 void __iomem *IO_ADDR_W; 884 885 int flash_node; 886 887 uint8_t (*read_byte)(struct mtd_info *mtd); 888 u16 (*read_word)(struct mtd_info *mtd); 889 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 890 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 891 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 892 void (*select_chip)(struct mtd_info *mtd, int chip); 893 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 894 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 895 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 896 int (*dev_ready)(struct mtd_info *mtd); 897 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 898 int page_addr); 899 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 900 int (*erase)(struct mtd_info *mtd, int page); 901 int (*scan_bbt)(struct mtd_info *mtd); 902 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 903 uint32_t offset, int data_len, const uint8_t *buf, 904 int oob_required, int page, int raw); 905 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 906 int feature_addr, uint8_t *subfeature_para); 907 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 908 int feature_addr, uint8_t *subfeature_para); 909 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 910 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 911 const struct nand_data_interface *conf); 912 913 914 int chip_delay; 915 unsigned int options; 916 unsigned int bbt_options; 917 918 int page_shift; 919 int phys_erase_shift; 920 int bbt_erase_shift; 921 int chip_shift; 922 int numchips; 923 uint64_t chipsize; 924 int pagemask; 925 int pagebuf; 926 unsigned int pagebuf_bitflips; 927 int subpagesize; 928 uint8_t bits_per_cell; 929 uint16_t ecc_strength_ds; 930 uint16_t ecc_step_ds; 931 int onfi_timing_mode_default; 932 int badblockpos; 933 int badblockbits; 934 935 int onfi_version; 936 int jedec_version; 937 struct nand_onfi_params onfi_params; 938 struct nand_jedec_params jedec_params; 939 940 struct nand_data_interface *data_interface; 941 942 int read_retries; 943 944 flstate_t state; 945 946 uint8_t *oob_poi; 947 struct nand_hw_control *controller; 948 struct nand_ecclayout *ecclayout; 949 950 struct nand_ecc_ctrl ecc; 951 struct nand_buffers *buffers; 952 unsigned long buf_align; 953 struct nand_hw_control hwcontrol; 954 955 uint8_t *bbt; 956 struct nand_bbt_descr *bbt_td; 957 struct nand_bbt_descr *bbt_md; 958 959 struct nand_bbt_descr *badblock_pattern; 960 961 void *priv; 962 }; 963 964 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 965 { 966 return container_of(mtd, struct nand_chip, mtd); 967 } 968 969 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 970 { 971 return &chip->mtd; 972 } 973 974 static inline void *nand_get_controller_data(struct nand_chip *chip) 975 { 976 return chip->priv; 977 } 978 979 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 980 { 981 chip->priv = priv; 982 } 983 984 /* 985 * NAND Flash Manufacturer ID Codes 986 */ 987 #define NAND_MFR_TOSHIBA 0x98 988 #define NAND_MFR_SAMSUNG 0xec 989 #define NAND_MFR_FUJITSU 0x04 990 #define NAND_MFR_NATIONAL 0x8f 991 #define NAND_MFR_RENESAS 0x07 992 #define NAND_MFR_STMICRO 0x20 993 #define NAND_MFR_HYNIX 0xad 994 #define NAND_MFR_MICRON 0x2c 995 #define NAND_MFR_AMD 0x01 996 #define NAND_MFR_MACRONIX 0xc2 997 #define NAND_MFR_EON 0x92 998 #define NAND_MFR_SANDISK 0x45 999 #define NAND_MFR_INTEL 0x89 1000 #define NAND_MFR_ATO 0x9b 1001 1002 /* The maximum expected count of bytes in the NAND ID sequence */ 1003 #define NAND_MAX_ID_LEN 8 1004 1005 /* 1006 * A helper for defining older NAND chips where the second ID byte fully 1007 * defined the chip, including the geometry (chip size, eraseblock size, page 1008 * size). All these chips have 512 bytes NAND page size. 1009 */ 1010 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1011 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1012 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1013 1014 /* 1015 * A helper for defining newer chips which report their page size and 1016 * eraseblock size via the extended ID bytes. 1017 * 1018 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1019 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1020 * device ID now only represented a particular total chip size (and voltage, 1021 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1022 * using the same device ID. 1023 */ 1024 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1025 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1026 .options = (opts) } 1027 1028 #define NAND_ECC_INFO(_strength, _step) \ 1029 { .strength_ds = (_strength), .step_ds = (_step) } 1030 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1031 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1032 1033 /** 1034 * struct nand_flash_dev - NAND Flash Device ID Structure 1035 * @name: a human-readable name of the NAND chip 1036 * @dev_id: the device ID (the second byte of the full chip ID array) 1037 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1038 * memory address as @id[0]) 1039 * @dev_id: device ID part of the full chip ID array (refers the same memory 1040 * address as @id[1]) 1041 * @id: full device ID array 1042 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1043 * well as the eraseblock size) is determined from the extended NAND 1044 * chip ID array) 1045 * @chipsize: total chip size in MiB 1046 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1047 * @options: stores various chip bit options 1048 * @id_len: The valid length of the @id. 1049 * @oobsize: OOB size 1050 * @ecc: ECC correctability and step information from the datasheet. 1051 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1052 * @ecc_strength_ds in nand_chip{}. 1053 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1054 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1055 * For example, the "4bit ECC for each 512Byte" can be set with 1056 * NAND_ECC_INFO(4, 512). 1057 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1058 * reset. Should be deduced from timings described 1059 * in the datasheet. 1060 * 1061 */ 1062 struct nand_flash_dev { 1063 char *name; 1064 union { 1065 struct { 1066 uint8_t mfr_id; 1067 uint8_t dev_id; 1068 }; 1069 uint8_t id[NAND_MAX_ID_LEN]; 1070 }; 1071 unsigned int pagesize; 1072 unsigned int chipsize; 1073 unsigned int erasesize; 1074 unsigned int options; 1075 uint16_t id_len; 1076 uint16_t oobsize; 1077 struct { 1078 uint16_t strength_ds; 1079 uint16_t step_ds; 1080 } ecc; 1081 int onfi_timing_mode_default; 1082 }; 1083 1084 /** 1085 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 1086 * @name: Manufacturer name 1087 * @id: manufacturer ID code of device. 1088 */ 1089 struct nand_manufacturers { 1090 int id; 1091 char *name; 1092 }; 1093 1094 extern struct nand_flash_dev nand_flash_ids[]; 1095 extern struct nand_manufacturers nand_manuf_ids[]; 1096 1097 int nand_default_bbt(struct mtd_info *mtd); 1098 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1099 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1100 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1101 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1102 int allowbbt); 1103 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1104 size_t *retlen, uint8_t *buf); 1105 1106 /* 1107 * Constants for oob configuration 1108 */ 1109 #define NAND_SMALL_BADBLOCK_POS 5 1110 #define NAND_LARGE_BADBLOCK_POS 0 1111 1112 /** 1113 * struct platform_nand_chip - chip level device structure 1114 * @nr_chips: max. number of chips to scan for 1115 * @chip_offset: chip number offset 1116 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1117 * @partitions: mtd partition list 1118 * @chip_delay: R/B delay value in us 1119 * @options: Option flags, e.g. 16bit buswidth 1120 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1121 * @part_probe_types: NULL-terminated array of probe types 1122 */ 1123 struct platform_nand_chip { 1124 int nr_chips; 1125 int chip_offset; 1126 int nr_partitions; 1127 struct mtd_partition *partitions; 1128 int chip_delay; 1129 unsigned int options; 1130 unsigned int bbt_options; 1131 const char **part_probe_types; 1132 }; 1133 1134 /* Keep gcc happy */ 1135 struct platform_device; 1136 1137 /** 1138 * struct platform_nand_ctrl - controller level device structure 1139 * @probe: platform specific function to probe/setup hardware 1140 * @remove: platform specific function to remove/teardown hardware 1141 * @hwcontrol: platform specific hardware control structure 1142 * @dev_ready: platform specific function to read ready/busy pin 1143 * @select_chip: platform specific chip select function 1144 * @cmd_ctrl: platform specific function for controlling 1145 * ALE/CLE/nCE. Also used to write command and address 1146 * @write_buf: platform specific function for write buffer 1147 * @read_buf: platform specific function for read buffer 1148 * @read_byte: platform specific function to read one byte from chip 1149 * @priv: private data to transport driver specific settings 1150 * 1151 * All fields are optional and depend on the hardware driver requirements 1152 */ 1153 struct platform_nand_ctrl { 1154 int (*probe)(struct platform_device *pdev); 1155 void (*remove)(struct platform_device *pdev); 1156 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1157 int (*dev_ready)(struct mtd_info *mtd); 1158 void (*select_chip)(struct mtd_info *mtd, int chip); 1159 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1160 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1161 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1162 unsigned char (*read_byte)(struct mtd_info *mtd); 1163 void *priv; 1164 }; 1165 1166 /** 1167 * struct platform_nand_data - container structure for platform-specific data 1168 * @chip: chip level chip structure 1169 * @ctrl: controller level device structure 1170 */ 1171 struct platform_nand_data { 1172 struct platform_nand_chip chip; 1173 struct platform_nand_ctrl ctrl; 1174 }; 1175 1176 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 1177 /* return the supported features. */ 1178 static inline int onfi_feature(struct nand_chip *chip) 1179 { 1180 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1181 } 1182 1183 /* return the supported asynchronous timing mode. */ 1184 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1185 { 1186 if (!chip->onfi_version) 1187 return ONFI_TIMING_MODE_UNKNOWN; 1188 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1189 } 1190 1191 /* return the supported synchronous timing mode. */ 1192 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1193 { 1194 if (!chip->onfi_version) 1195 return ONFI_TIMING_MODE_UNKNOWN; 1196 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1197 } 1198 #else 1199 static inline int onfi_feature(struct nand_chip *chip) 1200 { 1201 return 0; 1202 } 1203 1204 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1205 { 1206 return ONFI_TIMING_MODE_UNKNOWN; 1207 } 1208 1209 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1210 { 1211 return ONFI_TIMING_MODE_UNKNOWN; 1212 } 1213 #endif 1214 1215 int onfi_init_data_interface(struct nand_chip *chip, 1216 struct nand_data_interface *iface, 1217 enum nand_data_interface_type type, 1218 int timing_mode); 1219 1220 /* 1221 * Check if it is a SLC nand. 1222 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1223 * We do not distinguish the MLC and TLC now. 1224 */ 1225 static inline bool nand_is_slc(struct nand_chip *chip) 1226 { 1227 return chip->bits_per_cell == 1; 1228 } 1229 1230 /** 1231 * Check if the opcode's address should be sent only on the lower 8 bits 1232 * @command: opcode to check 1233 */ 1234 static inline int nand_opcode_8bits(unsigned int command) 1235 { 1236 switch (command) { 1237 case NAND_CMD_READID: 1238 case NAND_CMD_PARAM: 1239 case NAND_CMD_GET_FEATURES: 1240 case NAND_CMD_SET_FEATURES: 1241 return 1; 1242 default: 1243 break; 1244 } 1245 return 0; 1246 } 1247 1248 /* return the supported JEDEC features. */ 1249 static inline int jedec_feature(struct nand_chip *chip) 1250 { 1251 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1252 : 0; 1253 } 1254 1255 /* Standard NAND functions from nand_base.c */ 1256 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1257 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1258 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1259 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1260 uint8_t nand_read_byte(struct mtd_info *mtd); 1261 1262 /* get timing characteristics from ONFI timing mode. */ 1263 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1264 /* get data interface from ONFI timing mode 0, used after reset. */ 1265 const struct nand_data_interface *nand_get_default_data_interface(void); 1266 1267 int nand_check_erased_ecc_chunk(void *data, int datalen, 1268 void *ecc, int ecclen, 1269 void *extraoob, int extraooblen, 1270 int threshold); 1271 1272 int nand_check_ecc_caps(struct nand_chip *chip, 1273 const struct nand_ecc_caps *caps, int oobavail); 1274 1275 int nand_match_ecc_req(struct nand_chip *chip, 1276 const struct nand_ecc_caps *caps, int oobavail); 1277 1278 int nand_maximize_ecc(struct nand_chip *chip, 1279 const struct nand_ecc_caps *caps, int oobavail); 1280 1281 /* Reset and initialize a NAND device */ 1282 int nand_reset(struct nand_chip *chip, int chipnr); 1283 #endif /* __LINUX_MTD_RAWNAND_H */ 1284