1 /* 2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> 3 * Rohit Choraria <rohitkc@ti.com> 4 * 5 * (C) Copyright 2013 Andreas Bießmann <andreas@biessmann.org> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #ifndef __ASM_OMAP_GPMC_H 10 #define __ASM_OMAP_GPMC_H 11 12 #define GPMC_BUF_EMPTY 0 13 #define GPMC_BUF_FULL 1 14 #define GPMC_MAX_SECTORS 8 15 16 enum omap_ecc { 17 /* 1-bit ECC calculation by Software, Error detection by Software */ 18 OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ 19 /* 1-bit ECC calculation by GPMC, Error detection by Software */ 20 /* ECC layout compatible to legacy ROMCODE. */ 21 OMAP_ECC_HAM1_CODE_HW, 22 /* 4-bit ECC calculation by GPMC, Error detection by Software */ 23 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, 24 /* 4-bit ECC calculation by GPMC, Error detection by ELM */ 25 OMAP_ECC_BCH4_CODE_HW, 26 /* 8-bit ECC calculation by GPMC, Error detection by Software */ 27 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, 28 /* 8-bit ECC calculation by GPMC, Error detection by ELM */ 29 OMAP_ECC_BCH8_CODE_HW, 30 /* 16-bit ECC calculation by GPMC, Error detection by ELM */ 31 OMAP_ECC_BCH16_CODE_HW, 32 }; 33 34 struct gpmc_cs { 35 u32 config1; /* 0x00 */ 36 u32 config2; /* 0x04 */ 37 u32 config3; /* 0x08 */ 38 u32 config4; /* 0x0C */ 39 u32 config5; /* 0x10 */ 40 u32 config6; /* 0x14 */ 41 u32 config7; /* 0x18 */ 42 u32 nand_cmd; /* 0x1C */ 43 u32 nand_adr; /* 0x20 */ 44 u32 nand_dat; /* 0x24 */ 45 u8 res[8]; /* blow up to 0x30 byte */ 46 }; 47 48 struct bch_res_0_3 { 49 u32 bch_result_x[4]; 50 }; 51 52 struct bch_res_4_6 { 53 u32 bch_result_x[3]; 54 }; 55 56 struct gpmc { 57 u8 res1[0x10]; 58 u32 sysconfig; /* 0x10 */ 59 u8 res2[0x4]; 60 u32 irqstatus; /* 0x18 */ 61 u32 irqenable; /* 0x1C */ 62 u8 res3[0x20]; 63 u32 timeout_control; /* 0x40 */ 64 u8 res4[0xC]; 65 u32 config; /* 0x50 */ 66 u32 status; /* 0x54 */ 67 u8 res5[0x8]; /* 0x58 */ 68 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 69 u32 prefetch_config1; /* 0x1E0 */ 70 u32 prefetch_config2; /* 0x1E4 */ 71 u32 res6; /* 0x1E8 */ 72 u32 prefetch_control; /* 0x1EC */ 73 u32 prefetch_status; /* 0x1F0 */ 74 u32 ecc_config; /* 0x1F4 */ 75 u32 ecc_control; /* 0x1F8 */ 76 u32 ecc_size_config; /* 0x1FC */ 77 u32 ecc1_result; /* 0x200 */ 78 u32 ecc2_result; /* 0x204 */ 79 u32 ecc3_result; /* 0x208 */ 80 u32 ecc4_result; /* 0x20C */ 81 u32 ecc5_result; /* 0x210 */ 82 u32 ecc6_result; /* 0x214 */ 83 u32 ecc7_result; /* 0x218 */ 84 u32 ecc8_result; /* 0x21C */ 85 u32 ecc9_result; /* 0x220 */ 86 u8 res7[12]; /* 0x224 */ 87 u32 testmomde_ctrl; /* 0x230 */ 88 u8 res8[12]; /* 0x234 */ 89 struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */ 90 u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */ 91 struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */ 92 }; 93 94 /* Used for board specific gpmc initialization */ 95 extern const struct gpmc *gpmc_cfg; 96 extern char gpmc_cs0_flash; 97 98 #endif /* __ASM_OMAP_GPMC_H */ 99