xref: /openbmc/u-boot/include/linux/mtd/ndfc.h (revision ad5b5801)
1 /*
2  *  linux/include/linux/mtd/ndfc.h
3  *
4  *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  *  Info:
11  *   Contains defines, datastructures for ndfc nand controller
12  *
13  */
14 #ifndef __LINUX_MTD_NDFC_H
15 #define __LINUX_MTD_NDFC_H
16 
17 /* NDFC Register definitions */
18 #define NDFC_CMD		0x00
19 #define NDFC_ALE		0x04
20 #define NDFC_DATA		0x08
21 #define NDFC_ECC		0x10
22 #define NDFC_BCFG0		0x30
23 #define NDFC_BCFG1		0x34
24 #define NDFC_BCFG2		0x38
25 #define NDFC_BCFG3		0x3c
26 #define NDFC_CCR		0x40
27 #define NDFC_STAT		0x44
28 #define NDFC_HWCTL		0x48
29 #define NDFC_REVID		0x50
30 
31 #define NDFC_STAT_IS_READY	0x01000000
32 
33 #define NDFC_CCR_RESET_CE	0x80000000 /* CE Reset */
34 #define NDFC_CCR_RESET_ECC	0x40000000 /* ECC Reset */
35 #define NDFC_CCR_RIE		0x20000000 /* Interrupt Enable on Device Rdy */
36 #define NDFC_CCR_REN		0x10000000 /* Enable wait for Rdy in LinearR */
37 #define NDFC_CCR_ROMEN		0x08000000 /* Enable ROM In LinearR */
38 #define NDFC_CCR_ARE		0x04000000 /* Auto-Read Enable */
39 #define NDFC_CCR_BS(x)		(((x) & 0x3) << 24) /* Select Bank on CE[x] */
40 #define NDFC_CCR_BS_MASK	0x03000000 /* Select Bank */
41 #define NDFC_CCR_ARAC0		0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
42 #define NDFC_CCR_ARAC1		0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
43 #define NDFC_CCR_ARAC2		0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
44 #define NDFC_CCR_ARAC3		0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
45 #define NDFC_CCR_ARAC_MASK	0x00003000 /* Auto-Read mode Addr Cycles */
46 #define NDFC_CCR_RPG		0x0000C000 /* Auto-Read Page */
47 #define NDFC_CCR_EBCC		0x00000004 /* EBC Configuration Completed */
48 #define NDFC_CCR_DHC		0x00000002 /* Direct Hardware Control Enable */
49 
50 #define NDFC_BxCFG_EN		0x80000000 /* Bank Enable */
51 #define NDFC_BxCFG_CED		0x40000000 /* nCE Style */
52 #define NDFC_BxCFG_SZ_MASK	0x08000000 /* Bank Size */
53 #define NDFC_BxCFG_SZ_8BIT	0x00000000 /* 8bit */
54 #define NDFC_BxCFG_SZ_16BIT	0x08000000 /* 16bit */
55 
56 #define NDFC_MAX_BANKS		4
57 
58 struct ndfc_controller_settings {
59 	uint32_t	ccr_settings;
60 	uint64_t	ndfc_erpn;
61 };
62 
63 struct ndfc_chip_settings {
64 	uint32_t	bank_settings;
65 };
66 
67 #endif
68