1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_NAND_H 17 #define __LINUX_MTD_NAND_H 18 19 #ifndef __UBOOT__ 20 #include <linux/wait.h> 21 #include <linux/spinlock.h> 22 #include <linux/mtd/mtd.h> 23 #include <linux/mtd/flashchip.h> 24 #include <linux/mtd/bbm.h> 25 #else 26 #include "config.h" 27 28 #include "linux/compat.h" 29 #include "linux/mtd/mtd.h" 30 #include "linux/mtd/flashchip.h" 31 #include "linux/mtd/bbm.h" 32 #endif 33 34 struct mtd_info; 35 struct nand_flash_dev; 36 /* Scan and identify a NAND device */ 37 extern int nand_scan(struct mtd_info *mtd, int max_chips); 38 /* 39 * Separate phases of nand_scan(), allowing board driver to intervene 40 * and override command or ECC setup according to flash type. 41 */ 42 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 43 struct nand_flash_dev *table); 44 extern int nand_scan_tail(struct mtd_info *mtd); 45 46 /* Free resources held by the NAND device */ 47 extern void nand_release(struct mtd_info *mtd); 48 49 /* Internal helper for board drivers which need to override command function */ 50 extern void nand_wait_ready(struct mtd_info *mtd); 51 52 #ifndef __UBOOT__ 53 /* locks all blocks present in the device */ 54 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 55 56 /* unlocks specified locked blocks */ 57 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 58 59 /* The maximum number of NAND chips in an array */ 60 #define NAND_MAX_CHIPS 8 61 #else 62 /* 63 * This constant declares the max. oobsize / page, which 64 * is supported now. If you add a chip with bigger oobsize/page 65 * adjust this accordingly. 66 */ 67 #define NAND_MAX_OOBSIZE 744 68 #define NAND_MAX_PAGESIZE 8192 69 #endif 70 71 /* 72 * Constants for hardware specific CLE/ALE/NCE function 73 * 74 * These are bits which can be or'ed to set/clear multiple 75 * bits in one go. 76 */ 77 /* Select the chip by setting nCE to low */ 78 #define NAND_NCE 0x01 79 /* Select the command latch by setting CLE to high */ 80 #define NAND_CLE 0x02 81 /* Select the address latch by setting ALE to high */ 82 #define NAND_ALE 0x04 83 84 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 85 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 86 #define NAND_CTRL_CHANGE 0x80 87 88 /* 89 * Standard NAND flash commands 90 */ 91 #define NAND_CMD_READ0 0 92 #define NAND_CMD_READ1 1 93 #define NAND_CMD_RNDOUT 5 94 #define NAND_CMD_PAGEPROG 0x10 95 #define NAND_CMD_READOOB 0x50 96 #define NAND_CMD_ERASE1 0x60 97 #define NAND_CMD_STATUS 0x70 98 #define NAND_CMD_SEQIN 0x80 99 #define NAND_CMD_RNDIN 0x85 100 #define NAND_CMD_READID 0x90 101 #define NAND_CMD_ERASE2 0xd0 102 #define NAND_CMD_PARAM 0xec 103 #define NAND_CMD_GET_FEATURES 0xee 104 #define NAND_CMD_SET_FEATURES 0xef 105 #define NAND_CMD_RESET 0xff 106 107 #define NAND_CMD_LOCK 0x2a 108 #define NAND_CMD_UNLOCK1 0x23 109 #define NAND_CMD_UNLOCK2 0x24 110 111 /* Extended commands for large page devices */ 112 #define NAND_CMD_READSTART 0x30 113 #define NAND_CMD_RNDOUTSTART 0xE0 114 #define NAND_CMD_CACHEDPROG 0x15 115 116 /* Extended commands for AG-AND device */ 117 /* 118 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 119 * there is no way to distinguish that from NAND_CMD_READ0 120 * until the remaining sequence of commands has been completed 121 * so add a high order bit and mask it off in the command. 122 */ 123 #define NAND_CMD_DEPLETE1 0x100 124 #define NAND_CMD_DEPLETE2 0x38 125 #define NAND_CMD_STATUS_MULTI 0x71 126 #define NAND_CMD_STATUS_ERROR 0x72 127 /* multi-bank error status (banks 0-3) */ 128 #define NAND_CMD_STATUS_ERROR0 0x73 129 #define NAND_CMD_STATUS_ERROR1 0x74 130 #define NAND_CMD_STATUS_ERROR2 0x75 131 #define NAND_CMD_STATUS_ERROR3 0x76 132 #define NAND_CMD_STATUS_RESET 0x7f 133 #define NAND_CMD_STATUS_CLEAR 0xff 134 135 #define NAND_CMD_NONE -1 136 137 /* Status bits */ 138 #define NAND_STATUS_FAIL 0x01 139 #define NAND_STATUS_FAIL_N1 0x02 140 #define NAND_STATUS_TRUE_READY 0x20 141 #define NAND_STATUS_READY 0x40 142 #define NAND_STATUS_WP 0x80 143 144 /* 145 * Constants for ECC_MODES 146 */ 147 typedef enum { 148 NAND_ECC_NONE, 149 NAND_ECC_SOFT, 150 NAND_ECC_HW, 151 NAND_ECC_HW_SYNDROME, 152 NAND_ECC_HW_OOB_FIRST, 153 NAND_ECC_SOFT_BCH, 154 } nand_ecc_modes_t; 155 156 /* 157 * Constants for Hardware ECC 158 */ 159 /* Reset Hardware ECC for read */ 160 #define NAND_ECC_READ 0 161 /* Reset Hardware ECC for write */ 162 #define NAND_ECC_WRITE 1 163 /* Enable Hardware ECC before syndrome is read back from flash */ 164 #define NAND_ECC_READSYN 2 165 166 /* Bit mask for flags passed to do_nand_read_ecc */ 167 #define NAND_GET_DEVICE 0x80 168 169 170 /* 171 * Option constants for bizarre disfunctionality and real 172 * features. 173 */ 174 /* Buswidth is 16 bit */ 175 #define NAND_BUSWIDTH_16 0x00000002 176 /* Device supports partial programming without padding */ 177 #define NAND_NO_PADDING 0x00000004 178 /* Chip has cache program function */ 179 #define NAND_CACHEPRG 0x00000008 180 /* Chip has copy back function */ 181 #define NAND_COPYBACK 0x00000010 182 /* 183 * Chip requires ready check on read (for auto-incremented sequential read). 184 * True only for small page devices; large page devices do not support 185 * autoincrement. 186 */ 187 #define NAND_NEED_READRDY 0x00000100 188 189 /* Chip does not allow subpage writes */ 190 #define NAND_NO_SUBPAGE_WRITE 0x00000200 191 192 /* Device is one of 'new' xD cards that expose fake nand command set */ 193 #define NAND_BROKEN_XD 0x00000400 194 195 /* Device behaves just like nand, but is readonly */ 196 #define NAND_ROM 0x00000800 197 198 /* Device supports subpage reads */ 199 #define NAND_SUBPAGE_READ 0x00001000 200 201 /* Options valid for Samsung large page devices */ 202 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 203 204 /* Macros to identify the above */ 205 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 206 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 207 208 /* Non chip related options */ 209 /* This option skips the bbt scan during initialization. */ 210 #define NAND_SKIP_BBTSCAN 0x00010000 211 /* 212 * This option is defined if the board driver allocates its own buffers 213 * (e.g. because it needs them DMA-coherent). 214 */ 215 #define NAND_OWN_BUFFERS 0x00020000 216 /* Chip may not exist, so silence any errors in scan */ 217 #define NAND_SCAN_SILENT_NODEV 0x00040000 218 /* 219 * Autodetect nand buswidth with readid/onfi. 220 * This suppose the driver will configure the hardware in 8 bits mode 221 * when calling nand_scan_ident, and update its configuration 222 * before calling nand_scan_tail. 223 */ 224 #define NAND_BUSWIDTH_AUTO 0x00080000 225 226 /* Options set by nand scan */ 227 /* bbt has already been read */ 228 #define NAND_BBT_SCANNED 0x40000000 229 /* Nand scan has allocated controller struct */ 230 #define NAND_CONTROLLER_ALLOC 0x80000000 231 232 /* Cell info constants */ 233 #define NAND_CI_CHIPNR_MSK 0x03 234 #define NAND_CI_CELLTYPE_MSK 0x0C 235 #define NAND_CI_CELLTYPE_SHIFT 2 236 237 /* Keep gcc happy */ 238 struct nand_chip; 239 240 /* ONFI features */ 241 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 242 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 243 244 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 245 #define ONFI_TIMING_MODE_0 (1 << 0) 246 #define ONFI_TIMING_MODE_1 (1 << 1) 247 #define ONFI_TIMING_MODE_2 (1 << 2) 248 #define ONFI_TIMING_MODE_3 (1 << 3) 249 #define ONFI_TIMING_MODE_4 (1 << 4) 250 #define ONFI_TIMING_MODE_5 (1 << 5) 251 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 252 253 /* ONFI feature address */ 254 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 255 256 /* Vendor-specific feature address (Micron) */ 257 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 258 259 /* ONFI subfeature parameters length */ 260 #define ONFI_SUBFEATURE_PARAM_LEN 4 261 262 /* ONFI optional commands SET/GET FEATURES supported? */ 263 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 264 265 struct nand_onfi_params { 266 /* rev info and features block */ 267 /* 'O' 'N' 'F' 'I' */ 268 u8 sig[4]; 269 __le16 revision; 270 __le16 features; 271 __le16 opt_cmd; 272 u8 reserved0[2]; 273 __le16 ext_param_page_length; /* since ONFI 2.1 */ 274 u8 num_of_param_pages; /* since ONFI 2.1 */ 275 u8 reserved1[17]; 276 277 /* manufacturer information block */ 278 char manufacturer[12]; 279 char model[20]; 280 u8 jedec_id; 281 __le16 date_code; 282 u8 reserved2[13]; 283 284 /* memory organization block */ 285 __le32 byte_per_page; 286 __le16 spare_bytes_per_page; 287 __le32 data_bytes_per_ppage; 288 __le16 spare_bytes_per_ppage; 289 __le32 pages_per_block; 290 __le32 blocks_per_lun; 291 u8 lun_count; 292 u8 addr_cycles; 293 u8 bits_per_cell; 294 __le16 bb_per_lun; 295 __le16 block_endurance; 296 u8 guaranteed_good_blocks; 297 __le16 guaranteed_block_endurance; 298 u8 programs_per_page; 299 u8 ppage_attr; 300 u8 ecc_bits; 301 u8 interleaved_bits; 302 u8 interleaved_ops; 303 u8 reserved3[13]; 304 305 /* electrical parameter block */ 306 u8 io_pin_capacitance_max; 307 __le16 async_timing_mode; 308 __le16 program_cache_timing_mode; 309 __le16 t_prog; 310 __le16 t_bers; 311 __le16 t_r; 312 __le16 t_ccs; 313 __le16 src_sync_timing_mode; 314 __le16 src_ssync_features; 315 __le16 clk_pin_capacitance_typ; 316 __le16 io_pin_capacitance_typ; 317 __le16 input_pin_capacitance_typ; 318 u8 input_pin_capacitance_max; 319 u8 driver_strength_support; 320 __le16 t_int_r; 321 __le16 t_ald; 322 u8 reserved4[7]; 323 324 /* vendor */ 325 __le16 vendor_revision; 326 u8 vendor[88]; 327 328 __le16 crc; 329 } __packed; 330 331 #define ONFI_CRC_BASE 0x4F4E 332 333 /* Extended ECC information Block Definition (since ONFI 2.1) */ 334 struct onfi_ext_ecc_info { 335 u8 ecc_bits; 336 u8 codeword_size; 337 __le16 bb_per_lun; 338 __le16 block_endurance; 339 u8 reserved[2]; 340 } __packed; 341 342 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 343 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 344 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 345 struct onfi_ext_section { 346 u8 type; 347 u8 length; 348 } __packed; 349 350 #define ONFI_EXT_SECTION_MAX 8 351 352 /* Extended Parameter Page Definition (since ONFI 2.1) */ 353 struct onfi_ext_param_page { 354 __le16 crc; 355 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 356 u8 reserved0[10]; 357 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 358 359 /* 360 * The actual size of the Extended Parameter Page is in 361 * @ext_param_page_length of nand_onfi_params{}. 362 * The following are the variable length sections. 363 * So we do not add any fields below. Please see the ONFI spec. 364 */ 365 } __packed; 366 367 struct nand_onfi_vendor_micron { 368 u8 two_plane_read; 369 u8 read_cache; 370 u8 read_unique_id; 371 u8 dq_imped; 372 u8 dq_imped_num_settings; 373 u8 dq_imped_feat_addr; 374 u8 rb_pulldown_strength; 375 u8 rb_pulldown_strength_feat_addr; 376 u8 rb_pulldown_strength_num_settings; 377 u8 otp_mode; 378 u8 otp_page_start; 379 u8 otp_data_prot_addr; 380 u8 otp_num_pages; 381 u8 otp_feat_addr; 382 u8 read_retry_options; 383 u8 reserved[72]; 384 u8 param_revision; 385 } __packed; 386 387 struct jedec_ecc_info { 388 u8 ecc_bits; 389 u8 codeword_size; 390 __le16 bb_per_lun; 391 __le16 block_endurance; 392 u8 reserved[2]; 393 } __packed; 394 395 /* JEDEC features */ 396 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 397 398 struct nand_jedec_params { 399 /* rev info and features block */ 400 /* 'J' 'E' 'S' 'D' */ 401 u8 sig[4]; 402 __le16 revision; 403 __le16 features; 404 u8 opt_cmd[3]; 405 __le16 sec_cmd; 406 u8 num_of_param_pages; 407 u8 reserved0[18]; 408 409 /* manufacturer information block */ 410 char manufacturer[12]; 411 char model[20]; 412 u8 jedec_id[6]; 413 u8 reserved1[10]; 414 415 /* memory organization block */ 416 __le32 byte_per_page; 417 __le16 spare_bytes_per_page; 418 u8 reserved2[6]; 419 __le32 pages_per_block; 420 __le32 blocks_per_lun; 421 u8 lun_count; 422 u8 addr_cycles; 423 u8 bits_per_cell; 424 u8 programs_per_page; 425 u8 multi_plane_addr; 426 u8 multi_plane_op_attr; 427 u8 reserved3[38]; 428 429 /* electrical parameter block */ 430 __le16 async_sdr_speed_grade; 431 __le16 toggle_ddr_speed_grade; 432 __le16 sync_ddr_speed_grade; 433 u8 async_sdr_features; 434 u8 toggle_ddr_features; 435 u8 sync_ddr_features; 436 __le16 t_prog; 437 __le16 t_bers; 438 __le16 t_r; 439 __le16 t_r_multi_plane; 440 __le16 t_ccs; 441 __le16 io_pin_capacitance_typ; 442 __le16 input_pin_capacitance_typ; 443 __le16 clk_pin_capacitance_typ; 444 u8 driver_strength_support; 445 __le16 t_ald; 446 u8 reserved4[36]; 447 448 /* ECC and endurance block */ 449 u8 guaranteed_good_blocks; 450 __le16 guaranteed_block_endurance; 451 struct jedec_ecc_info ecc_info[4]; 452 u8 reserved5[29]; 453 454 /* reserved */ 455 u8 reserved6[148]; 456 457 /* vendor */ 458 __le16 vendor_rev_num; 459 u8 reserved7[88]; 460 461 /* CRC for Parameter Page */ 462 __le16 crc; 463 } __packed; 464 465 /** 466 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 467 * @lock: protection lock 468 * @active: the mtd device which holds the controller currently 469 * @wq: wait queue to sleep on if a NAND operation is in 470 * progress used instead of the per chip wait queue 471 * when a hw controller is available. 472 */ 473 struct nand_hw_control { 474 spinlock_t lock; 475 struct nand_chip *active; 476 #ifndef __UBOOT__ 477 wait_queue_head_t wq; 478 #endif 479 }; 480 481 /** 482 * struct nand_ecc_ctrl - Control structure for ECC 483 * @mode: ECC mode 484 * @steps: number of ECC steps per page 485 * @size: data bytes per ECC step 486 * @bytes: ECC bytes per step 487 * @strength: max number of correctible bits per ECC step 488 * @total: total number of ECC bytes per page 489 * @prepad: padding information for syndrome based ECC generators 490 * @postpad: padding information for syndrome based ECC generators 491 * @layout: ECC layout control struct pointer 492 * @priv: pointer to private ECC control data 493 * @hwctl: function to control hardware ECC generator. Must only 494 * be provided if an hardware ECC is available 495 * @calculate: function for ECC calculation or readback from ECC hardware 496 * @correct: function for ECC correction, matching to ECC generator (sw/hw) 497 * @read_page_raw: function to read a raw page without ECC 498 * @write_page_raw: function to write a raw page without ECC 499 * @read_page: function to read a page according to the ECC generator 500 * requirements; returns maximum number of bitflips corrected in 501 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 502 * @read_subpage: function to read parts of the page covered by ECC; 503 * returns same as read_page() 504 * @write_subpage: function to write parts of the page covered by ECC. 505 * @write_page: function to write a page according to the ECC generator 506 * requirements. 507 * @write_oob_raw: function to write chip OOB data without ECC 508 * @read_oob_raw: function to read chip OOB data without ECC 509 * @read_oob: function to read chip OOB data 510 * @write_oob: function to write chip OOB data 511 */ 512 struct nand_ecc_ctrl { 513 nand_ecc_modes_t mode; 514 int steps; 515 int size; 516 int bytes; 517 int total; 518 int strength; 519 int prepad; 520 int postpad; 521 struct nand_ecclayout *layout; 522 void *priv; 523 void (*hwctl)(struct mtd_info *mtd, int mode); 524 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 525 uint8_t *ecc_code); 526 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 527 uint8_t *calc_ecc); 528 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 529 uint8_t *buf, int oob_required, int page); 530 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 531 const uint8_t *buf, int oob_required); 532 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 533 uint8_t *buf, int oob_required, int page); 534 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 535 uint32_t offs, uint32_t len, uint8_t *buf, int page); 536 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 537 uint32_t offset, uint32_t data_len, 538 const uint8_t *data_buf, int oob_required); 539 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 540 const uint8_t *buf, int oob_required); 541 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 542 int page); 543 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 544 int page); 545 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 546 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 547 int page); 548 }; 549 550 /** 551 * struct nand_buffers - buffer structure for read/write 552 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 553 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 554 * @databuf: buffer pointer for data, size is (page size + oobsize). 555 * 556 * Do not change the order of buffers. databuf and oobrbuf must be in 557 * consecutive order. 558 */ 559 struct nand_buffers { 560 #ifndef __UBOOT__ 561 uint8_t *ecccalc; 562 uint8_t *ecccode; 563 uint8_t *databuf; 564 #else 565 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 566 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 567 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 568 ARCH_DMA_MINALIGN)]; 569 #endif 570 }; 571 572 /** 573 * struct nand_chip - NAND Private Flash Chip Data 574 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 575 * flash device 576 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 577 * flash device. 578 * @read_byte: [REPLACEABLE] read one byte from the chip 579 * @read_word: [REPLACEABLE] read one word from the chip 580 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 581 * low 8 I/O lines 582 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 583 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 584 * @select_chip: [REPLACEABLE] select chip nr 585 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 586 * @block_markbad: [REPLACEABLE] mark a block bad 587 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 588 * ALE/CLE/nCE. Also used to write command and address 589 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting 590 * mtd->oobsize, mtd->writesize and so on. 591 * @id_data contains the 8 bytes values of NAND_CMD_READID. 592 * Return with the bus width. 593 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 594 * device ready/busy line. If set to NULL no access to 595 * ready/busy is available and the ready/busy information 596 * is read from the chip status register. 597 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 598 * commands to the chip. 599 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 600 * ready. 601 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 602 * setting the read-retry mode. Mostly needed for MLC NAND. 603 * @ecc: [BOARDSPECIFIC] ECC control structure 604 * @buffers: buffer structure for read/write 605 * @hwcontrol: platform-specific hardware control structure 606 * @erase_cmd: [INTERN] erase command write function, selectable due 607 * to AND support. 608 * @scan_bbt: [REPLACEABLE] function to scan bad block table 609 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 610 * data from array to read regs (tR). 611 * @state: [INTERN] the current state of the NAND device 612 * @oob_poi: "poison value buffer," used for laying out OOB data 613 * before writing 614 * @page_shift: [INTERN] number of address bits in a page (column 615 * address bits). 616 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 617 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 618 * @chip_shift: [INTERN] number of address bits in one chip 619 * @options: [BOARDSPECIFIC] various chip options. They can partly 620 * be set to inform nand_scan about special functionality. 621 * See the defines for further explanation. 622 * @bbt_options: [INTERN] bad block specific options. All options used 623 * here must come from bbm.h. By default, these options 624 * will be copied to the appropriate nand_bbt_descr's. 625 * @badblockpos: [INTERN] position of the bad block marker in the oob 626 * area. 627 * @badblockbits: [INTERN] minimum number of set bits in a good block's 628 * bad block marker position; i.e., BBM == 11110111b is 629 * not bad when badblockbits == 7 630 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 631 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 632 * Minimum amount of bit errors per @ecc_step_ds guaranteed 633 * to be correctable. If unknown, set to zero. 634 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 635 * also from the datasheet. It is the recommended ECC step 636 * size, if known; if unknown, set to zero. 637 * @numchips: [INTERN] number of physical chips 638 * @chipsize: [INTERN] the size of one chip for multichip arrays 639 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 640 * @pagebuf: [INTERN] holds the pagenumber which is currently in 641 * data_buf. 642 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 643 * currently in data_buf. 644 * @subpagesize: [INTERN] holds the subpagesize 645 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 646 * non 0 if ONFI supported. 647 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 648 * non 0 if JEDEC supported. 649 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 650 * supported, 0 otherwise. 651 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 652 * supported, 0 otherwise. 653 * @read_retries: [INTERN] the number of read retry modes supported 654 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 655 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 656 * @bbt: [INTERN] bad block table pointer 657 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 658 * lookup. 659 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 660 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 661 * bad block scan. 662 * @controller: [REPLACEABLE] a pointer to a hardware controller 663 * structure which is shared among multiple independent 664 * devices. 665 * @priv: [OPTIONAL] pointer to private chip data 666 * @errstat: [OPTIONAL] hardware specific function to perform 667 * additional error status checks (determine if errors are 668 * correctable). 669 * @write_page: [REPLACEABLE] High-level page write function 670 */ 671 672 struct nand_chip { 673 void __iomem *IO_ADDR_R; 674 void __iomem *IO_ADDR_W; 675 676 uint8_t (*read_byte)(struct mtd_info *mtd); 677 u16 (*read_word)(struct mtd_info *mtd); 678 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 679 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 680 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 681 #ifdef __UBOOT__ 682 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE) 683 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 684 #endif 685 #endif 686 void (*select_chip)(struct mtd_info *mtd, int chip); 687 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 688 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 689 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 690 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, 691 u8 *id_data); 692 int (*dev_ready)(struct mtd_info *mtd); 693 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 694 int page_addr); 695 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 696 void (*erase_cmd)(struct mtd_info *mtd, int page); 697 int (*scan_bbt)(struct mtd_info *mtd); 698 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 699 int status, int page); 700 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 701 uint32_t offset, int data_len, const uint8_t *buf, 702 int oob_required, int page, int cached, int raw); 703 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 704 int feature_addr, uint8_t *subfeature_para); 705 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 706 int feature_addr, uint8_t *subfeature_para); 707 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 708 709 int chip_delay; 710 unsigned int options; 711 unsigned int bbt_options; 712 713 int page_shift; 714 int phys_erase_shift; 715 int bbt_erase_shift; 716 int chip_shift; 717 int numchips; 718 uint64_t chipsize; 719 int pagemask; 720 int pagebuf; 721 unsigned int pagebuf_bitflips; 722 int subpagesize; 723 uint8_t bits_per_cell; 724 uint16_t ecc_strength_ds; 725 uint16_t ecc_step_ds; 726 int badblockpos; 727 int badblockbits; 728 729 int onfi_version; 730 int jedec_version; 731 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 732 struct nand_onfi_params onfi_params; 733 #endif 734 struct nand_jedec_params jedec_params; 735 736 int read_retries; 737 738 flstate_t state; 739 740 uint8_t *oob_poi; 741 struct nand_hw_control *controller; 742 #ifdef __UBOOT__ 743 struct nand_ecclayout *ecclayout; 744 #endif 745 746 struct nand_ecc_ctrl ecc; 747 struct nand_buffers *buffers; 748 struct nand_hw_control hwcontrol; 749 750 uint8_t *bbt; 751 struct nand_bbt_descr *bbt_td; 752 struct nand_bbt_descr *bbt_md; 753 754 struct nand_bbt_descr *badblock_pattern; 755 756 void *priv; 757 }; 758 759 /* 760 * NAND Flash Manufacturer ID Codes 761 */ 762 #define NAND_MFR_TOSHIBA 0x98 763 #define NAND_MFR_SAMSUNG 0xec 764 #define NAND_MFR_FUJITSU 0x04 765 #define NAND_MFR_NATIONAL 0x8f 766 #define NAND_MFR_RENESAS 0x07 767 #define NAND_MFR_STMICRO 0x20 768 #define NAND_MFR_HYNIX 0xad 769 #define NAND_MFR_MICRON 0x2c 770 #define NAND_MFR_AMD 0x01 771 #define NAND_MFR_MACRONIX 0xc2 772 #define NAND_MFR_EON 0x92 773 #define NAND_MFR_SANDISK 0x45 774 #define NAND_MFR_INTEL 0x89 775 776 /* The maximum expected count of bytes in the NAND ID sequence */ 777 #define NAND_MAX_ID_LEN 8 778 779 /* 780 * A helper for defining older NAND chips where the second ID byte fully 781 * defined the chip, including the geometry (chip size, eraseblock size, page 782 * size). All these chips have 512 bytes NAND page size. 783 */ 784 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 785 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 786 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 787 788 /* 789 * A helper for defining newer chips which report their page size and 790 * eraseblock size via the extended ID bytes. 791 * 792 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 793 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 794 * device ID now only represented a particular total chip size (and voltage, 795 * buswidth), and the page size, eraseblock size, and OOB size could vary while 796 * using the same device ID. 797 */ 798 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 799 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 800 .options = (opts) } 801 802 #define NAND_ECC_INFO(_strength, _step) \ 803 { .strength_ds = (_strength), .step_ds = (_step) } 804 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 805 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 806 807 /** 808 * struct nand_flash_dev - NAND Flash Device ID Structure 809 * @name: a human-readable name of the NAND chip 810 * @dev_id: the device ID (the second byte of the full chip ID array) 811 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 812 * memory address as @id[0]) 813 * @dev_id: device ID part of the full chip ID array (refers the same memory 814 * address as @id[1]) 815 * @id: full device ID array 816 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 817 * well as the eraseblock size) is determined from the extended NAND 818 * chip ID array) 819 * @chipsize: total chip size in MiB 820 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 821 * @options: stores various chip bit options 822 * @id_len: The valid length of the @id. 823 * @oobsize: OOB size 824 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 825 * @ecc_strength_ds in nand_chip{}. 826 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 827 * @ecc_step_ds in nand_chip{}, also from the datasheet. 828 * For example, the "4bit ECC for each 512Byte" can be set with 829 * NAND_ECC_INFO(4, 512). 830 */ 831 struct nand_flash_dev { 832 char *name; 833 union { 834 struct { 835 uint8_t mfr_id; 836 uint8_t dev_id; 837 }; 838 uint8_t id[NAND_MAX_ID_LEN]; 839 }; 840 unsigned int pagesize; 841 unsigned int chipsize; 842 unsigned int erasesize; 843 unsigned int options; 844 uint16_t id_len; 845 uint16_t oobsize; 846 struct { 847 uint16_t strength_ds; 848 uint16_t step_ds; 849 } ecc; 850 }; 851 852 /** 853 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 854 * @name: Manufacturer name 855 * @id: manufacturer ID code of device. 856 */ 857 struct nand_manufacturers { 858 int id; 859 char *name; 860 }; 861 862 extern struct nand_flash_dev nand_flash_ids[]; 863 extern struct nand_manufacturers nand_manuf_ids[]; 864 865 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 866 extern int nand_default_bbt(struct mtd_info *mtd); 867 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 868 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 869 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 870 int allowbbt); 871 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 872 size_t *retlen, uint8_t *buf); 873 874 #ifdef __UBOOT__ 875 /* 876 * Constants for oob configuration 877 */ 878 #define NAND_SMALL_BADBLOCK_POS 5 879 #define NAND_LARGE_BADBLOCK_POS 0 880 #endif 881 882 /** 883 * struct platform_nand_chip - chip level device structure 884 * @nr_chips: max. number of chips to scan for 885 * @chip_offset: chip number offset 886 * @nr_partitions: number of partitions pointed to by partitions (or zero) 887 * @partitions: mtd partition list 888 * @chip_delay: R/B delay value in us 889 * @options: Option flags, e.g. 16bit buswidth 890 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 891 * @ecclayout: ECC layout info structure 892 * @part_probe_types: NULL-terminated array of probe types 893 */ 894 struct platform_nand_chip { 895 int nr_chips; 896 int chip_offset; 897 int nr_partitions; 898 struct mtd_partition *partitions; 899 struct nand_ecclayout *ecclayout; 900 int chip_delay; 901 unsigned int options; 902 unsigned int bbt_options; 903 const char **part_probe_types; 904 }; 905 906 /* Keep gcc happy */ 907 struct platform_device; 908 909 /** 910 * struct platform_nand_ctrl - controller level device structure 911 * @probe: platform specific function to probe/setup hardware 912 * @remove: platform specific function to remove/teardown hardware 913 * @hwcontrol: platform specific hardware control structure 914 * @dev_ready: platform specific function to read ready/busy pin 915 * @select_chip: platform specific chip select function 916 * @cmd_ctrl: platform specific function for controlling 917 * ALE/CLE/nCE. Also used to write command and address 918 * @write_buf: platform specific function for write buffer 919 * @read_buf: platform specific function for read buffer 920 * @read_byte: platform specific function to read one byte from chip 921 * @priv: private data to transport driver specific settings 922 * 923 * All fields are optional and depend on the hardware driver requirements 924 */ 925 struct platform_nand_ctrl { 926 int (*probe)(struct platform_device *pdev); 927 void (*remove)(struct platform_device *pdev); 928 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 929 int (*dev_ready)(struct mtd_info *mtd); 930 void (*select_chip)(struct mtd_info *mtd, int chip); 931 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 932 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 933 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 934 unsigned char (*read_byte)(struct mtd_info *mtd); 935 void *priv; 936 }; 937 938 /** 939 * struct platform_nand_data - container structure for platform-specific data 940 * @chip: chip level chip structure 941 * @ctrl: controller level device structure 942 */ 943 struct platform_nand_data { 944 struct platform_nand_chip chip; 945 struct platform_nand_ctrl ctrl; 946 }; 947 948 /* Some helpers to access the data structures */ 949 static inline 950 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 951 { 952 struct nand_chip *chip = mtd->priv; 953 954 return chip->priv; 955 } 956 957 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 958 /* return the supported features. */ 959 static inline int onfi_feature(struct nand_chip *chip) 960 { 961 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 962 } 963 964 /* return the supported asynchronous timing mode. */ 965 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 966 { 967 if (!chip->onfi_version) 968 return ONFI_TIMING_MODE_UNKNOWN; 969 return le16_to_cpu(chip->onfi_params.async_timing_mode); 970 } 971 972 /* return the supported synchronous timing mode. */ 973 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 974 { 975 if (!chip->onfi_version) 976 return ONFI_TIMING_MODE_UNKNOWN; 977 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 978 } 979 #endif 980 981 /* 982 * Check if it is a SLC nand. 983 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 984 * We do not distinguish the MLC and TLC now. 985 */ 986 static inline bool nand_is_slc(struct nand_chip *chip) 987 { 988 return chip->bits_per_cell == 1; 989 } 990 991 /** 992 * Check if the opcode's address should be sent only on the lower 8 bits 993 * @command: opcode to check 994 */ 995 static inline int nand_opcode_8bits(unsigned int command) 996 { 997 switch (command) { 998 case NAND_CMD_READID: 999 case NAND_CMD_PARAM: 1000 case NAND_CMD_GET_FEATURES: 1001 case NAND_CMD_SET_FEATURES: 1002 return 1; 1003 default: 1004 break; 1005 } 1006 return 0; 1007 } 1008 1009 /* return the supported JEDEC features. */ 1010 static inline int jedec_feature(struct nand_chip *chip) 1011 { 1012 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1013 : 0; 1014 } 1015 1016 #ifdef __UBOOT__ 1017 /* Standard NAND functions from nand_base.c */ 1018 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1019 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1020 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1021 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1022 uint8_t nand_read_byte(struct mtd_info *mtd); 1023 #endif 1024 #endif /* __LINUX_MTD_NAND_H */ 1025