1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include "config.h" 22 23 #include "linux/mtd/compat.h" 24 #include "linux/mtd/mtd.h" 25 #include "linux/mtd/bbm.h" 26 27 28 struct mtd_info; 29 struct nand_flash_dev; 30 /* Scan and identify a NAND device */ 31 extern int nand_scan (struct mtd_info *mtd, int max_chips); 32 /* Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type */ 34 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 35 const struct nand_flash_dev *table); 36 extern int nand_scan_tail(struct mtd_info *mtd); 37 38 /* Free resources held by the NAND device */ 39 extern void nand_release(struct mtd_info *mtd); 40 41 /* Internal helper for board drivers which need to override command function */ 42 extern void nand_wait_ready(struct mtd_info *mtd); 43 44 /* 45 * This constant declares the max. oobsize / page, which 46 * is supported now. If you add a chip with bigger oobsize/page 47 * adjust this accordingly. 48 */ 49 #define NAND_MAX_OOBSIZE 576 50 #define NAND_MAX_PAGESIZE 8192 51 52 /* 53 * Constants for hardware specific CLE/ALE/NCE function 54 * 55 * These are bits which can be or'ed to set/clear multiple 56 * bits in one go. 57 */ 58 /* Select the chip by setting nCE to low */ 59 #define NAND_NCE 0x01 60 /* Select the command latch by setting CLE to high */ 61 #define NAND_CLE 0x02 62 /* Select the address latch by setting ALE to high */ 63 #define NAND_ALE 0x04 64 65 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 66 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 67 #define NAND_CTRL_CHANGE 0x80 68 69 /* 70 * Standard NAND flash commands 71 */ 72 #define NAND_CMD_READ0 0 73 #define NAND_CMD_READ1 1 74 #define NAND_CMD_RNDOUT 5 75 #define NAND_CMD_PAGEPROG 0x10 76 #define NAND_CMD_READOOB 0x50 77 #define NAND_CMD_ERASE1 0x60 78 #define NAND_CMD_STATUS 0x70 79 #define NAND_CMD_STATUS_MULTI 0x71 80 #define NAND_CMD_SEQIN 0x80 81 #define NAND_CMD_RNDIN 0x85 82 #define NAND_CMD_READID 0x90 83 #define NAND_CMD_ERASE2 0xd0 84 #define NAND_CMD_PARAM 0xec 85 #define NAND_CMD_RESET 0xff 86 87 #define NAND_CMD_LOCK 0x2a 88 #define NAND_CMD_UNLOCK1 0x23 89 #define NAND_CMD_UNLOCK2 0x24 90 91 /* Extended commands for large page devices */ 92 #define NAND_CMD_READSTART 0x30 93 #define NAND_CMD_RNDOUTSTART 0xE0 94 #define NAND_CMD_CACHEDPROG 0x15 95 96 /* Extended commands for AG-AND device */ 97 /* 98 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 99 * there is no way to distinguish that from NAND_CMD_READ0 100 * until the remaining sequence of commands has been completed 101 * so add a high order bit and mask it off in the command. 102 */ 103 #define NAND_CMD_DEPLETE1 0x100 104 #define NAND_CMD_DEPLETE2 0x38 105 #define NAND_CMD_STATUS_MULTI 0x71 106 #define NAND_CMD_STATUS_ERROR 0x72 107 /* multi-bank error status (banks 0-3) */ 108 #define NAND_CMD_STATUS_ERROR0 0x73 109 #define NAND_CMD_STATUS_ERROR1 0x74 110 #define NAND_CMD_STATUS_ERROR2 0x75 111 #define NAND_CMD_STATUS_ERROR3 0x76 112 #define NAND_CMD_STATUS_RESET 0x7f 113 #define NAND_CMD_STATUS_CLEAR 0xff 114 115 #define NAND_CMD_NONE -1 116 117 /* Status bits */ 118 #define NAND_STATUS_FAIL 0x01 119 #define NAND_STATUS_FAIL_N1 0x02 120 #define NAND_STATUS_TRUE_READY 0x20 121 #define NAND_STATUS_READY 0x40 122 #define NAND_STATUS_WP 0x80 123 124 /* 125 * Constants for ECC_MODES 126 */ 127 typedef enum { 128 NAND_ECC_NONE, 129 NAND_ECC_SOFT, 130 NAND_ECC_HW, 131 NAND_ECC_HW_SYNDROME, 132 NAND_ECC_HW_OOB_FIRST, 133 NAND_ECC_SOFT_BCH, 134 } nand_ecc_modes_t; 135 136 /* 137 * Constants for Hardware ECC 138 */ 139 /* Reset Hardware ECC for read */ 140 #define NAND_ECC_READ 0 141 /* Reset Hardware ECC for write */ 142 #define NAND_ECC_WRITE 1 143 /* Enable Hardware ECC before syndrom is read back from flash */ 144 #define NAND_ECC_READSYN 2 145 146 /* Bit mask for flags passed to do_nand_read_ecc */ 147 #define NAND_GET_DEVICE 0x80 148 149 150 /* 151 * Option constants for bizarre disfunctionality and real 152 * features. 153 */ 154 /* Chip can not auto increment pages */ 155 #define NAND_NO_AUTOINCR 0x00000001 156 /* Buswitdh is 16 bit */ 157 #define NAND_BUSWIDTH_16 0x00000002 158 /* Device supports partial programming without padding */ 159 #define NAND_NO_PADDING 0x00000004 160 /* Chip has cache program function */ 161 #define NAND_CACHEPRG 0x00000008 162 /* Chip has copy back function */ 163 #define NAND_COPYBACK 0x00000010 164 /* 165 * AND Chip which has 4 banks and a confusing page / block 166 * assignment. See Renesas datasheet for further information. 167 */ 168 #define NAND_IS_AND 0x00000020 169 /* 170 * Chip has a array of 4 pages which can be read without 171 * additional ready /busy waits. 172 */ 173 #define NAND_4PAGE_ARRAY 0x00000040 174 /* 175 * Chip requires that BBT is periodically rewritten to prevent 176 * bits from adjacent blocks from 'leaking' in altering data. 177 * This happens with the Renesas AG-AND chips, possibly others. 178 */ 179 #define BBT_AUTO_REFRESH 0x00000080 180 /* 181 * Chip does not require ready check on read. True 182 * for all large page devices, as they do not support 183 * autoincrement. 184 */ 185 #define NAND_NO_READRDY 0x00000100 186 /* Chip does not allow subpage writes */ 187 #define NAND_NO_SUBPAGE_WRITE 0x00000200 188 189 /* Device is one of 'new' xD cards that expose fake nand command set */ 190 #define NAND_BROKEN_XD 0x00000400 191 192 /* Device behaves just like nand, but is readonly */ 193 #define NAND_ROM 0x00000800 194 195 /* Options valid for Samsung large page devices */ 196 #define NAND_SAMSUNG_LP_OPTIONS \ 197 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 198 199 /* Macros to identify the above */ 200 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) 201 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 202 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 203 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 204 /* Large page NAND with SOFT_ECC should support subpage reads */ 205 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ 206 && (chip->page_shift > 9)) 207 208 /* Mask to zero out the chip options, which come from the id table */ 209 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) 210 211 /* Non chip related options */ 212 /* 213 * Use a flash based bad block table. OOB identifier is saved in OOB area. 214 * This option is passed to the default bad block table function. 215 */ 216 #define NAND_USE_FLASH_BBT 0x00010000 217 /* This option skips the bbt scan during initialization. */ 218 #define NAND_SKIP_BBTSCAN 0x00020000 219 /* 220 * This option is defined if the board driver allocates its own buffers 221 * (e.g. because it needs them DMA-coherent). 222 */ 223 #define NAND_OWN_BUFFERS 0x00040000 224 /* Chip may not exist, so silence any errors in scan */ 225 #define NAND_SCAN_SILENT_NODEV 0x00080000 226 /* 227 * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch 228 * the OOB area. 229 */ 230 #define NAND_USE_FLASH_BBT_NO_OOB 0x00800000 231 /* Create an empty BBT with no vendor information if the BBT is available */ 232 #define NAND_CREATE_EMPTY_BBT 0x01000000 233 234 /* Options set by nand scan */ 235 /* Nand scan has allocated controller struct */ 236 #define NAND_CONTROLLER_ALLOC 0x80000000 237 238 /* Cell info constants */ 239 #define NAND_CI_CHIPNR_MSK 0x03 240 #define NAND_CI_CELLTYPE_MSK 0x0C 241 242 /* Keep gcc happy */ 243 struct nand_chip; 244 245 struct nand_onfi_params { 246 /* rev info and features block */ 247 /* 'O' 'N' 'F' 'I' */ 248 u8 sig[4]; 249 __le16 revision; 250 __le16 features; 251 __le16 opt_cmd; 252 u8 reserved[22]; 253 254 /* manufacturer information block */ 255 char manufacturer[12]; 256 char model[20]; 257 u8 jedec_id; 258 __le16 date_code; 259 u8 reserved2[13]; 260 261 /* memory organization block */ 262 __le32 byte_per_page; 263 __le16 spare_bytes_per_page; 264 __le32 data_bytes_per_ppage; 265 __le16 spare_bytes_per_ppage; 266 __le32 pages_per_block; 267 __le32 blocks_per_lun; 268 u8 lun_count; 269 u8 addr_cycles; 270 u8 bits_per_cell; 271 __le16 bb_per_lun; 272 __le16 block_endurance; 273 u8 guaranteed_good_blocks; 274 __le16 guaranteed_block_endurance; 275 u8 programs_per_page; 276 u8 ppage_attr; 277 u8 ecc_bits; 278 u8 interleaved_bits; 279 u8 interleaved_ops; 280 u8 reserved3[13]; 281 282 /* electrical parameter block */ 283 u8 io_pin_capacitance_max; 284 __le16 async_timing_mode; 285 __le16 program_cache_timing_mode; 286 __le16 t_prog; 287 __le16 t_bers; 288 __le16 t_r; 289 __le16 t_ccs; 290 __le16 src_sync_timing_mode; 291 __le16 src_ssync_features; 292 __le16 clk_pin_capacitance_typ; 293 __le16 io_pin_capacitance_typ; 294 __le16 input_pin_capacitance_typ; 295 u8 input_pin_capacitance_max; 296 u8 driver_strenght_support; 297 __le16 t_int_r; 298 __le16 t_ald; 299 u8 reserved4[7]; 300 301 /* vendor */ 302 u8 reserved5[90]; 303 304 __le16 crc; 305 } __attribute__((packed)); 306 307 #define ONFI_CRC_BASE 0x4F4E 308 309 /** 310 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 311 * @lock: protection lock 312 * @active: the mtd device which holds the controller currently 313 * @wq: wait queue to sleep on if a NAND operation is in 314 * progress used instead of the per chip wait queue 315 * when a hw controller is available. 316 */ 317 struct nand_hw_control { 318 /* XXX U-BOOT XXX */ 319 #if 0 320 spinlock_t lock; 321 wait_queue_head_t wq; 322 #endif 323 struct nand_chip *active; 324 }; 325 326 /** 327 * struct nand_ecc_ctrl - Control structure for ecc 328 * @mode: ecc mode 329 * @steps: number of ecc steps per page 330 * @size: data bytes per ecc step 331 * @bytes: ecc bytes per step 332 * @total: total number of ecc bytes per page 333 * @prepad: padding information for syndrome based ecc generators 334 * @postpad: padding information for syndrome based ecc generators 335 * @layout: ECC layout control struct pointer 336 * @priv: pointer to private ecc control data 337 * @hwctl: function to control hardware ecc generator. Must only 338 * be provided if an hardware ECC is available 339 * @calculate: function for ecc calculation or readback from ecc hardware 340 * @correct: function for ecc correction, matching to ecc generator (sw/hw) 341 * @read_page_raw: function to read a raw page without ECC 342 * @write_page_raw: function to write a raw page without ECC 343 * @read_page: function to read a page according to the ecc generator 344 * requirements. 345 * @read_subpage: function to read parts of the page covered by ECC. 346 * @write_page: function to write a page according to the ecc generator 347 * requirements. 348 * @read_oob: function to read chip OOB data 349 * @write_oob: function to write chip OOB data 350 */ 351 struct nand_ecc_ctrl { 352 nand_ecc_modes_t mode; 353 int steps; 354 int size; 355 int bytes; 356 int total; 357 int prepad; 358 int postpad; 359 struct nand_ecclayout *layout; 360 void *priv; 361 void (*hwctl)(struct mtd_info *mtd, int mode); 362 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 363 uint8_t *ecc_code); 364 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 365 uint8_t *calc_ecc); 366 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 367 uint8_t *buf, int page); 368 void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 369 const uint8_t *buf); 370 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 371 uint8_t *buf, int page); 372 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 373 uint32_t offs, uint32_t len, uint8_t *buf); 374 void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 375 const uint8_t *buf); 376 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page, 377 int sndcmd); 378 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 379 int page); 380 }; 381 382 /** 383 * struct nand_buffers - buffer structure for read/write 384 * @ecccalc: buffer for calculated ecc 385 * @ecccode: buffer for ecc read from flash 386 * @databuf: buffer for data - dynamically sized 387 * 388 * Do not change the order of buffers. databuf and oobrbuf must be in 389 * consecutive order. 390 */ 391 struct nand_buffers { 392 uint8_t ecccalc[NAND_MAX_OOBSIZE]; 393 uint8_t ecccode[NAND_MAX_OOBSIZE]; 394 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; 395 }; 396 397 /** 398 * struct nand_chip - NAND Private Flash Chip Data 399 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 400 * flash device 401 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 402 * flash device. 403 * @read_byte: [REPLACEABLE] read one byte from the chip 404 * @read_word: [REPLACEABLE] read one word from the chip 405 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 406 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 407 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip 408 * data. 409 * @select_chip: [REPLACEABLE] select chip nr 410 * @block_bad: [REPLACEABLE] check, if the block is bad 411 * @block_markbad: [REPLACEABLE] mark the block bad 412 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 413 * ALE/CLE/nCE. Also used to write command and address 414 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting 415 * mtd->oobsize, mtd->writesize and so on. 416 * @id_data contains the 8 bytes values of NAND_CMD_READID. 417 * Return with the bus width. 418 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing 419 * device ready/busy line. If set to NULL no access to 420 * ready/busy is available and the ready/busy information 421 * is read from the chip status register. 422 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 423 * commands to the chip. 424 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 425 * ready. 426 * @ecc: [BOARDSPECIFIC] ecc control ctructure 427 * @buffers: buffer structure for read/write 428 * @hwcontrol: platform-specific hardware control structure 429 * @ops: oob operation operands 430 * @erase_cmd: [INTERN] erase command write function, selectable due 431 * to AND support. 432 * @scan_bbt: [REPLACEABLE] function to scan bad block table 433 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 434 * data from array to read regs (tR). 435 * @state: [INTERN] the current state of the NAND device 436 * @oob_poi: poison value buffer 437 * @page_shift: [INTERN] number of address bits in a page (column 438 * address bits). 439 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 440 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 441 * @chip_shift: [INTERN] number of address bits in one chip 442 * @options: [BOARDSPECIFIC] various chip options. They can partly 443 * be set to inform nand_scan about special functionality. 444 * See the defines for further explanation. 445 * @badblockpos: [INTERN] position of the bad block marker in the oob 446 * area. 447 * @badblockbits: [INTERN] number of bits to left-shift the bad block 448 * number 449 * @cellinfo: [INTERN] MLC/multichip data from chip ident 450 * @numchips: [INTERN] number of physical chips 451 * @chipsize: [INTERN] the size of one chip for multichip arrays 452 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 453 * @pagebuf: [INTERN] holds the pagenumber which is currently in 454 * data_buf. 455 * @subpagesize: [INTERN] holds the subpagesize 456 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 457 * non 0 if ONFI supported. 458 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 459 * supported, 0 otherwise. 460 * @ecclayout: [REPLACEABLE] the default ecc placement scheme 461 * @bbt: [INTERN] bad block table pointer 462 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 463 * lookup. 464 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 465 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 466 * bad block scan. 467 * @controller: [REPLACEABLE] a pointer to a hardware controller 468 * structure which is shared among multiple independend 469 * devices. 470 * @priv: [OPTIONAL] pointer to private chip date 471 * @errstat: [OPTIONAL] hardware specific function to perform 472 * additional error status checks (determine if errors are 473 * correctable). 474 * @write_page: [REPLACEABLE] High-level page write function 475 */ 476 477 struct nand_chip { 478 void __iomem *IO_ADDR_R; 479 void __iomem *IO_ADDR_W; 480 481 uint8_t (*read_byte)(struct mtd_info *mtd); 482 u16 (*read_word)(struct mtd_info *mtd); 483 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 484 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 485 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 486 void (*select_chip)(struct mtd_info *mtd, int chip); 487 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 488 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 489 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 490 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, 491 u8 *id_data); 492 int (*dev_ready)(struct mtd_info *mtd); 493 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 494 int page_addr); 495 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 496 void (*erase_cmd)(struct mtd_info *mtd, int page); 497 int (*scan_bbt)(struct mtd_info *mtd); 498 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 499 int status, int page); 500 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 501 const uint8_t *buf, int page, int cached, int raw); 502 503 int chip_delay; 504 unsigned int options; 505 506 int page_shift; 507 int phys_erase_shift; 508 int bbt_erase_shift; 509 int chip_shift; 510 int numchips; 511 uint64_t chipsize; 512 int pagemask; 513 int pagebuf; 514 int subpagesize; 515 uint8_t cellinfo; 516 int badblockpos; 517 int badblockbits; 518 519 int onfi_version; 520 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 521 struct nand_onfi_params onfi_params; 522 #endif 523 524 int state; 525 526 uint8_t *oob_poi; 527 struct nand_hw_control *controller; 528 struct nand_ecclayout *ecclayout; 529 530 struct nand_ecc_ctrl ecc; 531 struct nand_buffers *buffers; 532 struct nand_hw_control hwcontrol; 533 534 struct mtd_oob_ops ops; 535 536 uint8_t *bbt; 537 struct nand_bbt_descr *bbt_td; 538 struct nand_bbt_descr *bbt_md; 539 540 struct nand_bbt_descr *badblock_pattern; 541 542 void *priv; 543 }; 544 545 /* 546 * NAND Flash Manufacturer ID Codes 547 */ 548 #define NAND_MFR_TOSHIBA 0x98 549 #define NAND_MFR_SAMSUNG 0xec 550 #define NAND_MFR_FUJITSU 0x04 551 #define NAND_MFR_NATIONAL 0x8f 552 #define NAND_MFR_RENESAS 0x07 553 #define NAND_MFR_STMICRO 0x20 554 #define NAND_MFR_HYNIX 0xad 555 #define NAND_MFR_MICRON 0x2c 556 #define NAND_MFR_AMD 0x01 557 558 /** 559 * struct nand_flash_dev - NAND Flash Device ID Structure 560 * @name: Identify the device type 561 * @id: device ID code 562 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 563 * If the pagesize is 0, then the real pagesize 564 * and the eraseize are determined from the 565 * extended id bytes in the chip 566 * @erasesize: Size of an erase block in the flash device. 567 * @chipsize: Total chipsize in Mega Bytes 568 * @options: Bitfield to store chip relevant options 569 */ 570 struct nand_flash_dev { 571 char *name; 572 int id; 573 unsigned long pagesize; 574 unsigned long chipsize; 575 unsigned long erasesize; 576 unsigned long options; 577 }; 578 579 /** 580 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 581 * @name: Manufacturer name 582 * @id: manufacturer ID code of device. 583 */ 584 struct nand_manufacturers { 585 int id; 586 char *name; 587 }; 588 589 extern const struct nand_flash_dev nand_flash_ids[]; 590 extern const struct nand_manufacturers nand_manuf_ids[]; 591 592 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 593 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 594 extern int nand_default_bbt(struct mtd_info *mtd); 595 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 596 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 597 int allowbbt); 598 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 599 size_t *retlen, uint8_t *buf); 600 601 /* 602 * Constants for oob configuration 603 */ 604 #define NAND_SMALL_BADBLOCK_POS 5 605 #define NAND_LARGE_BADBLOCK_POS 0 606 607 /** 608 * struct platform_nand_chip - chip level device structure 609 * @nr_chips: max. number of chips to scan for 610 * @chip_offset: chip number offset 611 * @nr_partitions: number of partitions pointed to by partitions (or zero) 612 * @partitions: mtd partition list 613 * @chip_delay: R/B delay value in us 614 * @options: Option flags, e.g. 16bit buswidth 615 * @ecclayout: ecc layout info structure 616 * @part_probe_types: NULL-terminated array of probe types 617 * @priv: hardware controller specific settings 618 */ 619 struct platform_nand_chip { 620 int nr_chips; 621 int chip_offset; 622 int nr_partitions; 623 struct mtd_partition *partitions; 624 struct nand_ecclayout *ecclayout; 625 int chip_delay; 626 unsigned int options; 627 const char **part_probe_types; 628 void *priv; 629 }; 630 631 /* Keep gcc happy */ 632 struct platform_device; 633 634 /** 635 * struct platform_nand_ctrl - controller level device structure 636 * @hwcontrol: platform specific hardware control structure 637 * @dev_ready: platform specific function to read ready/busy pin 638 * @select_chip: platform specific chip select function 639 * @cmd_ctrl: platform specific function for controlling 640 * ALE/CLE/nCE. Also used to write command and address 641 * @priv: private data to transport driver specific settings 642 * 643 * All fields are optional and depend on the hardware driver requirements 644 */ 645 struct platform_nand_ctrl { 646 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 647 int (*dev_ready)(struct mtd_info *mtd); 648 void (*select_chip)(struct mtd_info *mtd, int chip); 649 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 650 void *priv; 651 }; 652 653 /** 654 * struct platform_nand_data - container structure for platform-specific data 655 * @chip: chip level chip structure 656 * @ctrl: controller level device structure 657 */ 658 struct platform_nand_data { 659 struct platform_nand_chip chip; 660 struct platform_nand_ctrl ctrl; 661 }; 662 663 /* Some helpers to access the data structures */ 664 static inline 665 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 666 { 667 struct nand_chip *chip = mtd->priv; 668 669 return chip->priv; 670 } 671 672 /* Standard NAND functions from nand_base.c */ 673 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 674 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 675 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 676 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 677 uint8_t nand_read_byte(struct mtd_info *mtd); 678 679 #endif /* __LINUX_MTD_NAND_H */ 680