1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 /* XXX U-BOOT XXX */ 22 #if 0 23 #include <linux/wait.h> 24 #include <linux/spinlock.h> 25 #include <linux/mtd/mtd.h> 26 #endif 27 28 #include "config.h" 29 30 #include "linux/mtd/compat.h" 31 #include "linux/mtd/mtd.h" 32 #include "linux/mtd/bbm.h" 33 34 35 struct mtd_info; 36 /* Scan and identify a NAND device */ 37 extern int nand_scan (struct mtd_info *mtd, int max_chips); 38 /* Separate phases of nand_scan(), allowing board driver to intervene 39 * and override command or ECC setup according to flash type */ 40 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips); 41 extern int nand_scan_tail(struct mtd_info *mtd); 42 43 /* Free resources held by the NAND device */ 44 extern void nand_release (struct mtd_info *mtd); 45 46 /* Internal helper for board drivers which need to override command function */ 47 extern void nand_wait_ready(struct mtd_info *mtd); 48 49 /* The maximum number of NAND chips in an array */ 50 #ifndef NAND_MAX_CHIPS 51 #define NAND_MAX_CHIPS 8 52 #endif 53 54 /* This constant declares the max. oobsize / page, which 55 * is supported now. If you add a chip with bigger oobsize/page 56 * adjust this accordingly. 57 */ 58 #define NAND_MAX_OOBSIZE 128 59 #define NAND_MAX_PAGESIZE 4096 60 61 /* 62 * Constants for hardware specific CLE/ALE/NCE function 63 * 64 * These are bits which can be or'ed to set/clear multiple 65 * bits in one go. 66 */ 67 /* Select the chip by setting nCE to low */ 68 #define NAND_NCE 0x01 69 /* Select the command latch by setting CLE to high */ 70 #define NAND_CLE 0x02 71 /* Select the address latch by setting ALE to high */ 72 #define NAND_ALE 0x04 73 74 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 75 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 76 #define NAND_CTRL_CHANGE 0x80 77 78 /* 79 * Standard NAND flash commands 80 */ 81 #define NAND_CMD_READ0 0 82 #define NAND_CMD_READ1 1 83 #define NAND_CMD_RNDOUT 5 84 #define NAND_CMD_PAGEPROG 0x10 85 #define NAND_CMD_READOOB 0x50 86 #define NAND_CMD_ERASE1 0x60 87 #define NAND_CMD_STATUS 0x70 88 #define NAND_CMD_STATUS_MULTI 0x71 89 #define NAND_CMD_SEQIN 0x80 90 #define NAND_CMD_RNDIN 0x85 91 #define NAND_CMD_READID 0x90 92 #define NAND_CMD_ERASE2 0xd0 93 #define NAND_CMD_RESET 0xff 94 95 /* Extended commands for large page devices */ 96 #define NAND_CMD_READSTART 0x30 97 #define NAND_CMD_RNDOUTSTART 0xE0 98 #define NAND_CMD_CACHEDPROG 0x15 99 100 /* Extended commands for AG-AND device */ 101 /* 102 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 103 * there is no way to distinguish that from NAND_CMD_READ0 104 * until the remaining sequence of commands has been completed 105 * so add a high order bit and mask it off in the command. 106 */ 107 #define NAND_CMD_DEPLETE1 0x100 108 #define NAND_CMD_DEPLETE2 0x38 109 #define NAND_CMD_STATUS_MULTI 0x71 110 #define NAND_CMD_STATUS_ERROR 0x72 111 /* multi-bank error status (banks 0-3) */ 112 #define NAND_CMD_STATUS_ERROR0 0x73 113 #define NAND_CMD_STATUS_ERROR1 0x74 114 #define NAND_CMD_STATUS_ERROR2 0x75 115 #define NAND_CMD_STATUS_ERROR3 0x76 116 #define NAND_CMD_STATUS_RESET 0x7f 117 #define NAND_CMD_STATUS_CLEAR 0xff 118 119 #define NAND_CMD_NONE -1 120 121 /* Status bits */ 122 #define NAND_STATUS_FAIL 0x01 123 #define NAND_STATUS_FAIL_N1 0x02 124 #define NAND_STATUS_TRUE_READY 0x20 125 #define NAND_STATUS_READY 0x40 126 #define NAND_STATUS_WP 0x80 127 128 /* 129 * Constants for ECC_MODES 130 */ 131 typedef enum { 132 NAND_ECC_NONE, 133 NAND_ECC_SOFT, 134 NAND_ECC_HW, 135 NAND_ECC_HW_SYNDROME, 136 } nand_ecc_modes_t; 137 138 /* 139 * Constants for Hardware ECC 140 */ 141 /* Reset Hardware ECC for read */ 142 #define NAND_ECC_READ 0 143 /* Reset Hardware ECC for write */ 144 #define NAND_ECC_WRITE 1 145 /* Enable Hardware ECC before syndrom is read back from flash */ 146 #define NAND_ECC_READSYN 2 147 148 /* Bit mask for flags passed to do_nand_read_ecc */ 149 #define NAND_GET_DEVICE 0x80 150 151 152 /* Option constants for bizarre disfunctionality and real 153 * features 154 */ 155 /* Chip can not auto increment pages */ 156 #define NAND_NO_AUTOINCR 0x00000001 157 /* Buswitdh is 16 bit */ 158 #define NAND_BUSWIDTH_16 0x00000002 159 /* Device supports partial programming without padding */ 160 #define NAND_NO_PADDING 0x00000004 161 /* Chip has cache program function */ 162 #define NAND_CACHEPRG 0x00000008 163 /* Chip has copy back function */ 164 #define NAND_COPYBACK 0x00000010 165 /* AND Chip which has 4 banks and a confusing page / block 166 * assignment. See Renesas datasheet for further information */ 167 #define NAND_IS_AND 0x00000020 168 /* Chip has a array of 4 pages which can be read without 169 * additional ready /busy waits */ 170 #define NAND_4PAGE_ARRAY 0x00000040 171 /* Chip requires that BBT is periodically rewritten to prevent 172 * bits from adjacent blocks from 'leaking' in altering data. 173 * This happens with the Renesas AG-AND chips, possibly others. */ 174 #define BBT_AUTO_REFRESH 0x00000080 175 /* Chip does not require ready check on read. True 176 * for all large page devices, as they do not support 177 * autoincrement.*/ 178 #define NAND_NO_READRDY 0x00000100 179 /* Chip does not allow subpage writes */ 180 #define NAND_NO_SUBPAGE_WRITE 0x00000200 181 182 183 /* Options valid for Samsung large page devices */ 184 #define NAND_SAMSUNG_LP_OPTIONS \ 185 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 186 187 /* Macros to identify the above */ 188 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) 189 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 190 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 191 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 192 /* Large page NAND with SOFT_ECC should support subpage reads */ 193 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ 194 && (chip->page_shift > 9)) 195 196 /* Mask to zero out the chip options, which come from the id table */ 197 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) 198 199 /* Non chip related options */ 200 /* Use a flash based bad block table. This option is passed to the 201 * default bad block table function. */ 202 #define NAND_USE_FLASH_BBT 0x00010000 203 /* This option skips the bbt scan during initialization. */ 204 #define NAND_SKIP_BBTSCAN 0x00020000 205 /* This option is defined if the board driver allocates its own buffers 206 (e.g. because it needs them DMA-coherent */ 207 #define NAND_OWN_BUFFERS 0x00040000 208 /* Options set by nand scan */ 209 /* bbt has already been read */ 210 #define NAND_BBT_SCANNED 0x40000000 211 /* Nand scan has allocated controller struct */ 212 #define NAND_CONTROLLER_ALLOC 0x80000000 213 214 /* Cell info constants */ 215 #define NAND_CI_CHIPNR_MSK 0x03 216 #define NAND_CI_CELLTYPE_MSK 0x0C 217 218 /* Keep gcc happy */ 219 struct nand_chip; 220 221 /** 222 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 223 * @lock: protection lock 224 * @active: the mtd device which holds the controller currently 225 * @wq: wait queue to sleep on if a NAND operation is in progress 226 * used instead of the per chip wait queue when a hw controller is available 227 */ 228 struct nand_hw_control { 229 /* XXX U-BOOT XXX */ 230 #if 0 231 spinlock_t lock; 232 wait_queue_head_t wq; 233 #endif 234 struct nand_chip *active; 235 }; 236 237 /** 238 * struct nand_ecc_ctrl - Control structure for ecc 239 * @mode: ecc mode 240 * @steps: number of ecc steps per page 241 * @size: data bytes per ecc step 242 * @bytes: ecc bytes per step 243 * @total: total number of ecc bytes per page 244 * @prepad: padding information for syndrome based ecc generators 245 * @postpad: padding information for syndrome based ecc generators 246 * @layout: ECC layout control struct pointer 247 * @hwctl: function to control hardware ecc generator. Must only 248 * be provided if an hardware ECC is available 249 * @calculate: function for ecc calculation or readback from ecc hardware 250 * @correct: function for ecc correction, matching to ecc generator (sw/hw) 251 * @read_page_raw: function to read a raw page without ECC 252 * @write_page_raw: function to write a raw page without ECC 253 * @read_page: function to read a page according to the ecc generator requirements 254 * @write_page: function to write a page according to the ecc generator requirements 255 * @read_oob: function to read chip OOB data 256 * @write_oob: function to write chip OOB data 257 */ 258 struct nand_ecc_ctrl { 259 nand_ecc_modes_t mode; 260 int steps; 261 int size; 262 int bytes; 263 int total; 264 int prepad; 265 int postpad; 266 struct nand_ecclayout *layout; 267 void (*hwctl)(struct mtd_info *mtd, int mode); 268 int (*calculate)(struct mtd_info *mtd, 269 const uint8_t *dat, 270 uint8_t *ecc_code); 271 int (*correct)(struct mtd_info *mtd, uint8_t *dat, 272 uint8_t *read_ecc, 273 uint8_t *calc_ecc); 274 int (*read_page_raw)(struct mtd_info *mtd, 275 struct nand_chip *chip, 276 uint8_t *buf); 277 void (*write_page_raw)(struct mtd_info *mtd, 278 struct nand_chip *chip, 279 const uint8_t *buf); 280 int (*read_page)(struct mtd_info *mtd, 281 struct nand_chip *chip, 282 uint8_t *buf); 283 int (*read_subpage)(struct mtd_info *mtd, 284 struct nand_chip *chip, 285 uint32_t offs, uint32_t len, 286 uint8_t *buf); 287 void (*write_page)(struct mtd_info *mtd, 288 struct nand_chip *chip, 289 const uint8_t *buf); 290 int (*read_oob)(struct mtd_info *mtd, 291 struct nand_chip *chip, 292 int page, 293 int sndcmd); 294 int (*write_oob)(struct mtd_info *mtd, 295 struct nand_chip *chip, 296 int page); 297 }; 298 299 /** 300 * struct nand_buffers - buffer structure for read/write 301 * @ecccalc: buffer for calculated ecc 302 * @ecccode: buffer for ecc read from flash 303 * @databuf: buffer for data - dynamically sized 304 * 305 * Do not change the order of buffers. databuf and oobrbuf must be in 306 * consecutive order. 307 */ 308 struct nand_buffers { 309 uint8_t ecccalc[NAND_MAX_OOBSIZE]; 310 uint8_t ecccode[NAND_MAX_OOBSIZE]; 311 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; 312 }; 313 314 /** 315 * struct nand_chip - NAND Private Flash Chip Data 316 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device 317 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device 318 * @read_byte: [REPLACEABLE] read one byte from the chip 319 * @read_word: [REPLACEABLE] read one word from the chip 320 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 321 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 322 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data 323 * @select_chip: [REPLACEABLE] select chip nr 324 * @block_bad: [REPLACEABLE] check, if the block is bad 325 * @block_markbad: [REPLACEABLE] mark the block bad 326 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling 327 * ALE/CLE/nCE. Also used to write command and address 328 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line 329 * If set to NULL no access to ready/busy is available and the ready/busy information 330 * is read from the chip status register 331 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip 332 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready 333 * @ecc: [BOARDSPECIFIC] ecc control ctructure 334 * @buffers: buffer structure for read/write 335 * @hwcontrol: platform-specific hardware control structure 336 * @ops: oob operation operands 337 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support 338 * @scan_bbt: [REPLACEABLE] function to scan bad block table 339 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) 340 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress 341 * @state: [INTERN] the current state of the NAND device 342 * @oob_poi: poison value buffer 343 * @page_shift: [INTERN] number of address bits in a page (column address bits) 344 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 345 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 346 * @chip_shift: [INTERN] number of address bits in one chip 347 * @datbuf: [INTERN] internal buffer for one page + oob 348 * @oobbuf: [INTERN] oob buffer for one eraseblock 349 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized 350 * @data_poi: [INTERN] pointer to a data buffer 351 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about 352 * special functionality. See the defines for further explanation 353 * @badblockpos: [INTERN] position of the bad block marker in the oob area 354 * @cellinfo: [INTERN] MLC/multichip data from chip ident 355 * @numchips: [INTERN] number of physical chips 356 * @chipsize: [INTERN] the size of one chip for multichip arrays 357 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 358 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf 359 * @subpagesize: [INTERN] holds the subpagesize 360 * @ecclayout: [REPLACEABLE] the default ecc placement scheme 361 * @bbt: [INTERN] bad block table pointer 362 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup 363 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 364 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan 365 * @controller: [REPLACEABLE] a pointer to a hardware controller structure 366 * which is shared among multiple independend devices 367 * @priv: [OPTIONAL] pointer to private chip date 368 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks 369 * (determine if errors are correctable) 370 * @write_page: [REPLACEABLE] High-level page write function 371 */ 372 373 struct nand_chip { 374 void __iomem *IO_ADDR_R; 375 void __iomem *IO_ADDR_W; 376 377 uint8_t (*read_byte)(struct mtd_info *mtd); 378 u16 (*read_word)(struct mtd_info *mtd); 379 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 380 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 381 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 382 void (*select_chip)(struct mtd_info *mtd, int chip); 383 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 384 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 385 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, 386 unsigned int ctrl); 387 int (*dev_ready)(struct mtd_info *mtd); 388 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); 389 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 390 void (*erase_cmd)(struct mtd_info *mtd, int page); 391 int (*scan_bbt)(struct mtd_info *mtd); 392 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); 393 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 394 const uint8_t *buf, int page, int cached, int raw); 395 396 int chip_delay; 397 unsigned int options; 398 399 int page_shift; 400 int phys_erase_shift; 401 int bbt_erase_shift; 402 int chip_shift; 403 int numchips; 404 unsigned long chipsize; 405 int pagemask; 406 int pagebuf; 407 int subpagesize; 408 uint8_t cellinfo; 409 int badblockpos; 410 411 int state; 412 413 uint8_t *oob_poi; 414 struct nand_hw_control *controller; 415 struct nand_ecclayout *ecclayout; 416 417 struct nand_ecc_ctrl ecc; 418 struct nand_buffers *buffers; 419 420 struct nand_hw_control hwcontrol; 421 422 struct mtd_oob_ops ops; 423 424 uint8_t *bbt; 425 struct nand_bbt_descr *bbt_td; 426 struct nand_bbt_descr *bbt_md; 427 428 struct nand_bbt_descr *badblock_pattern; 429 430 void *priv; 431 }; 432 433 /* 434 * NAND Flash Manufacturer ID Codes 435 */ 436 #define NAND_MFR_TOSHIBA 0x98 437 #define NAND_MFR_SAMSUNG 0xec 438 #define NAND_MFR_FUJITSU 0x04 439 #define NAND_MFR_NATIONAL 0x8f 440 #define NAND_MFR_RENESAS 0x07 441 #define NAND_MFR_STMICRO 0x20 442 #define NAND_MFR_HYNIX 0xad 443 #define NAND_MFR_MICRON 0x2c 444 #define NAND_MFR_AMD 0x01 445 446 /** 447 * struct nand_flash_dev - NAND Flash Device ID Structure 448 * @name: Identify the device type 449 * @id: device ID code 450 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 451 * If the pagesize is 0, then the real pagesize 452 * and the eraseize are determined from the 453 * extended id bytes in the chip 454 * @erasesize: Size of an erase block in the flash device. 455 * @chipsize: Total chipsize in Mega Bytes 456 * @options: Bitfield to store chip relevant options 457 */ 458 struct nand_flash_dev { 459 char *name; 460 int id; 461 unsigned long pagesize; 462 unsigned long chipsize; 463 unsigned long erasesize; 464 unsigned long options; 465 }; 466 467 /** 468 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 469 * @name: Manufacturer name 470 * @id: manufacturer ID code of device. 471 */ 472 struct nand_manufacturers { 473 int id; 474 char * name; 475 }; 476 477 extern struct nand_flash_dev nand_flash_ids[]; 478 extern struct nand_manufacturers nand_manuf_ids[]; 479 480 #ifndef NAND_MAX_CHIPS 481 #define NAND_MAX_CHIPS 8 482 #endif 483 484 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 485 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 486 extern int nand_default_bbt(struct mtd_info *mtd); 487 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 488 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 489 int allowbbt); 490 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 491 size_t * retlen, uint8_t * buf); 492 493 /* 494 * Constants for oob configuration 495 */ 496 #define NAND_SMALL_BADBLOCK_POS 5 497 #define NAND_LARGE_BADBLOCK_POS 0 498 499 /** 500 * struct platform_nand_chip - chip level device structure 501 * @nr_chips: max. number of chips to scan for 502 * @chip_offset: chip number offset 503 * @nr_partitions: number of partitions pointed to by partitions (or zero) 504 * @partitions: mtd partition list 505 * @chip_delay: R/B delay value in us 506 * @options: Option flags, e.g. 16bit buswidth 507 * @ecclayout: ecc layout info structure 508 * @part_probe_types: NULL-terminated array of probe types 509 * @priv: hardware controller specific settings 510 */ 511 struct platform_nand_chip { 512 int nr_chips; 513 int chip_offset; 514 int nr_partitions; 515 struct mtd_partition *partitions; 516 struct nand_ecclayout *ecclayout; 517 int chip_delay; 518 unsigned int options; 519 const char **part_probe_types; 520 void *priv; 521 }; 522 523 /** 524 * struct platform_nand_ctrl - controller level device structure 525 * @hwcontrol: platform specific hardware control structure 526 * @dev_ready: platform specific function to read ready/busy pin 527 * @select_chip: platform specific chip select function 528 * @cmd_ctrl: platform specific function for controlling 529 * ALE/CLE/nCE. Also used to write command and address 530 * @priv: private data to transport driver specific settings 531 * 532 * All fields are optional and depend on the hardware driver requirements 533 */ 534 struct platform_nand_ctrl { 535 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 536 int (*dev_ready)(struct mtd_info *mtd); 537 void (*select_chip)(struct mtd_info *mtd, int chip); 538 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, 539 unsigned int ctrl); 540 void *priv; 541 }; 542 543 /** 544 * struct platform_nand_data - container structure for platform-specific data 545 * @chip: chip level chip structure 546 * @ctrl: controller level device structure 547 */ 548 struct platform_nand_data { 549 struct platform_nand_chip chip; 550 struct platform_nand_ctrl ctrl; 551 }; 552 553 /* Some helpers to access the data structures */ 554 static inline 555 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 556 { 557 struct nand_chip *chip = mtd->priv; 558 559 return chip->priv; 560 } 561 562 #endif /* __LINUX_MTD_NAND_H */ 563