1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include "config.h" 22 23 #include "linux/compat.h" 24 #include "linux/mtd/mtd.h" 25 #include "linux/mtd/bbm.h" 26 27 28 struct mtd_info; 29 struct nand_flash_dev; 30 /* Scan and identify a NAND device */ 31 extern int nand_scan (struct mtd_info *mtd, int max_chips); 32 /* Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type */ 34 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 35 const struct nand_flash_dev *table); 36 extern int nand_scan_tail(struct mtd_info *mtd); 37 38 /* Free resources held by the NAND device */ 39 extern void nand_release(struct mtd_info *mtd); 40 41 /* Internal helper for board drivers which need to override command function */ 42 extern void nand_wait_ready(struct mtd_info *mtd); 43 44 /* 45 * This constant declares the max. oobsize / page, which 46 * is supported now. If you add a chip with bigger oobsize/page 47 * adjust this accordingly. 48 */ 49 #define NAND_MAX_OOBSIZE 640 50 #define NAND_MAX_PAGESIZE 8192 51 52 /* 53 * Constants for hardware specific CLE/ALE/NCE function 54 * 55 * These are bits which can be or'ed to set/clear multiple 56 * bits in one go. 57 */ 58 /* Select the chip by setting nCE to low */ 59 #define NAND_NCE 0x01 60 /* Select the command latch by setting CLE to high */ 61 #define NAND_CLE 0x02 62 /* Select the address latch by setting ALE to high */ 63 #define NAND_ALE 0x04 64 65 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 66 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 67 #define NAND_CTRL_CHANGE 0x80 68 69 /* 70 * Standard NAND flash commands 71 */ 72 #define NAND_CMD_READ0 0 73 #define NAND_CMD_READ1 1 74 #define NAND_CMD_RNDOUT 5 75 #define NAND_CMD_PAGEPROG 0x10 76 #define NAND_CMD_READOOB 0x50 77 #define NAND_CMD_ERASE1 0x60 78 #define NAND_CMD_STATUS 0x70 79 #define NAND_CMD_STATUS_MULTI 0x71 80 #define NAND_CMD_SEQIN 0x80 81 #define NAND_CMD_RNDIN 0x85 82 #define NAND_CMD_READID 0x90 83 #define NAND_CMD_ERASE2 0xd0 84 #define NAND_CMD_PARAM 0xec 85 #define NAND_CMD_GET_FEATURES 0xee 86 #define NAND_CMD_SET_FEATURES 0xef 87 #define NAND_CMD_RESET 0xff 88 89 #define NAND_CMD_LOCK 0x2a 90 #define NAND_CMD_LOCK_TIGHT 0x2c 91 #define NAND_CMD_UNLOCK1 0x23 92 #define NAND_CMD_UNLOCK2 0x24 93 #define NAND_CMD_LOCK_STATUS 0x7a 94 95 /* Extended commands for large page devices */ 96 #define NAND_CMD_READSTART 0x30 97 #define NAND_CMD_RNDOUTSTART 0xE0 98 #define NAND_CMD_CACHEDPROG 0x15 99 100 /* Extended commands for AG-AND device */ 101 /* 102 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 103 * there is no way to distinguish that from NAND_CMD_READ0 104 * until the remaining sequence of commands has been completed 105 * so add a high order bit and mask it off in the command. 106 */ 107 #define NAND_CMD_DEPLETE1 0x100 108 #define NAND_CMD_DEPLETE2 0x38 109 #define NAND_CMD_STATUS_MULTI 0x71 110 #define NAND_CMD_STATUS_ERROR 0x72 111 /* multi-bank error status (banks 0-3) */ 112 #define NAND_CMD_STATUS_ERROR0 0x73 113 #define NAND_CMD_STATUS_ERROR1 0x74 114 #define NAND_CMD_STATUS_ERROR2 0x75 115 #define NAND_CMD_STATUS_ERROR3 0x76 116 #define NAND_CMD_STATUS_RESET 0x7f 117 #define NAND_CMD_STATUS_CLEAR 0xff 118 119 #define NAND_CMD_NONE -1 120 121 /* Status bits */ 122 #define NAND_STATUS_FAIL 0x01 123 #define NAND_STATUS_FAIL_N1 0x02 124 #define NAND_STATUS_TRUE_READY 0x20 125 #define NAND_STATUS_READY 0x40 126 #define NAND_STATUS_WP 0x80 127 128 /* 129 * Constants for ECC_MODES 130 */ 131 typedef enum { 132 NAND_ECC_NONE, 133 NAND_ECC_SOFT, 134 NAND_ECC_HW, 135 NAND_ECC_HW_SYNDROME, 136 NAND_ECC_HW_OOB_FIRST, 137 NAND_ECC_SOFT_BCH, 138 } nand_ecc_modes_t; 139 140 /* 141 * Constants for Hardware ECC 142 */ 143 /* Reset Hardware ECC for read */ 144 #define NAND_ECC_READ 0 145 /* Reset Hardware ECC for write */ 146 #define NAND_ECC_WRITE 1 147 /* Enable Hardware ECC before syndrome is read back from flash */ 148 #define NAND_ECC_READSYN 2 149 150 /* Bit mask for flags passed to do_nand_read_ecc */ 151 #define NAND_GET_DEVICE 0x80 152 153 154 /* 155 * Option constants for bizarre disfunctionality and real 156 * features. 157 */ 158 /* Buswidth is 16 bit */ 159 #define NAND_BUSWIDTH_16 0x00000002 160 /* Device supports partial programming without padding */ 161 #define NAND_NO_PADDING 0x00000004 162 /* Chip has cache program function */ 163 #define NAND_CACHEPRG 0x00000008 164 /* Chip has copy back function */ 165 #define NAND_COPYBACK 0x00000010 166 /* 167 * AND Chip which has 4 banks and a confusing page / block 168 * assignment. See Renesas datasheet for further information. 169 */ 170 #define NAND_IS_AND 0x00000020 171 /* 172 * Chip has a array of 4 pages which can be read without 173 * additional ready /busy waits. 174 */ 175 #define NAND_4PAGE_ARRAY 0x00000040 176 /* 177 * Chip requires that BBT is periodically rewritten to prevent 178 * bits from adjacent blocks from 'leaking' in altering data. 179 * This happens with the Renesas AG-AND chips, possibly others. 180 */ 181 #define BBT_AUTO_REFRESH 0x00000080 182 /* Chip does not allow subpage writes */ 183 #define NAND_NO_SUBPAGE_WRITE 0x00000200 184 185 /* Device is one of 'new' xD cards that expose fake nand command set */ 186 #define NAND_BROKEN_XD 0x00000400 187 188 /* Device behaves just like nand, but is readonly */ 189 #define NAND_ROM 0x00000800 190 191 /* Device supports subpage reads */ 192 #define NAND_SUBPAGE_READ 0x00001000 193 194 /* Options valid for Samsung large page devices */ 195 #define NAND_SAMSUNG_LP_OPTIONS \ 196 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 197 198 /* Macros to identify the above */ 199 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 200 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 201 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 202 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 203 204 /* Non chip related options */ 205 /* This option skips the bbt scan during initialization. */ 206 #define NAND_SKIP_BBTSCAN 0x00010000 207 /* 208 * This option is defined if the board driver allocates its own buffers 209 * (e.g. because it needs them DMA-coherent). 210 */ 211 #define NAND_OWN_BUFFERS 0x00020000 212 /* Chip may not exist, so silence any errors in scan */ 213 #define NAND_SCAN_SILENT_NODEV 0x00040000 214 215 /* Options set by nand scan */ 216 /* bbt has already been read */ 217 #define NAND_BBT_SCANNED 0x40000000 218 /* Nand scan has allocated controller struct */ 219 #define NAND_CONTROLLER_ALLOC 0x80000000 220 221 /* Cell info constants */ 222 #define NAND_CI_CHIPNR_MSK 0x03 223 #define NAND_CI_CELLTYPE_MSK 0x0C 224 225 /* Keep gcc happy */ 226 struct nand_chip; 227 228 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 229 #define ONFI_TIMING_MODE_0 (1 << 0) 230 #define ONFI_TIMING_MODE_1 (1 << 1) 231 #define ONFI_TIMING_MODE_2 (1 << 2) 232 #define ONFI_TIMING_MODE_3 (1 << 3) 233 #define ONFI_TIMING_MODE_4 (1 << 4) 234 #define ONFI_TIMING_MODE_5 (1 << 5) 235 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 236 237 /* ONFI feature address */ 238 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 239 240 /* ONFI subfeature parameters length */ 241 #define ONFI_SUBFEATURE_PARAM_LEN 4 242 243 struct nand_onfi_params { 244 /* rev info and features block */ 245 /* 'O' 'N' 'F' 'I' */ 246 u8 sig[4]; 247 __le16 revision; 248 __le16 features; 249 __le16 opt_cmd; 250 u8 reserved[22]; 251 252 /* manufacturer information block */ 253 char manufacturer[12]; 254 char model[20]; 255 u8 jedec_id; 256 __le16 date_code; 257 u8 reserved2[13]; 258 259 /* memory organization block */ 260 __le32 byte_per_page; 261 __le16 spare_bytes_per_page; 262 __le32 data_bytes_per_ppage; 263 __le16 spare_bytes_per_ppage; 264 __le32 pages_per_block; 265 __le32 blocks_per_lun; 266 u8 lun_count; 267 u8 addr_cycles; 268 u8 bits_per_cell; 269 __le16 bb_per_lun; 270 __le16 block_endurance; 271 u8 guaranteed_good_blocks; 272 __le16 guaranteed_block_endurance; 273 u8 programs_per_page; 274 u8 ppage_attr; 275 u8 ecc_bits; 276 u8 interleaved_bits; 277 u8 interleaved_ops; 278 u8 reserved3[13]; 279 280 /* electrical parameter block */ 281 u8 io_pin_capacitance_max; 282 __le16 async_timing_mode; 283 __le16 program_cache_timing_mode; 284 __le16 t_prog; 285 __le16 t_bers; 286 __le16 t_r; 287 __le16 t_ccs; 288 __le16 src_sync_timing_mode; 289 __le16 src_ssync_features; 290 __le16 clk_pin_capacitance_typ; 291 __le16 io_pin_capacitance_typ; 292 __le16 input_pin_capacitance_typ; 293 u8 input_pin_capacitance_max; 294 u8 driver_strenght_support; 295 __le16 t_int_r; 296 __le16 t_ald; 297 u8 reserved4[7]; 298 299 /* vendor */ 300 u8 reserved5[90]; 301 302 __le16 crc; 303 } __attribute__((packed)); 304 305 #define ONFI_CRC_BASE 0x4F4E 306 307 /** 308 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 309 * @lock: protection lock 310 * @active: the mtd device which holds the controller currently 311 * @wq: wait queue to sleep on if a NAND operation is in 312 * progress used instead of the per chip wait queue 313 * when a hw controller is available. 314 */ 315 struct nand_hw_control { 316 /* XXX U-BOOT XXX */ 317 #if 0 318 spinlock_t lock; 319 wait_queue_head_t wq; 320 #endif 321 struct nand_chip *active; 322 }; 323 324 /** 325 * struct nand_ecc_ctrl - Control structure for ECC 326 * @mode: ECC mode 327 * @steps: number of ECC steps per page 328 * @size: data bytes per ECC step 329 * @bytes: ECC bytes per step 330 * @strength: max number of correctible bits per ECC step 331 * @total: total number of ECC bytes per page 332 * @prepad: padding information for syndrome based ECC generators 333 * @postpad: padding information for syndrome based ECC generators 334 * @layout: ECC layout control struct pointer 335 * @priv: pointer to private ECC control data 336 * @hwctl: function to control hardware ECC generator. Must only 337 * be provided if an hardware ECC is available 338 * @calculate: function for ECC calculation or readback from ECC hardware 339 * @correct: function for ECC correction, matching to ECC generator (sw/hw) 340 * @read_page_raw: function to read a raw page without ECC 341 * @write_page_raw: function to write a raw page without ECC 342 * @read_page: function to read a page according to the ECC generator 343 * requirements; returns maximum number of bitflips corrected in 344 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 345 * @read_subpage: function to read parts of the page covered by ECC; 346 * returns same as read_page() 347 * @write_page: function to write a page according to the ECC generator 348 * requirements. 349 * @write_oob_raw: function to write chip OOB data without ECC 350 * @read_oob_raw: function to read chip OOB data without ECC 351 * @read_oob: function to read chip OOB data 352 * @write_oob: function to write chip OOB data 353 */ 354 struct nand_ecc_ctrl { 355 nand_ecc_modes_t mode; 356 int steps; 357 int size; 358 int bytes; 359 int total; 360 int strength; 361 int prepad; 362 int postpad; 363 struct nand_ecclayout *layout; 364 void *priv; 365 void (*hwctl)(struct mtd_info *mtd, int mode); 366 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 367 uint8_t *ecc_code); 368 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 369 uint8_t *calc_ecc); 370 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 371 uint8_t *buf, int oob_required, int page); 372 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 373 const uint8_t *buf, int oob_required); 374 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 375 uint8_t *buf, int oob_required, int page); 376 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 377 uint32_t offs, uint32_t len, uint8_t *buf); 378 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 379 const uint8_t *buf, int oob_required); 380 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 381 int page); 382 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 383 int page); 384 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 385 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 386 int page); 387 }; 388 389 /** 390 * struct nand_buffers - buffer structure for read/write 391 * @ecccalc: buffer for calculated ECC 392 * @ecccode: buffer for ECC read from flash 393 * @databuf: buffer for data - dynamically sized 394 * 395 * Do not change the order of buffers. databuf and oobrbuf must be in 396 * consecutive order. 397 */ 398 struct nand_buffers { 399 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 400 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 401 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 402 ARCH_DMA_MINALIGN)]; 403 }; 404 405 /** 406 * struct nand_chip - NAND Private Flash Chip Data 407 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 408 * flash device 409 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 410 * flash device. 411 * @read_byte: [REPLACEABLE] read one byte from the chip 412 * @read_word: [REPLACEABLE] read one word from the chip 413 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 414 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 415 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip 416 * data. 417 * @select_chip: [REPLACEABLE] select chip nr 418 * @block_bad: [REPLACEABLE] check, if the block is bad 419 * @block_markbad: [REPLACEABLE] mark the block bad 420 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 421 * ALE/CLE/nCE. Also used to write command and address 422 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting 423 * mtd->oobsize, mtd->writesize and so on. 424 * @id_data contains the 8 bytes values of NAND_CMD_READID. 425 * Return with the bus width. 426 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 427 * device ready/busy line. If set to NULL no access to 428 * ready/busy is available and the ready/busy information 429 * is read from the chip status register. 430 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 431 * commands to the chip. 432 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 433 * ready. 434 * @ecc: [BOARDSPECIFIC] ECC control structure 435 * @buffers: buffer structure for read/write 436 * @hwcontrol: platform-specific hardware control structure 437 * @erase_cmd: [INTERN] erase command write function, selectable due 438 * to AND support. 439 * @scan_bbt: [REPLACEABLE] function to scan bad block table 440 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 441 * data from array to read regs (tR). 442 * @state: [INTERN] the current state of the NAND device 443 * @oob_poi: "poison value buffer," used for laying out OOB data 444 * before writing 445 * @page_shift: [INTERN] number of address bits in a page (column 446 * address bits). 447 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 448 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 449 * @chip_shift: [INTERN] number of address bits in one chip 450 * @options: [BOARDSPECIFIC] various chip options. They can partly 451 * be set to inform nand_scan about special functionality. 452 * See the defines for further explanation. 453 * @bbt_options: [INTERN] bad block specific options. All options used 454 * here must come from bbm.h. By default, these options 455 * will be copied to the appropriate nand_bbt_descr's. 456 * @badblockpos: [INTERN] position of the bad block marker in the oob 457 * area. 458 * @badblockbits: [INTERN] minimum number of set bits in a good block's 459 * bad block marker position; i.e., BBM == 11110111b is 460 * not bad when badblockbits == 7 461 * @cellinfo: [INTERN] MLC/multichip data from chip ident 462 * @numchips: [INTERN] number of physical chips 463 * @chipsize: [INTERN] the size of one chip for multichip arrays 464 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 465 * @pagebuf: [INTERN] holds the pagenumber which is currently in 466 * data_buf. 467 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 468 * currently in data_buf. 469 * @subpagesize: [INTERN] holds the subpagesize 470 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 471 * non 0 if ONFI supported. 472 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 473 * supported, 0 otherwise. 474 * @onfi_set_features [REPLACEABLE] set the features for ONFI nand 475 * @onfi_get_features [REPLACEABLE] get the features for ONFI nand 476 * @ecclayout: [REPLACEABLE] the default ECC placement scheme 477 * @bbt: [INTERN] bad block table pointer 478 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 479 * lookup. 480 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 481 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 482 * bad block scan. 483 * @controller: [REPLACEABLE] a pointer to a hardware controller 484 * structure which is shared among multiple independent 485 * devices. 486 * @priv: [OPTIONAL] pointer to private chip data 487 * @errstat: [OPTIONAL] hardware specific function to perform 488 * additional error status checks (determine if errors are 489 * correctable). 490 * @write_page: [REPLACEABLE] High-level page write function 491 */ 492 493 struct nand_chip { 494 void __iomem *IO_ADDR_R; 495 void __iomem *IO_ADDR_W; 496 497 uint8_t (*read_byte)(struct mtd_info *mtd); 498 u16 (*read_word)(struct mtd_info *mtd); 499 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 500 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 501 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 502 void (*select_chip)(struct mtd_info *mtd, int chip); 503 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 504 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 505 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 506 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, 507 u8 *id_data); 508 int (*dev_ready)(struct mtd_info *mtd); 509 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 510 int page_addr); 511 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 512 void (*erase_cmd)(struct mtd_info *mtd, int page); 513 int (*scan_bbt)(struct mtd_info *mtd); 514 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 515 int status, int page); 516 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 517 const uint8_t *buf, int oob_required, int page, 518 int cached, int raw); 519 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 520 int feature_addr, uint8_t *subfeature_para); 521 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 522 int feature_addr, uint8_t *subfeature_para); 523 524 int chip_delay; 525 unsigned int options; 526 unsigned int bbt_options; 527 528 int page_shift; 529 int phys_erase_shift; 530 int bbt_erase_shift; 531 int chip_shift; 532 int numchips; 533 uint64_t chipsize; 534 int pagemask; 535 int pagebuf; 536 unsigned int pagebuf_bitflips; 537 int subpagesize; 538 uint8_t cellinfo; 539 int badblockpos; 540 int badblockbits; 541 542 int onfi_version; 543 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 544 struct nand_onfi_params onfi_params; 545 #endif 546 547 int state; 548 549 uint8_t *oob_poi; 550 struct nand_hw_control *controller; 551 struct nand_ecclayout *ecclayout; 552 553 struct nand_ecc_ctrl ecc; 554 struct nand_buffers *buffers; 555 struct nand_hw_control hwcontrol; 556 557 uint8_t *bbt; 558 struct nand_bbt_descr *bbt_td; 559 struct nand_bbt_descr *bbt_md; 560 561 struct nand_bbt_descr *badblock_pattern; 562 563 void *priv; 564 }; 565 566 /* 567 * NAND Flash Manufacturer ID Codes 568 */ 569 #define NAND_MFR_TOSHIBA 0x98 570 #define NAND_MFR_SAMSUNG 0xec 571 #define NAND_MFR_FUJITSU 0x04 572 #define NAND_MFR_NATIONAL 0x8f 573 #define NAND_MFR_RENESAS 0x07 574 #define NAND_MFR_STMICRO 0x20 575 #define NAND_MFR_HYNIX 0xad 576 #define NAND_MFR_MICRON 0x2c 577 #define NAND_MFR_AMD 0x01 578 #define NAND_MFR_MACRONIX 0xc2 579 #define NAND_MFR_EON 0x92 580 581 /** 582 * struct nand_flash_dev - NAND Flash Device ID Structure 583 * @name: Identify the device type 584 * @id: device ID code 585 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 586 * If the pagesize is 0, then the real pagesize 587 * and the eraseize are determined from the 588 * extended id bytes in the chip 589 * @erasesize: Size of an erase block in the flash device. 590 * @chipsize: Total chipsize in Mega Bytes 591 * @options: Bitfield to store chip relevant options 592 */ 593 struct nand_flash_dev { 594 char *name; 595 int id; 596 unsigned long pagesize; 597 unsigned long chipsize; 598 unsigned long erasesize; 599 unsigned long options; 600 }; 601 602 /** 603 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 604 * @name: Manufacturer name 605 * @id: manufacturer ID code of device. 606 */ 607 struct nand_manufacturers { 608 int id; 609 char *name; 610 }; 611 612 extern const struct nand_flash_dev nand_flash_ids[]; 613 extern const struct nand_manufacturers nand_manuf_ids[]; 614 615 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 616 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 617 extern int nand_default_bbt(struct mtd_info *mtd); 618 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 619 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 620 int allowbbt); 621 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 622 size_t *retlen, uint8_t *buf); 623 624 /* 625 * Constants for oob configuration 626 */ 627 #define NAND_SMALL_BADBLOCK_POS 5 628 #define NAND_LARGE_BADBLOCK_POS 0 629 630 /** 631 * struct platform_nand_chip - chip level device structure 632 * @nr_chips: max. number of chips to scan for 633 * @chip_offset: chip number offset 634 * @nr_partitions: number of partitions pointed to by partitions (or zero) 635 * @partitions: mtd partition list 636 * @chip_delay: R/B delay value in us 637 * @options: Option flags, e.g. 16bit buswidth 638 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 639 * @ecclayout: ECC layout info structure 640 * @part_probe_types: NULL-terminated array of probe types 641 */ 642 struct platform_nand_chip { 643 int nr_chips; 644 int chip_offset; 645 int nr_partitions; 646 struct mtd_partition *partitions; 647 struct nand_ecclayout *ecclayout; 648 int chip_delay; 649 unsigned int options; 650 unsigned int bbt_options; 651 const char **part_probe_types; 652 }; 653 654 /* Keep gcc happy */ 655 struct platform_device; 656 657 /** 658 * struct platform_nand_ctrl - controller level device structure 659 * @hwcontrol: platform specific hardware control structure 660 * @dev_ready: platform specific function to read ready/busy pin 661 * @select_chip: platform specific chip select function 662 * @cmd_ctrl: platform specific function for controlling 663 * ALE/CLE/nCE. Also used to write command and address 664 * @priv: private data to transport driver specific settings 665 * 666 * All fields are optional and depend on the hardware driver requirements 667 */ 668 struct platform_nand_ctrl { 669 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 670 int (*dev_ready)(struct mtd_info *mtd); 671 void (*select_chip)(struct mtd_info *mtd, int chip); 672 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 673 unsigned char (*read_byte)(struct mtd_info *mtd); 674 void *priv; 675 }; 676 677 /** 678 * struct platform_nand_data - container structure for platform-specific data 679 * @chip: chip level chip structure 680 * @ctrl: controller level device structure 681 */ 682 struct platform_nand_data { 683 struct platform_nand_chip chip; 684 struct platform_nand_ctrl ctrl; 685 }; 686 687 /* Some helpers to access the data structures */ 688 static inline 689 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 690 { 691 struct nand_chip *chip = mtd->priv; 692 693 return chip->priv; 694 } 695 696 /* Standard NAND functions from nand_base.c */ 697 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 698 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 699 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 700 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 701 uint8_t nand_read_byte(struct mtd_info *mtd); 702 703 /* return the supported asynchronous timing mode. */ 704 705 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 706 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 707 { 708 if (!chip->onfi_version) 709 return ONFI_TIMING_MODE_UNKNOWN; 710 return le16_to_cpu(chip->onfi_params.async_timing_mode); 711 } 712 713 /* return the supported synchronous timing mode. */ 714 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 715 { 716 if (!chip->onfi_version) 717 return ONFI_TIMING_MODE_UNKNOWN; 718 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 719 } 720 #endif 721 722 /** 723 * Check if the opcode's address should be sent only on the lower 8 bits 724 * @command: opcode to check 725 */ 726 static inline int nand_opcode_8bits(unsigned int command) 727 { 728 switch (command) { 729 case NAND_CMD_READID: 730 case NAND_CMD_PARAM: 731 case NAND_CMD_GET_FEATURES: 732 case NAND_CMD_SET_FEATURES: 733 return 1; 734 default: 735 break; 736 } 737 return 0; 738 } 739 740 741 #endif /* __LINUX_MTD_NAND_H */ 742