1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include "config.h" 22 23 #include "linux/compat.h" 24 #include "linux/mtd/mtd.h" 25 #include "linux/mtd/bbm.h" 26 27 28 struct mtd_info; 29 struct nand_flash_dev; 30 /* Scan and identify a NAND device */ 31 extern int nand_scan (struct mtd_info *mtd, int max_chips); 32 /* Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type */ 34 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 35 const struct nand_flash_dev *table); 36 extern int nand_scan_tail(struct mtd_info *mtd); 37 38 /* Free resources held by the NAND device */ 39 extern void nand_release(struct mtd_info *mtd); 40 41 /* Internal helper for board drivers which need to override command function */ 42 extern void nand_wait_ready(struct mtd_info *mtd); 43 44 /* 45 * This constant declares the max. oobsize / page, which 46 * is supported now. If you add a chip with bigger oobsize/page 47 * adjust this accordingly. 48 */ 49 #define NAND_MAX_OOBSIZE 576 50 #define NAND_MAX_PAGESIZE 8192 51 52 /* 53 * Constants for hardware specific CLE/ALE/NCE function 54 * 55 * These are bits which can be or'ed to set/clear multiple 56 * bits in one go. 57 */ 58 /* Select the chip by setting nCE to low */ 59 #define NAND_NCE 0x01 60 /* Select the command latch by setting CLE to high */ 61 #define NAND_CLE 0x02 62 /* Select the address latch by setting ALE to high */ 63 #define NAND_ALE 0x04 64 65 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 66 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 67 #define NAND_CTRL_CHANGE 0x80 68 69 /* 70 * Standard NAND flash commands 71 */ 72 #define NAND_CMD_READ0 0 73 #define NAND_CMD_READ1 1 74 #define NAND_CMD_RNDOUT 5 75 #define NAND_CMD_PAGEPROG 0x10 76 #define NAND_CMD_READOOB 0x50 77 #define NAND_CMD_ERASE1 0x60 78 #define NAND_CMD_STATUS 0x70 79 #define NAND_CMD_STATUS_MULTI 0x71 80 #define NAND_CMD_SEQIN 0x80 81 #define NAND_CMD_RNDIN 0x85 82 #define NAND_CMD_READID 0x90 83 #define NAND_CMD_ERASE2 0xd0 84 #define NAND_CMD_PARAM 0xec 85 #define NAND_CMD_RESET 0xff 86 87 #define NAND_CMD_LOCK 0x2a 88 #define NAND_CMD_LOCK_TIGHT 0x2c 89 #define NAND_CMD_UNLOCK1 0x23 90 #define NAND_CMD_UNLOCK2 0x24 91 #define NAND_CMD_LOCK_STATUS 0x7a 92 93 /* Extended commands for large page devices */ 94 #define NAND_CMD_READSTART 0x30 95 #define NAND_CMD_RNDOUTSTART 0xE0 96 #define NAND_CMD_CACHEDPROG 0x15 97 98 /* Extended commands for AG-AND device */ 99 /* 100 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 101 * there is no way to distinguish that from NAND_CMD_READ0 102 * until the remaining sequence of commands has been completed 103 * so add a high order bit and mask it off in the command. 104 */ 105 #define NAND_CMD_DEPLETE1 0x100 106 #define NAND_CMD_DEPLETE2 0x38 107 #define NAND_CMD_STATUS_MULTI 0x71 108 #define NAND_CMD_STATUS_ERROR 0x72 109 /* multi-bank error status (banks 0-3) */ 110 #define NAND_CMD_STATUS_ERROR0 0x73 111 #define NAND_CMD_STATUS_ERROR1 0x74 112 #define NAND_CMD_STATUS_ERROR2 0x75 113 #define NAND_CMD_STATUS_ERROR3 0x76 114 #define NAND_CMD_STATUS_RESET 0x7f 115 #define NAND_CMD_STATUS_CLEAR 0xff 116 117 #define NAND_CMD_NONE -1 118 119 /* Status bits */ 120 #define NAND_STATUS_FAIL 0x01 121 #define NAND_STATUS_FAIL_N1 0x02 122 #define NAND_STATUS_TRUE_READY 0x20 123 #define NAND_STATUS_READY 0x40 124 #define NAND_STATUS_WP 0x80 125 126 /* 127 * Constants for ECC_MODES 128 */ 129 typedef enum { 130 NAND_ECC_NONE, 131 NAND_ECC_SOFT, 132 NAND_ECC_HW, 133 NAND_ECC_HW_SYNDROME, 134 NAND_ECC_HW_OOB_FIRST, 135 NAND_ECC_SOFT_BCH, 136 } nand_ecc_modes_t; 137 138 /* 139 * Constants for Hardware ECC 140 */ 141 /* Reset Hardware ECC for read */ 142 #define NAND_ECC_READ 0 143 /* Reset Hardware ECC for write */ 144 #define NAND_ECC_WRITE 1 145 /* Enable Hardware ECC before syndrom is read back from flash */ 146 #define NAND_ECC_READSYN 2 147 148 /* Bit mask for flags passed to do_nand_read_ecc */ 149 #define NAND_GET_DEVICE 0x80 150 151 152 /* 153 * Option constants for bizarre disfunctionality and real 154 * features. 155 */ 156 /* Chip can not auto increment pages */ 157 #define NAND_NO_AUTOINCR 0x00000001 158 /* Buswitdh is 16 bit */ 159 #define NAND_BUSWIDTH_16 0x00000002 160 /* Device supports partial programming without padding */ 161 #define NAND_NO_PADDING 0x00000004 162 /* Chip has cache program function */ 163 #define NAND_CACHEPRG 0x00000008 164 /* Chip has copy back function */ 165 #define NAND_COPYBACK 0x00000010 166 /* 167 * AND Chip which has 4 banks and a confusing page / block 168 * assignment. See Renesas datasheet for further information. 169 */ 170 #define NAND_IS_AND 0x00000020 171 /* 172 * Chip has a array of 4 pages which can be read without 173 * additional ready /busy waits. 174 */ 175 #define NAND_4PAGE_ARRAY 0x00000040 176 /* 177 * Chip requires that BBT is periodically rewritten to prevent 178 * bits from adjacent blocks from 'leaking' in altering data. 179 * This happens with the Renesas AG-AND chips, possibly others. 180 */ 181 #define BBT_AUTO_REFRESH 0x00000080 182 /* 183 * Chip does not require ready check on read. True 184 * for all large page devices, as they do not support 185 * autoincrement. 186 */ 187 #define NAND_NO_READRDY 0x00000100 188 /* Chip does not allow subpage writes */ 189 #define NAND_NO_SUBPAGE_WRITE 0x00000200 190 191 /* Device is one of 'new' xD cards that expose fake nand command set */ 192 #define NAND_BROKEN_XD 0x00000400 193 194 /* Device behaves just like nand, but is readonly */ 195 #define NAND_ROM 0x00000800 196 197 /* Options valid for Samsung large page devices */ 198 #define NAND_SAMSUNG_LP_OPTIONS \ 199 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 200 201 /* Macros to identify the above */ 202 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) 203 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 204 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 205 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 206 /* Large page NAND with SOFT_ECC should support subpage reads */ 207 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ 208 && (chip->page_shift > 9)) 209 210 /* Non chip related options */ 211 /* 212 * Use a flash based bad block table. OOB identifier is saved in OOB area. 213 * This option is passed to the default bad block table function. 214 */ 215 #define NAND_USE_FLASH_BBT 0x00010000 216 /* This option skips the bbt scan during initialization. */ 217 #define NAND_SKIP_BBTSCAN 0x00020000 218 /* 219 * This option is defined if the board driver allocates its own buffers 220 * (e.g. because it needs them DMA-coherent). 221 */ 222 #define NAND_OWN_BUFFERS 0x00040000 223 /* Chip may not exist, so silence any errors in scan */ 224 #define NAND_SCAN_SILENT_NODEV 0x00080000 225 /* 226 * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch 227 * the OOB area. 228 */ 229 #define NAND_USE_FLASH_BBT_NO_OOB 0x00800000 230 /* Create an empty BBT with no vendor information if the BBT is available */ 231 #define NAND_CREATE_EMPTY_BBT 0x01000000 232 233 /* Options set by nand scan */ 234 /* bbt has already been read */ 235 #define NAND_BBT_SCANNED 0x40000000 236 /* Nand scan has allocated controller struct */ 237 #define NAND_CONTROLLER_ALLOC 0x80000000 238 239 /* Cell info constants */ 240 #define NAND_CI_CHIPNR_MSK 0x03 241 #define NAND_CI_CELLTYPE_MSK 0x0C 242 243 /* Keep gcc happy */ 244 struct nand_chip; 245 246 struct nand_onfi_params { 247 /* rev info and features block */ 248 /* 'O' 'N' 'F' 'I' */ 249 u8 sig[4]; 250 __le16 revision; 251 __le16 features; 252 __le16 opt_cmd; 253 u8 reserved[22]; 254 255 /* manufacturer information block */ 256 char manufacturer[12]; 257 char model[20]; 258 u8 jedec_id; 259 __le16 date_code; 260 u8 reserved2[13]; 261 262 /* memory organization block */ 263 __le32 byte_per_page; 264 __le16 spare_bytes_per_page; 265 __le32 data_bytes_per_ppage; 266 __le16 spare_bytes_per_ppage; 267 __le32 pages_per_block; 268 __le32 blocks_per_lun; 269 u8 lun_count; 270 u8 addr_cycles; 271 u8 bits_per_cell; 272 __le16 bb_per_lun; 273 __le16 block_endurance; 274 u8 guaranteed_good_blocks; 275 __le16 guaranteed_block_endurance; 276 u8 programs_per_page; 277 u8 ppage_attr; 278 u8 ecc_bits; 279 u8 interleaved_bits; 280 u8 interleaved_ops; 281 u8 reserved3[13]; 282 283 /* electrical parameter block */ 284 u8 io_pin_capacitance_max; 285 __le16 async_timing_mode; 286 __le16 program_cache_timing_mode; 287 __le16 t_prog; 288 __le16 t_bers; 289 __le16 t_r; 290 __le16 t_ccs; 291 __le16 src_sync_timing_mode; 292 __le16 src_ssync_features; 293 __le16 clk_pin_capacitance_typ; 294 __le16 io_pin_capacitance_typ; 295 __le16 input_pin_capacitance_typ; 296 u8 input_pin_capacitance_max; 297 u8 driver_strenght_support; 298 __le16 t_int_r; 299 __le16 t_ald; 300 u8 reserved4[7]; 301 302 /* vendor */ 303 u8 reserved5[90]; 304 305 __le16 crc; 306 } __attribute__((packed)); 307 308 #define ONFI_CRC_BASE 0x4F4E 309 310 /** 311 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 312 * @lock: protection lock 313 * @active: the mtd device which holds the controller currently 314 * @wq: wait queue to sleep on if a NAND operation is in 315 * progress used instead of the per chip wait queue 316 * when a hw controller is available. 317 */ 318 struct nand_hw_control { 319 /* XXX U-BOOT XXX */ 320 #if 0 321 spinlock_t lock; 322 wait_queue_head_t wq; 323 #endif 324 struct nand_chip *active; 325 }; 326 327 /** 328 * struct nand_ecc_ctrl - Control structure for ecc 329 * @mode: ecc mode 330 * @steps: number of ecc steps per page 331 * @size: data bytes per ecc step 332 * @bytes: ecc bytes per step 333 * @total: total number of ecc bytes per page 334 * @prepad: padding information for syndrome based ecc generators 335 * @postpad: padding information for syndrome based ecc generators 336 * @layout: ECC layout control struct pointer 337 * @priv: pointer to private ecc control data 338 * @hwctl: function to control hardware ecc generator. Must only 339 * be provided if an hardware ECC is available 340 * @calculate: function for ecc calculation or readback from ecc hardware 341 * @correct: function for ecc correction, matching to ecc generator (sw/hw) 342 * @read_page_raw: function to read a raw page without ECC 343 * @write_page_raw: function to write a raw page without ECC 344 * @read_page: function to read a page according to the ecc generator 345 * requirements. 346 * @read_subpage: function to read parts of the page covered by ECC. 347 * @write_page: function to write a page according to the ecc generator 348 * requirements. 349 * @read_oob: function to read chip OOB data 350 * @write_oob: function to write chip OOB data 351 */ 352 struct nand_ecc_ctrl { 353 nand_ecc_modes_t mode; 354 int steps; 355 int size; 356 int bytes; 357 int total; 358 int prepad; 359 int postpad; 360 struct nand_ecclayout *layout; 361 void *priv; 362 void (*hwctl)(struct mtd_info *mtd, int mode); 363 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 364 uint8_t *ecc_code); 365 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 366 uint8_t *calc_ecc); 367 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 368 uint8_t *buf, int page); 369 void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 370 const uint8_t *buf); 371 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 372 uint8_t *buf, int page); 373 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 374 uint32_t offs, uint32_t len, uint8_t *buf); 375 void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 376 const uint8_t *buf); 377 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page, 378 int sndcmd); 379 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 380 int page); 381 }; 382 383 /** 384 * struct nand_buffers - buffer structure for read/write 385 * @ecccalc: buffer for calculated ecc 386 * @ecccode: buffer for ecc read from flash 387 * @databuf: buffer for data - dynamically sized 388 * 389 * Do not change the order of buffers. databuf and oobrbuf must be in 390 * consecutive order. 391 */ 392 struct nand_buffers { 393 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 394 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 395 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 396 ARCH_DMA_MINALIGN)]; 397 }; 398 399 /** 400 * struct nand_chip - NAND Private Flash Chip Data 401 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 402 * flash device 403 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 404 * flash device. 405 * @read_byte: [REPLACEABLE] read one byte from the chip 406 * @read_word: [REPLACEABLE] read one word from the chip 407 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 408 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 409 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip 410 * data. 411 * @select_chip: [REPLACEABLE] select chip nr 412 * @block_bad: [REPLACEABLE] check, if the block is bad 413 * @block_markbad: [REPLACEABLE] mark the block bad 414 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 415 * ALE/CLE/nCE. Also used to write command and address 416 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting 417 * mtd->oobsize, mtd->writesize and so on. 418 * @id_data contains the 8 bytes values of NAND_CMD_READID. 419 * Return with the bus width. 420 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing 421 * device ready/busy line. If set to NULL no access to 422 * ready/busy is available and the ready/busy information 423 * is read from the chip status register. 424 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 425 * commands to the chip. 426 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 427 * ready. 428 * @ecc: [BOARDSPECIFIC] ecc control ctructure 429 * @buffers: buffer structure for read/write 430 * @hwcontrol: platform-specific hardware control structure 431 * @ops: oob operation operands 432 * @erase_cmd: [INTERN] erase command write function, selectable due 433 * to AND support. 434 * @scan_bbt: [REPLACEABLE] function to scan bad block table 435 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 436 * data from array to read regs (tR). 437 * @state: [INTERN] the current state of the NAND device 438 * @oob_poi: poison value buffer 439 * @page_shift: [INTERN] number of address bits in a page (column 440 * address bits). 441 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 442 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 443 * @chip_shift: [INTERN] number of address bits in one chip 444 * @options: [BOARDSPECIFIC] various chip options. They can partly 445 * be set to inform nand_scan about special functionality. 446 * See the defines for further explanation. 447 * @badblockpos: [INTERN] position of the bad block marker in the oob 448 * area. 449 * @badblockbits: [INTERN] number of bits to left-shift the bad block 450 * number 451 * @cellinfo: [INTERN] MLC/multichip data from chip ident 452 * @numchips: [INTERN] number of physical chips 453 * @chipsize: [INTERN] the size of one chip for multichip arrays 454 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 455 * @pagebuf: [INTERN] holds the pagenumber which is currently in 456 * data_buf. 457 * @subpagesize: [INTERN] holds the subpagesize 458 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 459 * non 0 if ONFI supported. 460 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 461 * supported, 0 otherwise. 462 * @ecclayout: [REPLACEABLE] the default ecc placement scheme 463 * @bbt: [INTERN] bad block table pointer 464 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 465 * lookup. 466 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 467 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 468 * bad block scan. 469 * @controller: [REPLACEABLE] a pointer to a hardware controller 470 * structure which is shared among multiple independend 471 * devices. 472 * @priv: [OPTIONAL] pointer to private chip date 473 * @errstat: [OPTIONAL] hardware specific function to perform 474 * additional error status checks (determine if errors are 475 * correctable). 476 * @write_page: [REPLACEABLE] High-level page write function 477 */ 478 479 struct nand_chip { 480 void __iomem *IO_ADDR_R; 481 void __iomem *IO_ADDR_W; 482 483 uint8_t (*read_byte)(struct mtd_info *mtd); 484 u16 (*read_word)(struct mtd_info *mtd); 485 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 486 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 487 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 488 void (*select_chip)(struct mtd_info *mtd, int chip); 489 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 490 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 491 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 492 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, 493 u8 *id_data); 494 int (*dev_ready)(struct mtd_info *mtd); 495 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 496 int page_addr); 497 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 498 void (*erase_cmd)(struct mtd_info *mtd, int page); 499 int (*scan_bbt)(struct mtd_info *mtd); 500 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 501 int status, int page); 502 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 503 const uint8_t *buf, int page, int cached, int raw); 504 505 int chip_delay; 506 unsigned int options; 507 508 int page_shift; 509 int phys_erase_shift; 510 int bbt_erase_shift; 511 int chip_shift; 512 int numchips; 513 uint64_t chipsize; 514 int pagemask; 515 int pagebuf; 516 int subpagesize; 517 uint8_t cellinfo; 518 int badblockpos; 519 int badblockbits; 520 521 int onfi_version; 522 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 523 struct nand_onfi_params onfi_params; 524 #endif 525 526 int state; 527 528 uint8_t *oob_poi; 529 struct nand_hw_control *controller; 530 struct nand_ecclayout *ecclayout; 531 532 struct nand_ecc_ctrl ecc; 533 struct nand_buffers *buffers; 534 struct nand_hw_control hwcontrol; 535 536 struct mtd_oob_ops ops; 537 538 uint8_t *bbt; 539 struct nand_bbt_descr *bbt_td; 540 struct nand_bbt_descr *bbt_md; 541 542 struct nand_bbt_descr *badblock_pattern; 543 544 void *priv; 545 }; 546 547 /* 548 * NAND Flash Manufacturer ID Codes 549 */ 550 #define NAND_MFR_TOSHIBA 0x98 551 #define NAND_MFR_SAMSUNG 0xec 552 #define NAND_MFR_FUJITSU 0x04 553 #define NAND_MFR_NATIONAL 0x8f 554 #define NAND_MFR_RENESAS 0x07 555 #define NAND_MFR_STMICRO 0x20 556 #define NAND_MFR_HYNIX 0xad 557 #define NAND_MFR_MICRON 0x2c 558 #define NAND_MFR_AMD 0x01 559 560 /** 561 * struct nand_flash_dev - NAND Flash Device ID Structure 562 * @name: Identify the device type 563 * @id: device ID code 564 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 565 * If the pagesize is 0, then the real pagesize 566 * and the eraseize are determined from the 567 * extended id bytes in the chip 568 * @erasesize: Size of an erase block in the flash device. 569 * @chipsize: Total chipsize in Mega Bytes 570 * @options: Bitfield to store chip relevant options 571 */ 572 struct nand_flash_dev { 573 char *name; 574 int id; 575 unsigned long pagesize; 576 unsigned long chipsize; 577 unsigned long erasesize; 578 unsigned long options; 579 }; 580 581 /** 582 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 583 * @name: Manufacturer name 584 * @id: manufacturer ID code of device. 585 */ 586 struct nand_manufacturers { 587 int id; 588 char *name; 589 }; 590 591 extern const struct nand_flash_dev nand_flash_ids[]; 592 extern const struct nand_manufacturers nand_manuf_ids[]; 593 594 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 595 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 596 extern int nand_default_bbt(struct mtd_info *mtd); 597 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 598 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 599 int allowbbt); 600 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 601 size_t *retlen, uint8_t *buf); 602 603 /* 604 * Constants for oob configuration 605 */ 606 #define NAND_SMALL_BADBLOCK_POS 5 607 #define NAND_LARGE_BADBLOCK_POS 0 608 609 /** 610 * struct platform_nand_chip - chip level device structure 611 * @nr_chips: max. number of chips to scan for 612 * @chip_offset: chip number offset 613 * @nr_partitions: number of partitions pointed to by partitions (or zero) 614 * @partitions: mtd partition list 615 * @chip_delay: R/B delay value in us 616 * @options: Option flags, e.g. 16bit buswidth 617 * @ecclayout: ecc layout info structure 618 * @part_probe_types: NULL-terminated array of probe types 619 * @priv: hardware controller specific settings 620 */ 621 struct platform_nand_chip { 622 int nr_chips; 623 int chip_offset; 624 int nr_partitions; 625 struct mtd_partition *partitions; 626 struct nand_ecclayout *ecclayout; 627 int chip_delay; 628 unsigned int options; 629 const char **part_probe_types; 630 void *priv; 631 }; 632 633 /* Keep gcc happy */ 634 struct platform_device; 635 636 /** 637 * struct platform_nand_ctrl - controller level device structure 638 * @hwcontrol: platform specific hardware control structure 639 * @dev_ready: platform specific function to read ready/busy pin 640 * @select_chip: platform specific chip select function 641 * @cmd_ctrl: platform specific function for controlling 642 * ALE/CLE/nCE. Also used to write command and address 643 * @priv: private data to transport driver specific settings 644 * 645 * All fields are optional and depend on the hardware driver requirements 646 */ 647 struct platform_nand_ctrl { 648 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 649 int (*dev_ready)(struct mtd_info *mtd); 650 void (*select_chip)(struct mtd_info *mtd, int chip); 651 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 652 void *priv; 653 }; 654 655 /** 656 * struct platform_nand_data - container structure for platform-specific data 657 * @chip: chip level chip structure 658 * @ctrl: controller level device structure 659 */ 660 struct platform_nand_data { 661 struct platform_nand_chip chip; 662 struct platform_nand_ctrl ctrl; 663 }; 664 665 /* Some helpers to access the data structures */ 666 static inline 667 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 668 { 669 struct nand_chip *chip = mtd->priv; 670 671 return chip->priv; 672 } 673 674 /* Standard NAND functions from nand_base.c */ 675 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 676 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 677 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 678 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 679 uint8_t nand_read_byte(struct mtd_info *mtd); 680 681 #endif /* __LINUX_MTD_NAND_H */ 682