xref: /openbmc/u-boot/include/linux/mtd/nand.h (revision 419adbfb)
1 /*
2  *  linux/include/linux/mtd/nand.h
3  *
4  *  Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
5  *                     Steven J. Hill <sjhill@realitydiluted.com>
6  *		       Thomas Gleixner <tglx@linutronix.de>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * Info:
13  *	Contains standard defines and IDs for NAND flash devices
14  *
15  * Changelog:
16  *	See git changelog.
17  */
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
20 
21 /* XXX U-BOOT XXX */
22 #if 0
23 #include <linux/wait.h>
24 #include <linux/spinlock.h>
25 #include <linux/mtd/mtd.h>
26 #endif
27 
28 #include "config.h"
29 
30 #include "linux/mtd/compat.h"
31 #include "linux/mtd/mtd.h"
32 #include "linux/mtd/bbm.h"
33 
34 
35 struct mtd_info;
36 struct nand_flash_dev;
37 /* Scan and identify a NAND device */
38 extern int nand_scan (struct mtd_info *mtd, int max_chips);
39 /* Separate phases of nand_scan(), allowing board driver to intervene
40  * and override command or ECC setup according to flash type */
41 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
42 			   const struct nand_flash_dev *table);
43 extern int nand_scan_tail(struct mtd_info *mtd);
44 
45 /* Free resources held by the NAND device */
46 extern void nand_release (struct mtd_info *mtd);
47 
48 /* Internal helper for board drivers which need to override command function */
49 extern void nand_wait_ready(struct mtd_info *mtd);
50 
51 /* This constant declares the max. oobsize / page, which
52  * is supported now. If you add a chip with bigger oobsize/page
53  * adjust this accordingly.
54  */
55 #define NAND_MAX_OOBSIZE	218
56 #define NAND_MAX_PAGESIZE	4096
57 
58 /*
59  * Constants for hardware specific CLE/ALE/NCE function
60  *
61  * These are bits which can be or'ed to set/clear multiple
62  * bits in one go.
63  */
64 /* Select the chip by setting nCE to low */
65 #define NAND_NCE		0x01
66 /* Select the command latch by setting CLE to high */
67 #define NAND_CLE		0x02
68 /* Select the address latch by setting ALE to high */
69 #define NAND_ALE		0x04
70 
71 #define NAND_CTRL_CLE		(NAND_NCE | NAND_CLE)
72 #define NAND_CTRL_ALE		(NAND_NCE | NAND_ALE)
73 #define NAND_CTRL_CHANGE	0x80
74 
75 /*
76  * Standard NAND flash commands
77  */
78 #define NAND_CMD_READ0		0
79 #define NAND_CMD_READ1		1
80 #define NAND_CMD_RNDOUT		5
81 #define NAND_CMD_PAGEPROG	0x10
82 #define NAND_CMD_READOOB	0x50
83 #define NAND_CMD_ERASE1		0x60
84 #define NAND_CMD_STATUS		0x70
85 #define NAND_CMD_STATUS_MULTI	0x71
86 #define NAND_CMD_SEQIN		0x80
87 #define NAND_CMD_RNDIN		0x85
88 #define NAND_CMD_READID		0x90
89 #define NAND_CMD_PARAM		0xec
90 #define NAND_CMD_ERASE2		0xd0
91 #define NAND_CMD_RESET		0xff
92 
93 /* Extended commands for large page devices */
94 #define NAND_CMD_READSTART	0x30
95 #define NAND_CMD_RNDOUTSTART	0xE0
96 #define NAND_CMD_CACHEDPROG	0x15
97 
98 /* Extended commands for AG-AND device */
99 /*
100  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
101  *       there is no way to distinguish that from NAND_CMD_READ0
102  *       until the remaining sequence of commands has been completed
103  *       so add a high order bit and mask it off in the command.
104  */
105 #define NAND_CMD_DEPLETE1	0x100
106 #define NAND_CMD_DEPLETE2	0x38
107 #define NAND_CMD_STATUS_MULTI	0x71
108 #define NAND_CMD_STATUS_ERROR	0x72
109 /* multi-bank error status (banks 0-3) */
110 #define NAND_CMD_STATUS_ERROR0	0x73
111 #define NAND_CMD_STATUS_ERROR1	0x74
112 #define NAND_CMD_STATUS_ERROR2	0x75
113 #define NAND_CMD_STATUS_ERROR3	0x76
114 #define NAND_CMD_STATUS_RESET	0x7f
115 #define NAND_CMD_STATUS_CLEAR	0xff
116 
117 #define NAND_CMD_NONE		-1
118 
119 /* Status bits */
120 #define NAND_STATUS_FAIL	0x01
121 #define NAND_STATUS_FAIL_N1	0x02
122 #define NAND_STATUS_TRUE_READY	0x20
123 #define NAND_STATUS_READY	0x40
124 #define NAND_STATUS_WP		0x80
125 
126 /*
127  * Constants for ECC_MODES
128  */
129 typedef enum {
130 	NAND_ECC_NONE,
131 	NAND_ECC_SOFT,
132 	NAND_ECC_HW,
133 	NAND_ECC_HW_SYNDROME,
134 	NAND_ECC_HW_OOB_FIRST,
135 } nand_ecc_modes_t;
136 
137 /*
138  * Constants for Hardware ECC
139  */
140 /* Reset Hardware ECC for read */
141 #define NAND_ECC_READ		0
142 /* Reset Hardware ECC for write */
143 #define NAND_ECC_WRITE		1
144 /* Enable Hardware ECC before syndrom is read back from flash */
145 #define NAND_ECC_READSYN	2
146 
147 /* Bit mask for flags passed to do_nand_read_ecc */
148 #define NAND_GET_DEVICE		0x80
149 
150 
151 /* Option constants for bizarre disfunctionality and real
152 *  features
153 */
154 /* Chip can not auto increment pages */
155 #define NAND_NO_AUTOINCR	0x00000001
156 /* Buswitdh is 16 bit */
157 #define NAND_BUSWIDTH_16	0x00000002
158 /* Device supports partial programming without padding */
159 #define NAND_NO_PADDING		0x00000004
160 /* Chip has cache program function */
161 #define NAND_CACHEPRG		0x00000008
162 /* Chip has copy back function */
163 #define NAND_COPYBACK		0x00000010
164 /* AND Chip which has 4 banks and a confusing page / block
165  * assignment. See Renesas datasheet for further information */
166 #define NAND_IS_AND		0x00000020
167 /* Chip has a array of 4 pages which can be read without
168  * additional ready /busy waits */
169 #define NAND_4PAGE_ARRAY	0x00000040
170 /* Chip requires that BBT is periodically rewritten to prevent
171  * bits from adjacent blocks from 'leaking' in altering data.
172  * This happens with the Renesas AG-AND chips, possibly others.  */
173 #define BBT_AUTO_REFRESH	0x00000080
174 /* Chip does not require ready check on read. True
175  * for all large page devices, as they do not support
176  * autoincrement.*/
177 #define NAND_NO_READRDY		0x00000100
178 /* Chip does not allow subpage writes */
179 #define NAND_NO_SUBPAGE_WRITE	0x00000200
180 
181 
182 /* Options valid for Samsung large page devices */
183 #define NAND_SAMSUNG_LP_OPTIONS \
184 	(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
185 
186 /* Macros to identify the above */
187 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
188 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
189 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
190 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
191 /* Large page NAND with SOFT_ECC should support subpage reads */
192 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
193 					&& (chip->page_shift > 9))
194 
195 /* Mask to zero out the chip options, which come from the id table */
196 #define NAND_CHIPOPTIONS_MSK	(0x0000ffff & ~NAND_NO_AUTOINCR)
197 
198 /* Non chip related options */
199 /* Use a flash based bad block table. This option is passed to the
200  * default bad block table function. */
201 #define NAND_USE_FLASH_BBT	0x00010000
202 /* This option skips the bbt scan during initialization. */
203 #define NAND_SKIP_BBTSCAN	0x00020000
204 /* This option is defined if the board driver allocates its own buffers
205    (e.g. because it needs them DMA-coherent */
206 #define NAND_OWN_BUFFERS	0x00040000
207 /* Options set by nand scan */
208 /* bbt has already been read */
209 #define NAND_BBT_SCANNED	0x40000000
210 /* Nand scan has allocated controller struct */
211 #define NAND_CONTROLLER_ALLOC	0x80000000
212 
213 /* Cell info constants */
214 #define NAND_CI_CHIPNR_MSK	0x03
215 #define NAND_CI_CELLTYPE_MSK	0x0C
216 
217 /* Keep gcc happy */
218 struct nand_chip;
219 
220 struct nand_onfi_params {
221 	/* rev info and features block */
222 	/* 'O' 'N' 'F' 'I'  */
223 	u8 sig[4];
224 	__le16 revision;
225 	__le16 features;
226 	__le16 opt_cmd;
227 	u8 reserved[22];
228 
229 	/* manufacturer information block */
230 	char manufacturer[12];
231 	char model[20];
232 	u8 jedec_id;
233 	__le16 date_code;
234 	u8 reserved2[13];
235 
236 	/* memory organization block */
237 	__le32 byte_per_page;
238 	__le16 spare_bytes_per_page;
239 	__le32 data_bytes_per_ppage;
240 	__le16 spare_bytes_per_ppage;
241 	__le32 pages_per_block;
242 	__le32 blocks_per_lun;
243 	u8 lun_count;
244 	u8 addr_cycles;
245 	u8 bits_per_cell;
246 	__le16 bb_per_lun;
247 	__le16 block_endurance;
248 	u8 guaranteed_good_blocks;
249 	__le16 guaranteed_block_endurance;
250 	u8 programs_per_page;
251 	u8 ppage_attr;
252 	u8 ecc_bits;
253 	u8 interleaved_bits;
254 	u8 interleaved_ops;
255 	u8 reserved3[13];
256 
257 	/* electrical parameter block */
258 	u8 io_pin_capacitance_max;
259 	__le16 async_timing_mode;
260 	__le16 program_cache_timing_mode;
261 	__le16 t_prog;
262 	__le16 t_bers;
263 	__le16 t_r;
264 	__le16 t_ccs;
265 	__le16 src_sync_timing_mode;
266 	__le16 src_ssync_features;
267 	__le16 clk_pin_capacitance_typ;
268 	__le16 io_pin_capacitance_typ;
269 	__le16 input_pin_capacitance_typ;
270 	u8 input_pin_capacitance_max;
271 	u8 driver_strenght_support;
272 	__le16 t_int_r;
273 	__le16 t_ald;
274 	u8 reserved4[7];
275 
276 	/* vendor */
277 	u8 reserved5[90];
278 
279 	__le16 crc;
280 } __attribute__((packed));
281 
282 #define ONFI_CRC_BASE	0x4F4E
283 
284 
285 /**
286  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
287  * @lock:               protection lock
288  * @active:		the mtd device which holds the controller currently
289  * @wq:			wait queue to sleep on if a NAND operation is in progress
290  *                      used instead of the per chip wait queue when a hw controller is available
291  */
292 struct nand_hw_control {
293 /* XXX U-BOOT XXX */
294 #if 0
295 	spinlock_t	 lock;
296 	wait_queue_head_t wq;
297 #endif
298 	struct nand_chip *active;
299 };
300 
301 /**
302  * struct nand_ecc_ctrl - Control structure for ecc
303  * @mode:	ecc mode
304  * @steps:	number of ecc steps per page
305  * @size:	data bytes per ecc step
306  * @bytes:	ecc bytes per step
307  * @total:	total number of ecc bytes per page
308  * @prepad:	padding information for syndrome based ecc generators
309  * @postpad:	padding information for syndrome based ecc generators
310  * @layout:	ECC layout control struct pointer
311  * @hwctl:	function to control hardware ecc generator. Must only
312  *		be provided if an hardware ECC is available
313  * @calculate:	function for ecc calculation or readback from ecc hardware
314  * @correct:	function for ecc correction, matching to ecc generator (sw/hw)
315  * @read_page_raw:	function to read a raw page without ECC
316  * @write_page_raw:	function to write a raw page without ECC
317  * @read_page:	function to read a page according to the ecc generator requirements
318  * @write_page:	function to write a page according to the ecc generator requirements
319  * @read_oob:	function to read chip OOB data
320  * @write_oob:	function to write chip OOB data
321  */
322 struct nand_ecc_ctrl {
323 	nand_ecc_modes_t	mode;
324 	int			steps;
325 	int			size;
326 	int			bytes;
327 	int			total;
328 	int			prepad;
329 	int			postpad;
330 	struct nand_ecclayout	*layout;
331 	void			(*hwctl)(struct mtd_info *mtd, int mode);
332 	int			(*calculate)(struct mtd_info *mtd,
333 					     const uint8_t *dat,
334 					     uint8_t *ecc_code);
335 	int			(*correct)(struct mtd_info *mtd, uint8_t *dat,
336 					   uint8_t *read_ecc,
337 					   uint8_t *calc_ecc);
338 	int			(*read_page_raw)(struct mtd_info *mtd,
339 						 struct nand_chip *chip,
340 						 uint8_t *buf, int page);
341 	void			(*write_page_raw)(struct mtd_info *mtd,
342 						  struct nand_chip *chip,
343 						  const uint8_t *buf);
344 	int			(*read_page)(struct mtd_info *mtd,
345 					     struct nand_chip *chip,
346 					     uint8_t *buf, int page);
347 	int			(*read_subpage)(struct mtd_info *mtd,
348 					     struct nand_chip *chip,
349 					     uint32_t offs, uint32_t len,
350 					     uint8_t *buf);
351 	void			(*write_page)(struct mtd_info *mtd,
352 					      struct nand_chip *chip,
353 					      const uint8_t *buf);
354 	int			(*read_oob)(struct mtd_info *mtd,
355 					    struct nand_chip *chip,
356 					    int page,
357 					    int sndcmd);
358 	int			(*write_oob)(struct mtd_info *mtd,
359 					     struct nand_chip *chip,
360 					     int page);
361 };
362 
363 /**
364  * struct nand_buffers - buffer structure for read/write
365  * @ecccalc:	buffer for calculated ecc
366  * @ecccode:	buffer for ecc read from flash
367  * @databuf:	buffer for data - dynamically sized
368  *
369  * Do not change the order of buffers. databuf and oobrbuf must be in
370  * consecutive order.
371  */
372 struct nand_buffers {
373 	uint8_t	ecccalc[NAND_MAX_OOBSIZE];
374 	uint8_t	ecccode[NAND_MAX_OOBSIZE];
375 	uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
376 };
377 
378 /**
379  * struct nand_chip - NAND Private Flash Chip Data
380  * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
381  * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
382  * @read_byte:		[REPLACEABLE] read one byte from the chip
383  * @read_word:		[REPLACEABLE] read one word from the chip
384  * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
385  * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
386  * @verify_buf:		[REPLACEABLE] verify buffer contents against the chip data
387  * @select_chip:	[REPLACEABLE] select chip nr
388  * @block_bad:		[REPLACEABLE] check, if the block is bad
389  * @block_markbad:	[REPLACEABLE] mark the block bad
390  * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific funtion for controlling
391  *			ALE/CLE/nCE. Also used to write command and address
392  * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
393  *			If set to NULL no access to ready/busy is available and the ready/busy information
394  *			is read from the chip status register
395  * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing commands to the chip
396  * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on ready
397  * @ecc:		[BOARDSPECIFIC] ecc control ctructure
398  * @buffers:		buffer structure for read/write
399  * @hwcontrol:		platform-specific hardware control structure
400  * @ops:		oob operation operands
401  * @erase_cmd:		[INTERN] erase command write function, selectable due to AND support
402  * @scan_bbt:		[REPLACEABLE] function to scan bad block table
403  * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
404  * @wq:			[INTERN] wait queue to sleep on if a NAND operation is in progress
405  * @state:		[INTERN] the current state of the NAND device
406  * @oob_poi:		poison value buffer
407  * @page_shift:		[INTERN] number of address bits in a page (column address bits)
408  * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
409  * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
410  * @chip_shift:		[INTERN] number of address bits in one chip
411  * @datbuf:		[INTERN] internal buffer for one page + oob
412  * @oobbuf:		[INTERN] oob buffer for one eraseblock
413  * @oobdirty:		[INTERN] indicates that oob_buf must be reinitialized
414  * @data_poi:		[INTERN] pointer to a data buffer
415  * @options:		[BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
416  *			special functionality. See the defines for further explanation
417  * @badblockpos:	[INTERN] position of the bad block marker in the oob area
418  * @cellinfo:		[INTERN] MLC/multichip data from chip ident
419  * @numchips:		[INTERN] number of physical chips
420  * @chipsize:		[INTERN] the size of one chip for multichip arrays
421  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
422  * @pagebuf:		[INTERN] holds the pagenumber which is currently in data_buf
423  * @subpagesize:	[INTERN] holds the subpagesize
424  * @ecclayout:		[REPLACEABLE] the default ecc placement scheme
425  * @bbt:		[INTERN] bad block table pointer
426  * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash lookup
427  * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
428  * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial bad block scan
429  * @controller:		[REPLACEABLE] a pointer to a hardware controller structure
430  *			which is shared among multiple independend devices
431  * @priv:		[OPTIONAL] pointer to private chip date
432  * @errstat:		[OPTIONAL] hardware specific function to perform additional error status checks
433  *			(determine if errors are correctable)
434  * @write_page:		[REPLACEABLE] High-level page write function
435  */
436 
437 struct nand_chip {
438 	void  __iomem	*IO_ADDR_R;
439 	void  __iomem	*IO_ADDR_W;
440 
441 	uint8_t		(*read_byte)(struct mtd_info *mtd);
442 	u16		(*read_word)(struct mtd_info *mtd);
443 	void		(*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
444 	void		(*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
445 	int		(*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
446 	void		(*select_chip)(struct mtd_info *mtd, int chip);
447 	int		(*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
448 	int		(*block_markbad)(struct mtd_info *mtd, loff_t ofs);
449 	void		(*cmd_ctrl)(struct mtd_info *mtd, int dat,
450 				    unsigned int ctrl);
451 	int		(*dev_ready)(struct mtd_info *mtd);
452 	void		(*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
453 	int		(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
454 	void		(*erase_cmd)(struct mtd_info *mtd, int page);
455 	int		(*scan_bbt)(struct mtd_info *mtd);
456 	int		(*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
457 	int		(*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
458 				      const uint8_t *buf, int page, int cached, int raw);
459 
460 	int		chip_delay;
461 	unsigned int	options;
462 
463 	int		page_shift;
464 	int		phys_erase_shift;
465 	int		bbt_erase_shift;
466 	int		chip_shift;
467 	int		numchips;
468 	uint64_t	chipsize;
469 	int		pagemask;
470 	int		pagebuf;
471 	int		subpagesize;
472 	uint8_t		cellinfo;
473 	int		badblockpos;
474 	int		onfi_version;
475 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
476 	struct nand_onfi_params onfi_params;
477 #endif
478 
479 	int 		state;
480 
481 	uint8_t		*oob_poi;
482 	struct nand_hw_control  *controller;
483 	struct nand_ecclayout	*ecclayout;
484 
485 	struct nand_ecc_ctrl ecc;
486 	struct nand_buffers *buffers;
487 
488 	struct nand_hw_control hwcontrol;
489 
490 	struct mtd_oob_ops ops;
491 
492 	uint8_t		*bbt;
493 	struct nand_bbt_descr	*bbt_td;
494 	struct nand_bbt_descr	*bbt_md;
495 
496 	struct nand_bbt_descr	*badblock_pattern;
497 
498 	void		*priv;
499 };
500 
501 /*
502  * NAND Flash Manufacturer ID Codes
503  */
504 #define NAND_MFR_TOSHIBA	0x98
505 #define NAND_MFR_SAMSUNG	0xec
506 #define NAND_MFR_FUJITSU	0x04
507 #define NAND_MFR_NATIONAL	0x8f
508 #define NAND_MFR_RENESAS	0x07
509 #define NAND_MFR_STMICRO	0x20
510 #define NAND_MFR_HYNIX		0xad
511 #define NAND_MFR_MICRON		0x2c
512 #define NAND_MFR_AMD		0x01
513 
514 /**
515  * struct nand_flash_dev - NAND Flash Device ID Structure
516  * @name:	Identify the device type
517  * @id:		device ID code
518  * @pagesize:	Pagesize in bytes. Either 256 or 512 or 0
519  *		If the pagesize is 0, then the real pagesize
520  *		and the eraseize are determined from the
521  *		extended id bytes in the chip
522  * @erasesize:	Size of an erase block in the flash device.
523  * @chipsize:	Total chipsize in Mega Bytes
524  * @options:	Bitfield to store chip relevant options
525  */
526 struct nand_flash_dev {
527 	char *name;
528 	int id;
529 	unsigned long pagesize;
530 	unsigned long chipsize;
531 	unsigned long erasesize;
532 	unsigned long options;
533 };
534 
535 /**
536  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
537  * @name:	Manufacturer name
538  * @id:		manufacturer ID code of device.
539 */
540 struct nand_manufacturers {
541 	int id;
542 	char * name;
543 };
544 
545 extern const struct nand_flash_dev nand_flash_ids[];
546 extern const struct nand_manufacturers nand_manuf_ids[];
547 
548 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
549 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
550 extern int nand_default_bbt(struct mtd_info *mtd);
551 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
552 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
553 			   int allowbbt);
554 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
555 			size_t * retlen, uint8_t * buf);
556 
557 /*
558 * Constants for oob configuration
559 */
560 #define NAND_SMALL_BADBLOCK_POS		5
561 #define NAND_LARGE_BADBLOCK_POS		0
562 
563 /**
564  * struct platform_nand_chip - chip level device structure
565  * @nr_chips:		max. number of chips to scan for
566  * @chip_offset:	chip number offset
567  * @nr_partitions:	number of partitions pointed to by partitions (or zero)
568  * @partitions:		mtd partition list
569  * @chip_delay:		R/B delay value in us
570  * @options:		Option flags, e.g. 16bit buswidth
571  * @ecclayout:		ecc layout info structure
572  * @part_probe_types:	NULL-terminated array of probe types
573  * @priv:		hardware controller specific settings
574  */
575 struct platform_nand_chip {
576 	int			nr_chips;
577 	int			chip_offset;
578 	int			nr_partitions;
579 	struct mtd_partition	*partitions;
580 	struct nand_ecclayout	*ecclayout;
581 	int			chip_delay;
582 	unsigned int		options;
583 	const char		**part_probe_types;
584 	void			*priv;
585 };
586 
587 /**
588  * struct platform_nand_ctrl - controller level device structure
589  * @hwcontrol:		platform specific hardware control structure
590  * @dev_ready:		platform specific function to read ready/busy pin
591  * @select_chip:	platform specific chip select function
592  * @cmd_ctrl:		platform specific function for controlling
593  *			ALE/CLE/nCE. Also used to write command and address
594  * @priv:		private data to transport driver specific settings
595  *
596  * All fields are optional and depend on the hardware driver requirements
597  */
598 struct platform_nand_ctrl {
599 	void		(*hwcontrol)(struct mtd_info *mtd, int cmd);
600 	int		(*dev_ready)(struct mtd_info *mtd);
601 	void		(*select_chip)(struct mtd_info *mtd, int chip);
602 	void		(*cmd_ctrl)(struct mtd_info *mtd, int dat,
603 				    unsigned int ctrl);
604 	void		*priv;
605 };
606 
607 /**
608  * struct platform_nand_data - container structure for platform-specific data
609  * @chip:		chip level chip structure
610  * @ctrl:		controller level device structure
611  */
612 struct platform_nand_data {
613 	struct platform_nand_chip	chip;
614 	struct platform_nand_ctrl	ctrl;
615 };
616 
617 /* Some helpers to access the data structures */
618 static inline
619 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
620 {
621 	struct nand_chip *chip = mtd->priv;
622 
623 	return chip->priv;
624 }
625 
626 #endif /* __LINUX_MTD_NAND_H */
627