1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 /* XXX U-BOOT XXX */ 22 #if 0 23 #include <linux/wait.h> 24 #include <linux/spinlock.h> 25 #include <linux/mtd/mtd.h> 26 #endif 27 28 #include "config.h" 29 30 #include "linux/mtd/compat.h" 31 #include "linux/mtd/mtd.h" 32 #include "linux/mtd/bbm.h" 33 34 35 struct mtd_info; 36 /* Scan and identify a NAND device */ 37 extern int nand_scan (struct mtd_info *mtd, int max_chips); 38 /* Separate phases of nand_scan(), allowing board driver to intervene 39 * and override command or ECC setup according to flash type */ 40 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips); 41 extern int nand_scan_tail(struct mtd_info *mtd); 42 43 /* Free resources held by the NAND device */ 44 extern void nand_release (struct mtd_info *mtd); 45 46 /* Internal helper for board drivers which need to override command function */ 47 extern void nand_wait_ready(struct mtd_info *mtd); 48 49 /* This constant declares the max. oobsize / page, which 50 * is supported now. If you add a chip with bigger oobsize/page 51 * adjust this accordingly. 52 */ 53 #define NAND_MAX_OOBSIZE 128 54 #define NAND_MAX_PAGESIZE 4096 55 56 /* 57 * Constants for hardware specific CLE/ALE/NCE function 58 * 59 * These are bits which can be or'ed to set/clear multiple 60 * bits in one go. 61 */ 62 /* Select the chip by setting nCE to low */ 63 #define NAND_NCE 0x01 64 /* Select the command latch by setting CLE to high */ 65 #define NAND_CLE 0x02 66 /* Select the address latch by setting ALE to high */ 67 #define NAND_ALE 0x04 68 69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 71 #define NAND_CTRL_CHANGE 0x80 72 73 /* 74 * Standard NAND flash commands 75 */ 76 #define NAND_CMD_READ0 0 77 #define NAND_CMD_READ1 1 78 #define NAND_CMD_RNDOUT 5 79 #define NAND_CMD_PAGEPROG 0x10 80 #define NAND_CMD_READOOB 0x50 81 #define NAND_CMD_ERASE1 0x60 82 #define NAND_CMD_STATUS 0x70 83 #define NAND_CMD_STATUS_MULTI 0x71 84 #define NAND_CMD_SEQIN 0x80 85 #define NAND_CMD_RNDIN 0x85 86 #define NAND_CMD_READID 0x90 87 #define NAND_CMD_ERASE2 0xd0 88 #define NAND_CMD_RESET 0xff 89 90 /* Extended commands for large page devices */ 91 #define NAND_CMD_READSTART 0x30 92 #define NAND_CMD_RNDOUTSTART 0xE0 93 #define NAND_CMD_CACHEDPROG 0x15 94 95 /* Extended commands for AG-AND device */ 96 /* 97 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 98 * there is no way to distinguish that from NAND_CMD_READ0 99 * until the remaining sequence of commands has been completed 100 * so add a high order bit and mask it off in the command. 101 */ 102 #define NAND_CMD_DEPLETE1 0x100 103 #define NAND_CMD_DEPLETE2 0x38 104 #define NAND_CMD_STATUS_MULTI 0x71 105 #define NAND_CMD_STATUS_ERROR 0x72 106 /* multi-bank error status (banks 0-3) */ 107 #define NAND_CMD_STATUS_ERROR0 0x73 108 #define NAND_CMD_STATUS_ERROR1 0x74 109 #define NAND_CMD_STATUS_ERROR2 0x75 110 #define NAND_CMD_STATUS_ERROR3 0x76 111 #define NAND_CMD_STATUS_RESET 0x7f 112 #define NAND_CMD_STATUS_CLEAR 0xff 113 114 #define NAND_CMD_NONE -1 115 116 /* Status bits */ 117 #define NAND_STATUS_FAIL 0x01 118 #define NAND_STATUS_FAIL_N1 0x02 119 #define NAND_STATUS_TRUE_READY 0x20 120 #define NAND_STATUS_READY 0x40 121 #define NAND_STATUS_WP 0x80 122 123 /* 124 * Constants for ECC_MODES 125 */ 126 typedef enum { 127 NAND_ECC_NONE, 128 NAND_ECC_SOFT, 129 NAND_ECC_HW, 130 NAND_ECC_HW_SYNDROME, 131 } nand_ecc_modes_t; 132 133 /* 134 * Constants for Hardware ECC 135 */ 136 /* Reset Hardware ECC for read */ 137 #define NAND_ECC_READ 0 138 /* Reset Hardware ECC for write */ 139 #define NAND_ECC_WRITE 1 140 /* Enable Hardware ECC before syndrom is read back from flash */ 141 #define NAND_ECC_READSYN 2 142 143 /* Bit mask for flags passed to do_nand_read_ecc */ 144 #define NAND_GET_DEVICE 0x80 145 146 147 /* Option constants for bizarre disfunctionality and real 148 * features 149 */ 150 /* Chip can not auto increment pages */ 151 #define NAND_NO_AUTOINCR 0x00000001 152 /* Buswitdh is 16 bit */ 153 #define NAND_BUSWIDTH_16 0x00000002 154 /* Device supports partial programming without padding */ 155 #define NAND_NO_PADDING 0x00000004 156 /* Chip has cache program function */ 157 #define NAND_CACHEPRG 0x00000008 158 /* Chip has copy back function */ 159 #define NAND_COPYBACK 0x00000010 160 /* AND Chip which has 4 banks and a confusing page / block 161 * assignment. See Renesas datasheet for further information */ 162 #define NAND_IS_AND 0x00000020 163 /* Chip has a array of 4 pages which can be read without 164 * additional ready /busy waits */ 165 #define NAND_4PAGE_ARRAY 0x00000040 166 /* Chip requires that BBT is periodically rewritten to prevent 167 * bits from adjacent blocks from 'leaking' in altering data. 168 * This happens with the Renesas AG-AND chips, possibly others. */ 169 #define BBT_AUTO_REFRESH 0x00000080 170 /* Chip does not require ready check on read. True 171 * for all large page devices, as they do not support 172 * autoincrement.*/ 173 #define NAND_NO_READRDY 0x00000100 174 /* Chip does not allow subpage writes */ 175 #define NAND_NO_SUBPAGE_WRITE 0x00000200 176 177 178 /* Options valid for Samsung large page devices */ 179 #define NAND_SAMSUNG_LP_OPTIONS \ 180 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 181 182 /* Macros to identify the above */ 183 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) 184 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 185 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 186 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 187 /* Large page NAND with SOFT_ECC should support subpage reads */ 188 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ 189 && (chip->page_shift > 9)) 190 191 /* Mask to zero out the chip options, which come from the id table */ 192 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) 193 194 /* Non chip related options */ 195 /* Use a flash based bad block table. This option is passed to the 196 * default bad block table function. */ 197 #define NAND_USE_FLASH_BBT 0x00010000 198 /* This option skips the bbt scan during initialization. */ 199 #define NAND_SKIP_BBTSCAN 0x00020000 200 /* This option is defined if the board driver allocates its own buffers 201 (e.g. because it needs them DMA-coherent */ 202 #define NAND_OWN_BUFFERS 0x00040000 203 /* Options set by nand scan */ 204 /* bbt has already been read */ 205 #define NAND_BBT_SCANNED 0x40000000 206 /* Nand scan has allocated controller struct */ 207 #define NAND_CONTROLLER_ALLOC 0x80000000 208 209 /* Cell info constants */ 210 #define NAND_CI_CHIPNR_MSK 0x03 211 #define NAND_CI_CELLTYPE_MSK 0x0C 212 213 /* Keep gcc happy */ 214 struct nand_chip; 215 216 /** 217 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 218 * @lock: protection lock 219 * @active: the mtd device which holds the controller currently 220 * @wq: wait queue to sleep on if a NAND operation is in progress 221 * used instead of the per chip wait queue when a hw controller is available 222 */ 223 struct nand_hw_control { 224 /* XXX U-BOOT XXX */ 225 #if 0 226 spinlock_t lock; 227 wait_queue_head_t wq; 228 #endif 229 struct nand_chip *active; 230 }; 231 232 /** 233 * struct nand_ecc_ctrl - Control structure for ecc 234 * @mode: ecc mode 235 * @steps: number of ecc steps per page 236 * @size: data bytes per ecc step 237 * @bytes: ecc bytes per step 238 * @total: total number of ecc bytes per page 239 * @prepad: padding information for syndrome based ecc generators 240 * @postpad: padding information for syndrome based ecc generators 241 * @layout: ECC layout control struct pointer 242 * @hwctl: function to control hardware ecc generator. Must only 243 * be provided if an hardware ECC is available 244 * @calculate: function for ecc calculation or readback from ecc hardware 245 * @correct: function for ecc correction, matching to ecc generator (sw/hw) 246 * @read_page_raw: function to read a raw page without ECC 247 * @write_page_raw: function to write a raw page without ECC 248 * @read_page: function to read a page according to the ecc generator requirements 249 * @write_page: function to write a page according to the ecc generator requirements 250 * @read_oob: function to read chip OOB data 251 * @write_oob: function to write chip OOB data 252 */ 253 struct nand_ecc_ctrl { 254 nand_ecc_modes_t mode; 255 int steps; 256 int size; 257 int bytes; 258 int total; 259 int prepad; 260 int postpad; 261 struct nand_ecclayout *layout; 262 void (*hwctl)(struct mtd_info *mtd, int mode); 263 int (*calculate)(struct mtd_info *mtd, 264 const uint8_t *dat, 265 uint8_t *ecc_code); 266 int (*correct)(struct mtd_info *mtd, uint8_t *dat, 267 uint8_t *read_ecc, 268 uint8_t *calc_ecc); 269 int (*read_page_raw)(struct mtd_info *mtd, 270 struct nand_chip *chip, 271 uint8_t *buf); 272 void (*write_page_raw)(struct mtd_info *mtd, 273 struct nand_chip *chip, 274 const uint8_t *buf); 275 int (*read_page)(struct mtd_info *mtd, 276 struct nand_chip *chip, 277 uint8_t *buf); 278 int (*read_subpage)(struct mtd_info *mtd, 279 struct nand_chip *chip, 280 uint32_t offs, uint32_t len, 281 uint8_t *buf); 282 void (*write_page)(struct mtd_info *mtd, 283 struct nand_chip *chip, 284 const uint8_t *buf); 285 int (*read_oob)(struct mtd_info *mtd, 286 struct nand_chip *chip, 287 int page, 288 int sndcmd); 289 int (*write_oob)(struct mtd_info *mtd, 290 struct nand_chip *chip, 291 int page); 292 }; 293 294 /** 295 * struct nand_buffers - buffer structure for read/write 296 * @ecccalc: buffer for calculated ecc 297 * @ecccode: buffer for ecc read from flash 298 * @databuf: buffer for data - dynamically sized 299 * 300 * Do not change the order of buffers. databuf and oobrbuf must be in 301 * consecutive order. 302 */ 303 struct nand_buffers { 304 uint8_t ecccalc[NAND_MAX_OOBSIZE]; 305 uint8_t ecccode[NAND_MAX_OOBSIZE]; 306 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; 307 }; 308 309 /** 310 * struct nand_chip - NAND Private Flash Chip Data 311 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device 312 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device 313 * @read_byte: [REPLACEABLE] read one byte from the chip 314 * @read_word: [REPLACEABLE] read one word from the chip 315 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 316 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 317 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data 318 * @select_chip: [REPLACEABLE] select chip nr 319 * @block_bad: [REPLACEABLE] check, if the block is bad 320 * @block_markbad: [REPLACEABLE] mark the block bad 321 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling 322 * ALE/CLE/nCE. Also used to write command and address 323 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line 324 * If set to NULL no access to ready/busy is available and the ready/busy information 325 * is read from the chip status register 326 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip 327 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready 328 * @ecc: [BOARDSPECIFIC] ecc control ctructure 329 * @buffers: buffer structure for read/write 330 * @hwcontrol: platform-specific hardware control structure 331 * @ops: oob operation operands 332 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support 333 * @scan_bbt: [REPLACEABLE] function to scan bad block table 334 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) 335 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress 336 * @state: [INTERN] the current state of the NAND device 337 * @oob_poi: poison value buffer 338 * @page_shift: [INTERN] number of address bits in a page (column address bits) 339 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 340 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 341 * @chip_shift: [INTERN] number of address bits in one chip 342 * @datbuf: [INTERN] internal buffer for one page + oob 343 * @oobbuf: [INTERN] oob buffer for one eraseblock 344 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized 345 * @data_poi: [INTERN] pointer to a data buffer 346 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about 347 * special functionality. See the defines for further explanation 348 * @badblockpos: [INTERN] position of the bad block marker in the oob area 349 * @cellinfo: [INTERN] MLC/multichip data from chip ident 350 * @numchips: [INTERN] number of physical chips 351 * @chipsize: [INTERN] the size of one chip for multichip arrays 352 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 353 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf 354 * @subpagesize: [INTERN] holds the subpagesize 355 * @ecclayout: [REPLACEABLE] the default ecc placement scheme 356 * @bbt: [INTERN] bad block table pointer 357 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup 358 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 359 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan 360 * @controller: [REPLACEABLE] a pointer to a hardware controller structure 361 * which is shared among multiple independend devices 362 * @priv: [OPTIONAL] pointer to private chip date 363 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks 364 * (determine if errors are correctable) 365 * @write_page: [REPLACEABLE] High-level page write function 366 */ 367 368 struct nand_chip { 369 void __iomem *IO_ADDR_R; 370 void __iomem *IO_ADDR_W; 371 372 uint8_t (*read_byte)(struct mtd_info *mtd); 373 u16 (*read_word)(struct mtd_info *mtd); 374 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 375 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 376 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 377 void (*select_chip)(struct mtd_info *mtd, int chip); 378 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 379 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 380 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, 381 unsigned int ctrl); 382 int (*dev_ready)(struct mtd_info *mtd); 383 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); 384 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 385 void (*erase_cmd)(struct mtd_info *mtd, int page); 386 int (*scan_bbt)(struct mtd_info *mtd); 387 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); 388 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 389 const uint8_t *buf, int page, int cached, int raw); 390 391 int chip_delay; 392 unsigned int options; 393 394 int page_shift; 395 int phys_erase_shift; 396 int bbt_erase_shift; 397 int chip_shift; 398 int numchips; 399 unsigned long chipsize; 400 int pagemask; 401 int pagebuf; 402 int subpagesize; 403 uint8_t cellinfo; 404 int badblockpos; 405 406 int state; 407 408 uint8_t *oob_poi; 409 struct nand_hw_control *controller; 410 struct nand_ecclayout *ecclayout; 411 412 struct nand_ecc_ctrl ecc; 413 struct nand_buffers *buffers; 414 415 struct nand_hw_control hwcontrol; 416 417 struct mtd_oob_ops ops; 418 419 uint8_t *bbt; 420 struct nand_bbt_descr *bbt_td; 421 struct nand_bbt_descr *bbt_md; 422 423 struct nand_bbt_descr *badblock_pattern; 424 425 void *priv; 426 }; 427 428 /* 429 * NAND Flash Manufacturer ID Codes 430 */ 431 #define NAND_MFR_TOSHIBA 0x98 432 #define NAND_MFR_SAMSUNG 0xec 433 #define NAND_MFR_FUJITSU 0x04 434 #define NAND_MFR_NATIONAL 0x8f 435 #define NAND_MFR_RENESAS 0x07 436 #define NAND_MFR_STMICRO 0x20 437 #define NAND_MFR_HYNIX 0xad 438 #define NAND_MFR_MICRON 0x2c 439 #define NAND_MFR_AMD 0x01 440 441 /** 442 * struct nand_flash_dev - NAND Flash Device ID Structure 443 * @name: Identify the device type 444 * @id: device ID code 445 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 446 * If the pagesize is 0, then the real pagesize 447 * and the eraseize are determined from the 448 * extended id bytes in the chip 449 * @erasesize: Size of an erase block in the flash device. 450 * @chipsize: Total chipsize in Mega Bytes 451 * @options: Bitfield to store chip relevant options 452 */ 453 struct nand_flash_dev { 454 char *name; 455 int id; 456 unsigned long pagesize; 457 unsigned long chipsize; 458 unsigned long erasesize; 459 unsigned long options; 460 }; 461 462 /** 463 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 464 * @name: Manufacturer name 465 * @id: manufacturer ID code of device. 466 */ 467 struct nand_manufacturers { 468 int id; 469 char * name; 470 }; 471 472 extern struct nand_flash_dev nand_flash_ids[]; 473 extern struct nand_manufacturers nand_manuf_ids[]; 474 475 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 476 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 477 extern int nand_default_bbt(struct mtd_info *mtd); 478 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 479 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 480 int allowbbt); 481 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 482 size_t * retlen, uint8_t * buf); 483 484 /* 485 * Constants for oob configuration 486 */ 487 #define NAND_SMALL_BADBLOCK_POS 5 488 #define NAND_LARGE_BADBLOCK_POS 0 489 490 /** 491 * struct platform_nand_chip - chip level device structure 492 * @nr_chips: max. number of chips to scan for 493 * @chip_offset: chip number offset 494 * @nr_partitions: number of partitions pointed to by partitions (or zero) 495 * @partitions: mtd partition list 496 * @chip_delay: R/B delay value in us 497 * @options: Option flags, e.g. 16bit buswidth 498 * @ecclayout: ecc layout info structure 499 * @part_probe_types: NULL-terminated array of probe types 500 * @priv: hardware controller specific settings 501 */ 502 struct platform_nand_chip { 503 int nr_chips; 504 int chip_offset; 505 int nr_partitions; 506 struct mtd_partition *partitions; 507 struct nand_ecclayout *ecclayout; 508 int chip_delay; 509 unsigned int options; 510 const char **part_probe_types; 511 void *priv; 512 }; 513 514 /** 515 * struct platform_nand_ctrl - controller level device structure 516 * @hwcontrol: platform specific hardware control structure 517 * @dev_ready: platform specific function to read ready/busy pin 518 * @select_chip: platform specific chip select function 519 * @cmd_ctrl: platform specific function for controlling 520 * ALE/CLE/nCE. Also used to write command and address 521 * @priv: private data to transport driver specific settings 522 * 523 * All fields are optional and depend on the hardware driver requirements 524 */ 525 struct platform_nand_ctrl { 526 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 527 int (*dev_ready)(struct mtd_info *mtd); 528 void (*select_chip)(struct mtd_info *mtd, int chip); 529 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, 530 unsigned int ctrl); 531 void *priv; 532 }; 533 534 /** 535 * struct platform_nand_data - container structure for platform-specific data 536 * @chip: chip level chip structure 537 * @ctrl: controller level device structure 538 */ 539 struct platform_nand_data { 540 struct platform_nand_chip chip; 541 struct platform_nand_ctrl ctrl; 542 }; 543 544 /* Some helpers to access the data structures */ 545 static inline 546 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 547 { 548 struct nand_chip *chip = mtd->priv; 549 550 return chip->priv; 551 } 552 553 #endif /* __LINUX_MTD_NAND_H */ 554