1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_NAND_H 17 #define __LINUX_MTD_NAND_H 18 19 #include <config.h> 20 21 #include <linux/compat.h> 22 #include <linux/mtd/mtd.h> 23 #include <linux/mtd/flashchip.h> 24 #include <linux/mtd/bbm.h> 25 26 struct mtd_info; 27 struct nand_flash_dev; 28 struct device_node; 29 30 /* Scan and identify a NAND device */ 31 extern int nand_scan(struct mtd_info *mtd, int max_chips); 32 /* 33 * Separate phases of nand_scan(), allowing board driver to intervene 34 * and override command or ECC setup according to flash type. 35 */ 36 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 37 struct nand_flash_dev *table); 38 extern int nand_scan_tail(struct mtd_info *mtd); 39 40 /* Free resources held by the NAND device */ 41 extern void nand_release(struct mtd_info *mtd); 42 43 /* Internal helper for board drivers which need to override command function */ 44 extern void nand_wait_ready(struct mtd_info *mtd); 45 46 /* 47 * This constant declares the max. oobsize / page, which 48 * is supported now. If you add a chip with bigger oobsize/page 49 * adjust this accordingly. 50 */ 51 #define NAND_MAX_OOBSIZE 1664 52 #define NAND_MAX_PAGESIZE 16384 53 54 /* 55 * Constants for hardware specific CLE/ALE/NCE function 56 * 57 * These are bits which can be or'ed to set/clear multiple 58 * bits in one go. 59 */ 60 /* Select the chip by setting nCE to low */ 61 #define NAND_NCE 0x01 62 /* Select the command latch by setting CLE to high */ 63 #define NAND_CLE 0x02 64 /* Select the address latch by setting ALE to high */ 65 #define NAND_ALE 0x04 66 67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 69 #define NAND_CTRL_CHANGE 0x80 70 71 /* 72 * Standard NAND flash commands 73 */ 74 #define NAND_CMD_READ0 0 75 #define NAND_CMD_READ1 1 76 #define NAND_CMD_RNDOUT 5 77 #define NAND_CMD_PAGEPROG 0x10 78 #define NAND_CMD_READOOB 0x50 79 #define NAND_CMD_ERASE1 0x60 80 #define NAND_CMD_STATUS 0x70 81 #define NAND_CMD_SEQIN 0x80 82 #define NAND_CMD_RNDIN 0x85 83 #define NAND_CMD_READID 0x90 84 #define NAND_CMD_ERASE2 0xd0 85 #define NAND_CMD_PARAM 0xec 86 #define NAND_CMD_GET_FEATURES 0xee 87 #define NAND_CMD_SET_FEATURES 0xef 88 #define NAND_CMD_RESET 0xff 89 90 #define NAND_CMD_LOCK 0x2a 91 #define NAND_CMD_UNLOCK1 0x23 92 #define NAND_CMD_UNLOCK2 0x24 93 94 /* Extended commands for large page devices */ 95 #define NAND_CMD_READSTART 0x30 96 #define NAND_CMD_RNDOUTSTART 0xE0 97 #define NAND_CMD_CACHEDPROG 0x15 98 99 /* Extended commands for AG-AND device */ 100 /* 101 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 102 * there is no way to distinguish that from NAND_CMD_READ0 103 * until the remaining sequence of commands has been completed 104 * so add a high order bit and mask it off in the command. 105 */ 106 #define NAND_CMD_DEPLETE1 0x100 107 #define NAND_CMD_DEPLETE2 0x38 108 #define NAND_CMD_STATUS_MULTI 0x71 109 #define NAND_CMD_STATUS_ERROR 0x72 110 /* multi-bank error status (banks 0-3) */ 111 #define NAND_CMD_STATUS_ERROR0 0x73 112 #define NAND_CMD_STATUS_ERROR1 0x74 113 #define NAND_CMD_STATUS_ERROR2 0x75 114 #define NAND_CMD_STATUS_ERROR3 0x76 115 #define NAND_CMD_STATUS_RESET 0x7f 116 #define NAND_CMD_STATUS_CLEAR 0xff 117 118 #define NAND_CMD_NONE -1 119 120 /* Status bits */ 121 #define NAND_STATUS_FAIL 0x01 122 #define NAND_STATUS_FAIL_N1 0x02 123 #define NAND_STATUS_TRUE_READY 0x20 124 #define NAND_STATUS_READY 0x40 125 #define NAND_STATUS_WP 0x80 126 127 /* 128 * Constants for ECC_MODES 129 */ 130 typedef enum { 131 NAND_ECC_NONE, 132 NAND_ECC_SOFT, 133 NAND_ECC_HW, 134 NAND_ECC_HW_SYNDROME, 135 NAND_ECC_HW_OOB_FIRST, 136 NAND_ECC_SOFT_BCH, 137 } nand_ecc_modes_t; 138 139 /* 140 * Constants for Hardware ECC 141 */ 142 /* Reset Hardware ECC for read */ 143 #define NAND_ECC_READ 0 144 /* Reset Hardware ECC for write */ 145 #define NAND_ECC_WRITE 1 146 /* Enable Hardware ECC before syndrome is read back from flash */ 147 #define NAND_ECC_READSYN 2 148 149 /* 150 * Enable generic NAND 'page erased' check. This check is only done when 151 * ecc.correct() returns -EBADMSG. 152 * Set this flag if your implementation does not fix bitflips in erased 153 * pages and you want to rely on the default implementation. 154 */ 155 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 156 157 /* Bit mask for flags passed to do_nand_read_ecc */ 158 #define NAND_GET_DEVICE 0x80 159 160 161 /* 162 * Option constants for bizarre disfunctionality and real 163 * features. 164 */ 165 /* Buswidth is 16 bit */ 166 #define NAND_BUSWIDTH_16 0x00000002 167 /* Device supports partial programming without padding */ 168 #define NAND_NO_PADDING 0x00000004 169 /* Chip has cache program function */ 170 #define NAND_CACHEPRG 0x00000008 171 /* Chip has copy back function */ 172 #define NAND_COPYBACK 0x00000010 173 /* 174 * Chip requires ready check on read (for auto-incremented sequential read). 175 * True only for small page devices; large page devices do not support 176 * autoincrement. 177 */ 178 #define NAND_NEED_READRDY 0x00000100 179 180 /* Chip does not allow subpage writes */ 181 #define NAND_NO_SUBPAGE_WRITE 0x00000200 182 183 /* Device is one of 'new' xD cards that expose fake nand command set */ 184 #define NAND_BROKEN_XD 0x00000400 185 186 /* Device behaves just like nand, but is readonly */ 187 #define NAND_ROM 0x00000800 188 189 /* Device supports subpage reads */ 190 #define NAND_SUBPAGE_READ 0x00001000 191 192 /* 193 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 194 * patterns. 195 */ 196 #define NAND_NEED_SCRAMBLING 0x00002000 197 198 /* Options valid for Samsung large page devices */ 199 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 200 201 /* Macros to identify the above */ 202 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 203 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 204 205 /* Non chip related options */ 206 /* This option skips the bbt scan during initialization. */ 207 #define NAND_SKIP_BBTSCAN 0x00010000 208 /* 209 * This option is defined if the board driver allocates its own buffers 210 * (e.g. because it needs them DMA-coherent). 211 */ 212 #define NAND_OWN_BUFFERS 0x00020000 213 /* Chip may not exist, so silence any errors in scan */ 214 #define NAND_SCAN_SILENT_NODEV 0x00040000 215 /* 216 * Autodetect nand buswidth with readid/onfi. 217 * This suppose the driver will configure the hardware in 8 bits mode 218 * when calling nand_scan_ident, and update its configuration 219 * before calling nand_scan_tail. 220 */ 221 #define NAND_BUSWIDTH_AUTO 0x00080000 222 /* 223 * This option could be defined by controller drivers to protect against 224 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 225 */ 226 #define NAND_USE_BOUNCE_BUFFER 0x00100000 227 228 /* Options set by nand scan */ 229 /* bbt has already been read */ 230 #define NAND_BBT_SCANNED 0x40000000 231 /* Nand scan has allocated controller struct */ 232 #define NAND_CONTROLLER_ALLOC 0x80000000 233 234 /* Cell info constants */ 235 #define NAND_CI_CHIPNR_MSK 0x03 236 #define NAND_CI_CELLTYPE_MSK 0x0C 237 #define NAND_CI_CELLTYPE_SHIFT 2 238 239 /* Keep gcc happy */ 240 struct nand_chip; 241 242 /* ONFI features */ 243 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 244 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 245 246 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 247 #define ONFI_TIMING_MODE_0 (1 << 0) 248 #define ONFI_TIMING_MODE_1 (1 << 1) 249 #define ONFI_TIMING_MODE_2 (1 << 2) 250 #define ONFI_TIMING_MODE_3 (1 << 3) 251 #define ONFI_TIMING_MODE_4 (1 << 4) 252 #define ONFI_TIMING_MODE_5 (1 << 5) 253 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 254 255 /* ONFI feature address */ 256 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 257 258 /* Vendor-specific feature address (Micron) */ 259 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 260 261 /* ONFI subfeature parameters length */ 262 #define ONFI_SUBFEATURE_PARAM_LEN 4 263 264 /* ONFI optional commands SET/GET FEATURES supported? */ 265 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 266 267 struct nand_onfi_params { 268 /* rev info and features block */ 269 /* 'O' 'N' 'F' 'I' */ 270 u8 sig[4]; 271 __le16 revision; 272 __le16 features; 273 __le16 opt_cmd; 274 u8 reserved0[2]; 275 __le16 ext_param_page_length; /* since ONFI 2.1 */ 276 u8 num_of_param_pages; /* since ONFI 2.1 */ 277 u8 reserved1[17]; 278 279 /* manufacturer information block */ 280 char manufacturer[12]; 281 char model[20]; 282 u8 jedec_id; 283 __le16 date_code; 284 u8 reserved2[13]; 285 286 /* memory organization block */ 287 __le32 byte_per_page; 288 __le16 spare_bytes_per_page; 289 __le32 data_bytes_per_ppage; 290 __le16 spare_bytes_per_ppage; 291 __le32 pages_per_block; 292 __le32 blocks_per_lun; 293 u8 lun_count; 294 u8 addr_cycles; 295 u8 bits_per_cell; 296 __le16 bb_per_lun; 297 __le16 block_endurance; 298 u8 guaranteed_good_blocks; 299 __le16 guaranteed_block_endurance; 300 u8 programs_per_page; 301 u8 ppage_attr; 302 u8 ecc_bits; 303 u8 interleaved_bits; 304 u8 interleaved_ops; 305 u8 reserved3[13]; 306 307 /* electrical parameter block */ 308 u8 io_pin_capacitance_max; 309 __le16 async_timing_mode; 310 __le16 program_cache_timing_mode; 311 __le16 t_prog; 312 __le16 t_bers; 313 __le16 t_r; 314 __le16 t_ccs; 315 __le16 src_sync_timing_mode; 316 u8 src_ssync_features; 317 __le16 clk_pin_capacitance_typ; 318 __le16 io_pin_capacitance_typ; 319 __le16 input_pin_capacitance_typ; 320 u8 input_pin_capacitance_max; 321 u8 driver_strength_support; 322 __le16 t_int_r; 323 __le16 t_adl; 324 u8 reserved4[8]; 325 326 /* vendor */ 327 __le16 vendor_revision; 328 u8 vendor[88]; 329 330 __le16 crc; 331 } __packed; 332 333 #define ONFI_CRC_BASE 0x4F4E 334 335 /* Extended ECC information Block Definition (since ONFI 2.1) */ 336 struct onfi_ext_ecc_info { 337 u8 ecc_bits; 338 u8 codeword_size; 339 __le16 bb_per_lun; 340 __le16 block_endurance; 341 u8 reserved[2]; 342 } __packed; 343 344 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 345 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 346 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 347 struct onfi_ext_section { 348 u8 type; 349 u8 length; 350 } __packed; 351 352 #define ONFI_EXT_SECTION_MAX 8 353 354 /* Extended Parameter Page Definition (since ONFI 2.1) */ 355 struct onfi_ext_param_page { 356 __le16 crc; 357 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 358 u8 reserved0[10]; 359 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 360 361 /* 362 * The actual size of the Extended Parameter Page is in 363 * @ext_param_page_length of nand_onfi_params{}. 364 * The following are the variable length sections. 365 * So we do not add any fields below. Please see the ONFI spec. 366 */ 367 } __packed; 368 369 struct nand_onfi_vendor_micron { 370 u8 two_plane_read; 371 u8 read_cache; 372 u8 read_unique_id; 373 u8 dq_imped; 374 u8 dq_imped_num_settings; 375 u8 dq_imped_feat_addr; 376 u8 rb_pulldown_strength; 377 u8 rb_pulldown_strength_feat_addr; 378 u8 rb_pulldown_strength_num_settings; 379 u8 otp_mode; 380 u8 otp_page_start; 381 u8 otp_data_prot_addr; 382 u8 otp_num_pages; 383 u8 otp_feat_addr; 384 u8 read_retry_options; 385 u8 reserved[72]; 386 u8 param_revision; 387 } __packed; 388 389 struct jedec_ecc_info { 390 u8 ecc_bits; 391 u8 codeword_size; 392 __le16 bb_per_lun; 393 __le16 block_endurance; 394 u8 reserved[2]; 395 } __packed; 396 397 /* JEDEC features */ 398 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 399 400 struct nand_jedec_params { 401 /* rev info and features block */ 402 /* 'J' 'E' 'S' 'D' */ 403 u8 sig[4]; 404 __le16 revision; 405 __le16 features; 406 u8 opt_cmd[3]; 407 __le16 sec_cmd; 408 u8 num_of_param_pages; 409 u8 reserved0[18]; 410 411 /* manufacturer information block */ 412 char manufacturer[12]; 413 char model[20]; 414 u8 jedec_id[6]; 415 u8 reserved1[10]; 416 417 /* memory organization block */ 418 __le32 byte_per_page; 419 __le16 spare_bytes_per_page; 420 u8 reserved2[6]; 421 __le32 pages_per_block; 422 __le32 blocks_per_lun; 423 u8 lun_count; 424 u8 addr_cycles; 425 u8 bits_per_cell; 426 u8 programs_per_page; 427 u8 multi_plane_addr; 428 u8 multi_plane_op_attr; 429 u8 reserved3[38]; 430 431 /* electrical parameter block */ 432 __le16 async_sdr_speed_grade; 433 __le16 toggle_ddr_speed_grade; 434 __le16 sync_ddr_speed_grade; 435 u8 async_sdr_features; 436 u8 toggle_ddr_features; 437 u8 sync_ddr_features; 438 __le16 t_prog; 439 __le16 t_bers; 440 __le16 t_r; 441 __le16 t_r_multi_plane; 442 __le16 t_ccs; 443 __le16 io_pin_capacitance_typ; 444 __le16 input_pin_capacitance_typ; 445 __le16 clk_pin_capacitance_typ; 446 u8 driver_strength_support; 447 __le16 t_adl; 448 u8 reserved4[36]; 449 450 /* ECC and endurance block */ 451 u8 guaranteed_good_blocks; 452 __le16 guaranteed_block_endurance; 453 struct jedec_ecc_info ecc_info[4]; 454 u8 reserved5[29]; 455 456 /* reserved */ 457 u8 reserved6[148]; 458 459 /* vendor */ 460 __le16 vendor_rev_num; 461 u8 reserved7[88]; 462 463 /* CRC for Parameter Page */ 464 __le16 crc; 465 } __packed; 466 467 /** 468 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 469 * @lock: protection lock 470 * @active: the mtd device which holds the controller currently 471 * @wq: wait queue to sleep on if a NAND operation is in 472 * progress used instead of the per chip wait queue 473 * when a hw controller is available. 474 */ 475 struct nand_hw_control { 476 spinlock_t lock; 477 struct nand_chip *active; 478 }; 479 480 /** 481 * struct nand_ecc_ctrl - Control structure for ECC 482 * @mode: ECC mode 483 * @steps: number of ECC steps per page 484 * @size: data bytes per ECC step 485 * @bytes: ECC bytes per step 486 * @strength: max number of correctible bits per ECC step 487 * @total: total number of ECC bytes per page 488 * @prepad: padding information for syndrome based ECC generators 489 * @postpad: padding information for syndrome based ECC generators 490 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 491 * @layout: ECC layout control struct pointer 492 * @priv: pointer to private ECC control data 493 * @hwctl: function to control hardware ECC generator. Must only 494 * be provided if an hardware ECC is available 495 * @calculate: function for ECC calculation or readback from ECC hardware 496 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 497 * Should return a positive number representing the number of 498 * corrected bitflips, -EBADMSG if the number of bitflips exceed 499 * ECC strength, or any other error code if the error is not 500 * directly related to correction. 501 * If -EBADMSG is returned the input buffers should be left 502 * untouched. 503 * @read_page_raw: function to read a raw page without ECC. This function 504 * should hide the specific layout used by the ECC 505 * controller and always return contiguous in-band and 506 * out-of-band data even if they're not stored 507 * contiguously on the NAND chip (e.g. 508 * NAND_ECC_HW_SYNDROME interleaves in-band and 509 * out-of-band data). 510 * @write_page_raw: function to write a raw page without ECC. This function 511 * should hide the specific layout used by the ECC 512 * controller and consider the passed data as contiguous 513 * in-band and out-of-band data. ECC controller is 514 * responsible for doing the appropriate transformations 515 * to adapt to its specific layout (e.g. 516 * NAND_ECC_HW_SYNDROME interleaves in-band and 517 * out-of-band data). 518 * @read_page: function to read a page according to the ECC generator 519 * requirements; returns maximum number of bitflips corrected in 520 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 521 * @read_subpage: function to read parts of the page covered by ECC; 522 * returns same as read_page() 523 * @write_subpage: function to write parts of the page covered by ECC. 524 * @write_page: function to write a page according to the ECC generator 525 * requirements. 526 * @write_oob_raw: function to write chip OOB data without ECC 527 * @read_oob_raw: function to read chip OOB data without ECC 528 * @read_oob: function to read chip OOB data 529 * @write_oob: function to write chip OOB data 530 */ 531 struct nand_ecc_ctrl { 532 nand_ecc_modes_t mode; 533 int steps; 534 int size; 535 int bytes; 536 int total; 537 int strength; 538 int prepad; 539 int postpad; 540 unsigned int options; 541 struct nand_ecclayout *layout; 542 void *priv; 543 void (*hwctl)(struct mtd_info *mtd, int mode); 544 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 545 uint8_t *ecc_code); 546 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 547 uint8_t *calc_ecc); 548 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 549 uint8_t *buf, int oob_required, int page); 550 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 551 const uint8_t *buf, int oob_required, int page); 552 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 553 uint8_t *buf, int oob_required, int page); 554 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 555 uint32_t offs, uint32_t len, uint8_t *buf, int page); 556 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 557 uint32_t offset, uint32_t data_len, 558 const uint8_t *data_buf, int oob_required, int page); 559 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 560 const uint8_t *buf, int oob_required, int page); 561 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 562 int page); 563 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 564 int page); 565 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 566 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 567 int page); 568 }; 569 570 /** 571 * struct nand_buffers - buffer structure for read/write 572 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 573 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 574 * @databuf: buffer pointer for data, size is (page size + oobsize). 575 * 576 * Do not change the order of buffers. databuf and oobrbuf must be in 577 * consecutive order. 578 */ 579 struct nand_buffers { 580 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 581 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 582 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 583 ARCH_DMA_MINALIGN)]; 584 }; 585 586 /** 587 * struct nand_chip - NAND Private Flash Chip Data 588 * @mtd: MTD device registered to the MTD framework 589 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 590 * flash device 591 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 592 * flash device. 593 * @flash_node: [BOARDSPECIFIC] device node describing this instance 594 * @read_byte: [REPLACEABLE] read one byte from the chip 595 * @read_word: [REPLACEABLE] read one word from the chip 596 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 597 * low 8 I/O lines 598 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 599 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 600 * @select_chip: [REPLACEABLE] select chip nr 601 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 602 * @block_markbad: [REPLACEABLE] mark a block bad 603 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 604 * ALE/CLE/nCE. Also used to write command and address 605 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 606 * device ready/busy line. If set to NULL no access to 607 * ready/busy is available and the ready/busy information 608 * is read from the chip status register. 609 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 610 * commands to the chip. 611 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 612 * ready. 613 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 614 * setting the read-retry mode. Mostly needed for MLC NAND. 615 * @ecc: [BOARDSPECIFIC] ECC control structure 616 * @buffers: buffer structure for read/write 617 * @hwcontrol: platform-specific hardware control structure 618 * @erase: [REPLACEABLE] erase function 619 * @scan_bbt: [REPLACEABLE] function to scan bad block table 620 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 621 * data from array to read regs (tR). 622 * @state: [INTERN] the current state of the NAND device 623 * @oob_poi: "poison value buffer," used for laying out OOB data 624 * before writing 625 * @page_shift: [INTERN] number of address bits in a page (column 626 * address bits). 627 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 628 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 629 * @chip_shift: [INTERN] number of address bits in one chip 630 * @options: [BOARDSPECIFIC] various chip options. They can partly 631 * be set to inform nand_scan about special functionality. 632 * See the defines for further explanation. 633 * @bbt_options: [INTERN] bad block specific options. All options used 634 * here must come from bbm.h. By default, these options 635 * will be copied to the appropriate nand_bbt_descr's. 636 * @badblockpos: [INTERN] position of the bad block marker in the oob 637 * area. 638 * @badblockbits: [INTERN] minimum number of set bits in a good block's 639 * bad block marker position; i.e., BBM == 11110111b is 640 * not bad when badblockbits == 7 641 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 642 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 643 * Minimum amount of bit errors per @ecc_step_ds guaranteed 644 * to be correctable. If unknown, set to zero. 645 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 646 * also from the datasheet. It is the recommended ECC step 647 * size, if known; if unknown, set to zero. 648 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 649 * either deduced from the datasheet if the NAND 650 * chip is not ONFI compliant or set to 0 if it is 651 * (an ONFI chip is always configured in mode 0 652 * after a NAND reset) 653 * @numchips: [INTERN] number of physical chips 654 * @chipsize: [INTERN] the size of one chip for multichip arrays 655 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 656 * @pagebuf: [INTERN] holds the pagenumber which is currently in 657 * data_buf. 658 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 659 * currently in data_buf. 660 * @subpagesize: [INTERN] holds the subpagesize 661 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 662 * non 0 if ONFI supported. 663 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 664 * non 0 if JEDEC supported. 665 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 666 * supported, 0 otherwise. 667 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 668 * supported, 0 otherwise. 669 * @read_retries: [INTERN] the number of read retry modes supported 670 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 671 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 672 * @bbt: [INTERN] bad block table pointer 673 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 674 * lookup. 675 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 676 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 677 * bad block scan. 678 * @controller: [REPLACEABLE] a pointer to a hardware controller 679 * structure which is shared among multiple independent 680 * devices. 681 * @priv: [OPTIONAL] pointer to private chip data 682 * @errstat: [OPTIONAL] hardware specific function to perform 683 * additional error status checks (determine if errors are 684 * correctable). 685 * @write_page: [REPLACEABLE] High-level page write function 686 */ 687 688 struct nand_chip { 689 struct mtd_info mtd; 690 void __iomem *IO_ADDR_R; 691 void __iomem *IO_ADDR_W; 692 693 int flash_node; 694 695 uint8_t (*read_byte)(struct mtd_info *mtd); 696 u16 (*read_word)(struct mtd_info *mtd); 697 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 698 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 699 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 700 void (*select_chip)(struct mtd_info *mtd, int chip); 701 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 702 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 703 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 704 int (*dev_ready)(struct mtd_info *mtd); 705 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 706 int page_addr); 707 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 708 int (*erase)(struct mtd_info *mtd, int page); 709 int (*scan_bbt)(struct mtd_info *mtd); 710 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 711 int status, int page); 712 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 713 uint32_t offset, int data_len, const uint8_t *buf, 714 int oob_required, int page, int cached, int raw); 715 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 716 int feature_addr, uint8_t *subfeature_para); 717 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 718 int feature_addr, uint8_t *subfeature_para); 719 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 720 721 int chip_delay; 722 unsigned int options; 723 unsigned int bbt_options; 724 725 int page_shift; 726 int phys_erase_shift; 727 int bbt_erase_shift; 728 int chip_shift; 729 int numchips; 730 uint64_t chipsize; 731 int pagemask; 732 int pagebuf; 733 unsigned int pagebuf_bitflips; 734 int subpagesize; 735 uint8_t bits_per_cell; 736 uint16_t ecc_strength_ds; 737 uint16_t ecc_step_ds; 738 int onfi_timing_mode_default; 739 int badblockpos; 740 int badblockbits; 741 742 int onfi_version; 743 int jedec_version; 744 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 745 struct nand_onfi_params onfi_params; 746 #endif 747 struct nand_jedec_params jedec_params; 748 749 int read_retries; 750 751 flstate_t state; 752 753 uint8_t *oob_poi; 754 struct nand_hw_control *controller; 755 struct nand_ecclayout *ecclayout; 756 757 struct nand_ecc_ctrl ecc; 758 struct nand_buffers *buffers; 759 struct nand_hw_control hwcontrol; 760 761 uint8_t *bbt; 762 struct nand_bbt_descr *bbt_td; 763 struct nand_bbt_descr *bbt_md; 764 765 struct nand_bbt_descr *badblock_pattern; 766 767 void *priv; 768 }; 769 770 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 771 { 772 return container_of(mtd, struct nand_chip, mtd); 773 } 774 775 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 776 { 777 return &chip->mtd; 778 } 779 780 static inline void *nand_get_controller_data(struct nand_chip *chip) 781 { 782 return chip->priv; 783 } 784 785 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 786 { 787 chip->priv = priv; 788 } 789 790 /* 791 * NAND Flash Manufacturer ID Codes 792 */ 793 #define NAND_MFR_TOSHIBA 0x98 794 #define NAND_MFR_SAMSUNG 0xec 795 #define NAND_MFR_FUJITSU 0x04 796 #define NAND_MFR_NATIONAL 0x8f 797 #define NAND_MFR_RENESAS 0x07 798 #define NAND_MFR_STMICRO 0x20 799 #define NAND_MFR_HYNIX 0xad 800 #define NAND_MFR_MICRON 0x2c 801 #define NAND_MFR_AMD 0x01 802 #define NAND_MFR_MACRONIX 0xc2 803 #define NAND_MFR_EON 0x92 804 #define NAND_MFR_SANDISK 0x45 805 #define NAND_MFR_INTEL 0x89 806 #define NAND_MFR_ATO 0x9b 807 808 /* The maximum expected count of bytes in the NAND ID sequence */ 809 #define NAND_MAX_ID_LEN 8 810 811 /* 812 * A helper for defining older NAND chips where the second ID byte fully 813 * defined the chip, including the geometry (chip size, eraseblock size, page 814 * size). All these chips have 512 bytes NAND page size. 815 */ 816 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 817 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 818 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 819 820 /* 821 * A helper for defining newer chips which report their page size and 822 * eraseblock size via the extended ID bytes. 823 * 824 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 825 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 826 * device ID now only represented a particular total chip size (and voltage, 827 * buswidth), and the page size, eraseblock size, and OOB size could vary while 828 * using the same device ID. 829 */ 830 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 831 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 832 .options = (opts) } 833 834 #define NAND_ECC_INFO(_strength, _step) \ 835 { .strength_ds = (_strength), .step_ds = (_step) } 836 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 837 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 838 839 /** 840 * struct nand_flash_dev - NAND Flash Device ID Structure 841 * @name: a human-readable name of the NAND chip 842 * @dev_id: the device ID (the second byte of the full chip ID array) 843 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 844 * memory address as @id[0]) 845 * @dev_id: device ID part of the full chip ID array (refers the same memory 846 * address as @id[1]) 847 * @id: full device ID array 848 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 849 * well as the eraseblock size) is determined from the extended NAND 850 * chip ID array) 851 * @chipsize: total chip size in MiB 852 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 853 * @options: stores various chip bit options 854 * @id_len: The valid length of the @id. 855 * @oobsize: OOB size 856 * @ecc: ECC correctability and step information from the datasheet. 857 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 858 * @ecc_strength_ds in nand_chip{}. 859 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 860 * @ecc_step_ds in nand_chip{}, also from the datasheet. 861 * For example, the "4bit ECC for each 512Byte" can be set with 862 * NAND_ECC_INFO(4, 512). 863 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 864 * reset. Should be deduced from timings described 865 * in the datasheet. 866 * 867 */ 868 struct nand_flash_dev { 869 char *name; 870 union { 871 struct { 872 uint8_t mfr_id; 873 uint8_t dev_id; 874 }; 875 uint8_t id[NAND_MAX_ID_LEN]; 876 }; 877 unsigned int pagesize; 878 unsigned int chipsize; 879 unsigned int erasesize; 880 unsigned int options; 881 uint16_t id_len; 882 uint16_t oobsize; 883 struct { 884 uint16_t strength_ds; 885 uint16_t step_ds; 886 } ecc; 887 int onfi_timing_mode_default; 888 }; 889 890 /** 891 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 892 * @name: Manufacturer name 893 * @id: manufacturer ID code of device. 894 */ 895 struct nand_manufacturers { 896 int id; 897 char *name; 898 }; 899 900 extern struct nand_flash_dev nand_flash_ids[]; 901 extern struct nand_manufacturers nand_manuf_ids[]; 902 903 extern int nand_default_bbt(struct mtd_info *mtd); 904 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 905 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 906 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 907 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 908 int allowbbt); 909 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 910 size_t *retlen, uint8_t *buf); 911 912 /* 913 * Constants for oob configuration 914 */ 915 #define NAND_SMALL_BADBLOCK_POS 5 916 #define NAND_LARGE_BADBLOCK_POS 0 917 918 /** 919 * struct platform_nand_chip - chip level device structure 920 * @nr_chips: max. number of chips to scan for 921 * @chip_offset: chip number offset 922 * @nr_partitions: number of partitions pointed to by partitions (or zero) 923 * @partitions: mtd partition list 924 * @chip_delay: R/B delay value in us 925 * @options: Option flags, e.g. 16bit buswidth 926 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 927 * @part_probe_types: NULL-terminated array of probe types 928 */ 929 struct platform_nand_chip { 930 int nr_chips; 931 int chip_offset; 932 int nr_partitions; 933 struct mtd_partition *partitions; 934 int chip_delay; 935 unsigned int options; 936 unsigned int bbt_options; 937 const char **part_probe_types; 938 }; 939 940 /* Keep gcc happy */ 941 struct platform_device; 942 943 /** 944 * struct platform_nand_ctrl - controller level device structure 945 * @probe: platform specific function to probe/setup hardware 946 * @remove: platform specific function to remove/teardown hardware 947 * @hwcontrol: platform specific hardware control structure 948 * @dev_ready: platform specific function to read ready/busy pin 949 * @select_chip: platform specific chip select function 950 * @cmd_ctrl: platform specific function for controlling 951 * ALE/CLE/nCE. Also used to write command and address 952 * @write_buf: platform specific function for write buffer 953 * @read_buf: platform specific function for read buffer 954 * @read_byte: platform specific function to read one byte from chip 955 * @priv: private data to transport driver specific settings 956 * 957 * All fields are optional and depend on the hardware driver requirements 958 */ 959 struct platform_nand_ctrl { 960 int (*probe)(struct platform_device *pdev); 961 void (*remove)(struct platform_device *pdev); 962 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 963 int (*dev_ready)(struct mtd_info *mtd); 964 void (*select_chip)(struct mtd_info *mtd, int chip); 965 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 966 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 967 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 968 unsigned char (*read_byte)(struct mtd_info *mtd); 969 void *priv; 970 }; 971 972 /** 973 * struct platform_nand_data - container structure for platform-specific data 974 * @chip: chip level chip structure 975 * @ctrl: controller level device structure 976 */ 977 struct platform_nand_data { 978 struct platform_nand_chip chip; 979 struct platform_nand_ctrl ctrl; 980 }; 981 982 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 983 /* return the supported features. */ 984 static inline int onfi_feature(struct nand_chip *chip) 985 { 986 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 987 } 988 989 /* return the supported asynchronous timing mode. */ 990 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 991 { 992 if (!chip->onfi_version) 993 return ONFI_TIMING_MODE_UNKNOWN; 994 return le16_to_cpu(chip->onfi_params.async_timing_mode); 995 } 996 997 /* return the supported synchronous timing mode. */ 998 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 999 { 1000 if (!chip->onfi_version) 1001 return ONFI_TIMING_MODE_UNKNOWN; 1002 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1003 } 1004 #endif 1005 1006 /* 1007 * Check if it is a SLC nand. 1008 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1009 * We do not distinguish the MLC and TLC now. 1010 */ 1011 static inline bool nand_is_slc(struct nand_chip *chip) 1012 { 1013 return chip->bits_per_cell == 1; 1014 } 1015 1016 /** 1017 * Check if the opcode's address should be sent only on the lower 8 bits 1018 * @command: opcode to check 1019 */ 1020 static inline int nand_opcode_8bits(unsigned int command) 1021 { 1022 switch (command) { 1023 case NAND_CMD_READID: 1024 case NAND_CMD_PARAM: 1025 case NAND_CMD_GET_FEATURES: 1026 case NAND_CMD_SET_FEATURES: 1027 return 1; 1028 default: 1029 break; 1030 } 1031 return 0; 1032 } 1033 1034 /* return the supported JEDEC features. */ 1035 static inline int jedec_feature(struct nand_chip *chip) 1036 { 1037 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1038 : 0; 1039 } 1040 1041 /* Standard NAND functions from nand_base.c */ 1042 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1043 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1044 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1045 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1046 uint8_t nand_read_byte(struct mtd_info *mtd); 1047 1048 /* 1049 * struct nand_sdr_timings - SDR NAND chip timings 1050 * 1051 * This struct defines the timing requirements of a SDR NAND chip. 1052 * These informations can be found in every NAND datasheets and the timings 1053 * meaning are described in the ONFI specifications: 1054 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 1055 * Parameters) 1056 * 1057 * All these timings are expressed in picoseconds. 1058 */ 1059 1060 struct nand_sdr_timings { 1061 u32 tALH_min; 1062 u32 tADL_min; 1063 u32 tALS_min; 1064 u32 tAR_min; 1065 u32 tCEA_max; 1066 u32 tCEH_min; 1067 u32 tCH_min; 1068 u32 tCHZ_max; 1069 u32 tCLH_min; 1070 u32 tCLR_min; 1071 u32 tCLS_min; 1072 u32 tCOH_min; 1073 u32 tCS_min; 1074 u32 tDH_min; 1075 u32 tDS_min; 1076 u32 tFEAT_max; 1077 u32 tIR_min; 1078 u32 tITC_max; 1079 u32 tRC_min; 1080 u32 tREA_max; 1081 u32 tREH_min; 1082 u32 tRHOH_min; 1083 u32 tRHW_min; 1084 u32 tRHZ_max; 1085 u32 tRLOH_min; 1086 u32 tRP_min; 1087 u32 tRR_min; 1088 u64 tRST_max; 1089 u32 tWB_max; 1090 u32 tWC_min; 1091 u32 tWH_min; 1092 u32 tWHR_min; 1093 u32 tWP_min; 1094 u32 tWW_min; 1095 }; 1096 1097 /* get timing characteristics from ONFI timing mode. */ 1098 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1099 1100 int nand_check_erased_ecc_chunk(void *data, int datalen, 1101 void *ecc, int ecclen, 1102 void *extraoob, int extraooblen, 1103 int threshold); 1104 #endif /* __LINUX_MTD_NAND_H */ 1105