1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * linux/mii.h: definitions for MII-compatible transceivers 4 * Originally drivers/net/sunhme.h. 5 * 6 * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) 7 */ 8 9 #ifndef __LINUX_MII_H__ 10 #define __LINUX_MII_H__ 11 12 /* Generic MII registers. */ 13 #define MII_BMCR 0x00 /* Basic mode control register */ 14 #define MII_BMSR 0x01 /* Basic mode status register */ 15 #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 16 #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 17 #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 18 #define MII_LPA 0x05 /* Link partner ability reg */ 19 #define MII_EXPANSION 0x06 /* Expansion register */ 20 #define MII_CTRL1000 0x09 /* 1000BASE-T control */ 21 #define MII_STAT1000 0x0a /* 1000BASE-T status */ 22 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 23 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 24 #define MII_ESTATUS 0x0f /* Extended Status */ 25 #define MII_DCOUNTER 0x12 /* Disconnect counter */ 26 #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 27 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 28 #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 29 #define MII_SREVISION 0x16 /* Silicon revision */ 30 #define MII_RESV1 0x17 /* Reserved... */ 31 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 32 #define MII_PHYADDR 0x19 /* PHY address */ 33 #define MII_RESV2 0x1a /* Reserved... */ 34 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 35 #define MII_NCONFIG 0x1c /* Network interface config */ 36 37 /* Basic mode control register. */ 38 #define BMCR_RESV 0x003f /* Unused... */ 39 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ 40 #define BMCR_CTST 0x0080 /* Collision test */ 41 #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 42 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 43 #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ 44 #define BMCR_PDOWN 0x0800 /* Enable low power state */ 45 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 46 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 47 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 48 #define BMCR_RESET 0x8000 /* Reset to default state */ 49 #define BMCR_SPEED10 0x0000 /* Select 10Mbps */ 50 51 /* Basic mode status register. */ 52 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 53 #define BMSR_JCD 0x0002 /* Jabber detected */ 54 #define BMSR_LSTATUS 0x0004 /* Link status */ 55 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 56 #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 57 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 58 #define BMSR_RESV 0x00c0 /* Unused... */ 59 #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ 60 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ 61 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ 62 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 63 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 64 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 65 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 66 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 67 68 /* Advertisement control register. */ 69 #define ADVERTISE_SLCT 0x001f /* Selector bits */ 70 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 71 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 72 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ 73 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 74 #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ 75 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 76 #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ 77 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 78 #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ 79 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 80 #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ 81 #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ 82 #define ADVERTISE_RESV 0x1000 /* Unused... */ 83 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 84 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 85 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 86 87 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 88 ADVERTISE_CSMA) 89 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 90 ADVERTISE_100HALF | ADVERTISE_100FULL) 91 92 /* Link partner ability register. */ 93 #define LPA_SLCT 0x001f /* Same as advertise selector */ 94 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 95 #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ 96 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 97 #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ 98 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 99 #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ 100 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 101 #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ 102 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 103 #define LPA_PAUSE_CAP 0x0400 /* Can pause */ 104 #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ 105 #define LPA_RESV 0x1000 /* Unused... */ 106 #define LPA_RFAULT 0x2000 /* Link partner faulted */ 107 #define LPA_LPACK 0x4000 /* Link partner acked us */ 108 #define LPA_NPAGE 0x8000 /* Next page bit */ 109 110 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 111 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 112 113 /* Expansion register for auto-negotiation. */ 114 #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ 115 #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ 116 #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ 117 #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ 118 #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ 119 #define EXPANSION_RESV 0xffe0 /* Unused... */ 120 121 #define ESTATUS_1000_XFULL 0x8000 /* Can do 1000BX Full */ 122 #define ESTATUS_1000_XHALF 0x4000 /* Can do 1000BX Half */ 123 #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ 124 #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ 125 126 /* N-way test register. */ 127 #define NWAYTEST_RESV1 0x00ff /* Unused... */ 128 #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ 129 #define NWAYTEST_RESV2 0xfe00 /* Unused... */ 130 131 /* 1000BASE-T Control register */ 132 #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ 133 #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ 134 #define CTL1000_AS_MASTER 0x0800 135 #define CTL1000_ENABLE_MASTER 0x1000 136 137 /* 1000BASE-T Status register */ 138 #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ 139 #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ 140 #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ 141 #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ 142 143 /* Flow control flags */ 144 #define FLOW_CTRL_TX 0x01 145 #define FLOW_CTRL_RX 0x02 146 147 /* MMD Access Control register fields */ 148 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ 149 #define MII_MMD_CTRL_ADDR 0x0000 /* Address */ 150 #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ 151 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ 152 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ 153 154 /** 155 * mii_nway_result 156 * @negotiated: value of MII ANAR and'd with ANLPAR 157 * 158 * Given a set of MII abilities, check each bit and returns the 159 * currently supported media, in the priority order defined by 160 * IEEE 802.3u. We use LPA_xxx constants but note this is not the 161 * value of LPA solely, as described above. 162 * 163 * The one exception to IEEE 802.3u is that 100baseT4 is placed 164 * between 100T-full and 100T-half. If your phy does not support 165 * 100T4 this is fine. If your phy places 100T4 elsewhere in the 166 * priority order, you will need to roll your own function. 167 */ 168 static inline unsigned int mii_nway_result (unsigned int negotiated) 169 { 170 unsigned int ret; 171 172 if (negotiated & LPA_100FULL) 173 ret = LPA_100FULL; 174 else if (negotiated & LPA_100BASE4) 175 ret = LPA_100BASE4; 176 else if (negotiated & LPA_100HALF) 177 ret = LPA_100HALF; 178 else if (negotiated & LPA_10FULL) 179 ret = LPA_10FULL; 180 else 181 ret = LPA_10HALF; 182 183 return ret; 184 } 185 186 /** 187 * mii_duplex 188 * @duplex_lock: Non-zero if duplex is locked at full 189 * @negotiated: value of MII ANAR and'd with ANLPAR 190 * 191 * A small helper function for a common case. Returns one 192 * if the media is operating or locked at full duplex, and 193 * returns zero otherwise. 194 */ 195 static inline unsigned int mii_duplex (unsigned int duplex_lock, 196 unsigned int negotiated) 197 { 198 if (duplex_lock) 199 return 1; 200 if (mii_nway_result(negotiated) & LPA_DUPLEX) 201 return 1; 202 return 0; 203 } 204 205 /** 206 * mii_resolve_flowctrl_fdx 207 * @lcladv: value of MII ADVERTISE register 208 * @rmtadv: value of MII LPA register 209 * 210 * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3 211 */ 212 static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv) 213 { 214 u8 cap = 0; 215 216 if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) { 217 cap = FLOW_CTRL_TX | FLOW_CTRL_RX; 218 } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) { 219 if (lcladv & ADVERTISE_PAUSE_CAP) 220 cap = FLOW_CTRL_RX; 221 else if (rmtadv & ADVERTISE_PAUSE_CAP) 222 cap = FLOW_CTRL_TX; 223 } 224 225 return cap; 226 } 227 228 #endif /* __LINUX_MII_H__ */ 229