xref: /openbmc/u-boot/include/linux/mc146818rtc.h (revision 8e6f1a8e)
1 /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
2  * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
3  * derived from Data Sheet, Copyright Motorola 1984 (!).
4  * It was written to be part of the Linux operating system.
5  */
6 /* permission is hereby granted to copy, modify and redistribute this code
7  * in terms of the GNU Library General Public License, Version 2 or later,
8  * at your option.
9  */
10 
11 #ifndef _MC146818RTC_H
12 #define _MC146818RTC_H
13 
14 #include <asm/io.h>
15 #include <linux/rtc.h>          /* get the user-level API */
16 #include <asm/mc146818rtc.h>        /* register access macros */
17 
18 /**********************************************************************
19  * register summary
20  **********************************************************************/
21 #define RTC_SECONDS     0
22 #define RTC_SECONDS_ALARM   1
23 #define RTC_MINUTES     2
24 #define RTC_MINUTES_ALARM   3
25 #define RTC_HOURS       4
26 #define RTC_HOURS_ALARM     5
27 /* RTC_*_alarm is always true if 2 MSBs are set */
28 # define RTC_ALARM_DONT_CARE    0xC0
29 
30 #define RTC_DAY_OF_WEEK     6
31 #define RTC_DAY_OF_MONTH    7
32 #define RTC_MONTH       8
33 #define RTC_YEAR        9
34 
35 /* control registers - Moto names
36  */
37 #define RTC_REG_A       10
38 #define RTC_REG_B       11
39 #define RTC_REG_C       12
40 #define RTC_REG_D       13
41 
42 /**********************************************************************
43  * register details
44  **********************************************************************/
45 #define RTC_FREQ_SELECT RTC_REG_A
46 
47 /* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
48  * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
49  * totalling to a max high interval of 2.228 ms.
50  */
51 # define RTC_UIP        0x80
52 # define RTC_DIV_CTL        0x70
53    /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
54 #  define RTC_REF_CLCK_4MHZ 0x00
55 #  define RTC_REF_CLCK_1MHZ 0x10
56 #  define RTC_REF_CLCK_32KHZ    0x20
57    /* 2 values for divider stage reset, others for "testing purposes only" */
58 #  define RTC_DIV_RESET1    0x60
59 #  define RTC_DIV_RESET2    0x70
60   /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
61 # define RTC_RATE_SELECT    0x0F
62 
63 /**********************************************************************/
64 #define RTC_CONTROL RTC_REG_B
65 # define RTC_SET 0x80       /* disable updates for clock setting */
66 # define RTC_PIE 0x40       /* periodic interrupt enable */
67 # define RTC_AIE 0x20       /* alarm interrupt enable */
68 # define RTC_UIE 0x10       /* update-finished interrupt enable */
69 # define RTC_SQWE 0x08      /* enable square-wave output */
70 # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
71 # define RTC_24H 0x02       /* 24 hour mode - else hours bit 7 means pm */
72 # define RTC_DST_EN 0x01    /* auto switch DST - works f. USA only */
73 
74 /**********************************************************************/
75 #define RTC_INTR_FLAGS  RTC_REG_C
76 /* caution - cleared by read */
77 # define RTC_IRQF 0x80      /* any of the following 3 is active */
78 # define RTC_PF 0x40
79 # define RTC_AF 0x20
80 # define RTC_UF 0x10
81 
82 /**********************************************************************/
83 #define RTC_VALID   RTC_REG_D
84 # define RTC_VRT 0x80       /* valid RAM and time */
85 /**********************************************************************/
86 
87 /* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
88  * determines if the following two #defines are needed
89  */
90 #ifndef BCD_TO_BIN
91 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
92 #endif
93 
94 #ifndef BIN_TO_BCD
95 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
96 #endif
97 
98 #endif /* _MC146818RTC_H */
99