1 /* 2 * QUICC Engine (QE) Internal Memory Map. 3 * The Internal Memory Map for devices with QE on them. This 4 * is the superset of all QE devices (8360, etc.). 5 * 6 * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc. 7 * Author: Shlomi Gridih <gridish@freescale.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __IMMAP_QE_H__ 13 #define __IMMAP_QE_H__ 14 15 #ifdef CONFIG_MPC83xx 16 #if defined(CONFIG_MPC8360) 17 #define QE_MURAM_SIZE 0xc000UL 18 #define MAX_QE_RISC 2 19 #define QE_NUM_OF_SNUM 28 20 #elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309) 21 #define QE_MURAM_SIZE 0x4000UL 22 #define MAX_QE_RISC 1 23 #define QE_NUM_OF_SNUM 28 24 #endif 25 #endif 26 27 /* QE I-RAM */ 28 typedef struct qe_iram { 29 u32 iadd; /* I-RAM Address Register */ 30 u32 idata; /* I-RAM Data Register */ 31 u8 res0[0x4]; 32 u32 iready; 33 u8 res1[0x70]; 34 } __attribute__ ((packed)) qe_iram_t; 35 36 /* QE Interrupt Controller */ 37 typedef struct qe_ic { 38 u32 qicr; 39 u32 qivec; 40 u32 qripnr; 41 u32 qipnr; 42 u32 qipxcc; 43 u32 qipycc; 44 u32 qipwcc; 45 u32 qipzcc; 46 u32 qimr; 47 u32 qrimr; 48 u32 qicnr; 49 u8 res0[0x4]; 50 u32 qiprta; 51 u32 qiprtb; 52 u8 res1[0x4]; 53 u32 qricr; 54 u8 res2[0x20]; 55 u32 qhivec; 56 u8 res3[0x1C]; 57 } __attribute__ ((packed)) qe_ic_t; 58 59 /* Communications Processor */ 60 typedef struct cp_qe { 61 u32 cecr; /* QE command register */ 62 u32 ceccr; /* QE controller configuration register */ 63 u32 cecdr; /* QE command data register */ 64 u8 res0[0xA]; 65 u16 ceter; /* QE timer event register */ 66 u8 res1[0x2]; 67 u16 cetmr; /* QE timers mask register */ 68 u32 cetscr; /* QE time-stamp timer control register */ 69 u32 cetsr1; /* QE time-stamp register 1 */ 70 u32 cetsr2; /* QE time-stamp register 2 */ 71 u8 res2[0x8]; 72 u32 cevter; /* QE virtual tasks event register */ 73 u32 cevtmr; /* QE virtual tasks mask register */ 74 u16 cercr; /* QE RAM control register */ 75 u8 res3[0x2]; 76 u8 res4[0x24]; 77 u16 ceexe1; /* QE external request 1 event register */ 78 u8 res5[0x2]; 79 u16 ceexm1; /* QE external request 1 mask register */ 80 u8 res6[0x2]; 81 u16 ceexe2; /* QE external request 2 event register */ 82 u8 res7[0x2]; 83 u16 ceexm2; /* QE external request 2 mask register */ 84 u8 res8[0x2]; 85 u16 ceexe3; /* QE external request 3 event register */ 86 u8 res9[0x2]; 87 u16 ceexm3; /* QE external request 3 mask register */ 88 u8 res10[0x2]; 89 u16 ceexe4; /* QE external request 4 event register */ 90 u8 res11[0x2]; 91 u16 ceexm4; /* QE external request 4 mask register */ 92 u8 res12[0x2]; 93 u8 res13[0x280]; 94 } __attribute__ ((packed)) cp_qe_t; 95 96 /* QE Multiplexer */ 97 typedef struct qe_mux { 98 u32 cmxgcr; /* CMX general clock route register */ 99 u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ 100 u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ 101 u32 cmxsi1syr; /* CMX SI1 SYNC route register */ 102 u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ 103 u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ 104 u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ 105 u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ 106 u32 cmxupcr; /* CMX UPC clock route register */ 107 u8 res0[0x1C]; 108 } __attribute__ ((packed)) qe_mux_t; 109 110 /* QE Timers */ 111 typedef struct qe_timers { 112 u8 gtcfr1; /* Timer 1 2 global configuration register */ 113 u8 res0[0x3]; 114 u8 gtcfr2; /* Timer 3 4 global configuration register */ 115 u8 res1[0xB]; 116 u16 gtmdr1; /* Timer 1 mode register */ 117 u16 gtmdr2; /* Timer 2 mode register */ 118 u16 gtrfr1; /* Timer 1 reference register */ 119 u16 gtrfr2; /* Timer 2 reference register */ 120 u16 gtcpr1; /* Timer 1 capture register */ 121 u16 gtcpr2; /* Timer 2 capture register */ 122 u16 gtcnr1; /* Timer 1 counter */ 123 u16 gtcnr2; /* Timer 2 counter */ 124 u16 gtmdr3; /* Timer 3 mode register */ 125 u16 gtmdr4; /* Timer 4 mode register */ 126 u16 gtrfr3; /* Timer 3 reference register */ 127 u16 gtrfr4; /* Timer 4 reference register */ 128 u16 gtcpr3; /* Timer 3 capture register */ 129 u16 gtcpr4; /* Timer 4 capture register */ 130 u16 gtcnr3; /* Timer 3 counter */ 131 u16 gtcnr4; /* Timer 4 counter */ 132 u16 gtevr1; /* Timer 1 event register */ 133 u16 gtevr2; /* Timer 2 event register */ 134 u16 gtevr3; /* Timer 3 event register */ 135 u16 gtevr4; /* Timer 4 event register */ 136 u16 gtps; /* Timer 1 prescale register */ 137 u8 res2[0x46]; 138 } __attribute__ ((packed)) qe_timers_t; 139 140 /* BRG */ 141 typedef struct qe_brg { 142 u32 brgc1; /* BRG1 configuration register */ 143 u32 brgc2; /* BRG2 configuration register */ 144 u32 brgc3; /* BRG3 configuration register */ 145 u32 brgc4; /* BRG4 configuration register */ 146 u32 brgc5; /* BRG5 configuration register */ 147 u32 brgc6; /* BRG6 configuration register */ 148 u32 brgc7; /* BRG7 configuration register */ 149 u32 brgc8; /* BRG8 configuration register */ 150 u32 brgc9; /* BRG9 configuration register */ 151 u32 brgc10; /* BRG10 configuration register */ 152 u32 brgc11; /* BRG11 configuration register */ 153 u32 brgc12; /* BRG12 configuration register */ 154 u32 brgc13; /* BRG13 configuration register */ 155 u32 brgc14; /* BRG14 configuration register */ 156 u32 brgc15; /* BRG15 configuration register */ 157 u32 brgc16; /* BRG16 configuration register */ 158 u8 res0[0x40]; 159 } __attribute__ ((packed)) qe_brg_t; 160 161 /* SPI */ 162 typedef struct spi { 163 u8 res0[0x20]; 164 u32 spmode; /* SPI mode register */ 165 u8 res1[0x2]; 166 u8 spie; /* SPI event register */ 167 u8 res2[0x1]; 168 u8 res3[0x2]; 169 u8 spim; /* SPI mask register */ 170 u8 res4[0x1]; 171 u8 res5[0x1]; 172 u8 spcom; /* SPI command register */ 173 u8 res6[0x2]; 174 u32 spitd; /* SPI transmit data register (cpu mode) */ 175 u32 spird; /* SPI receive data register (cpu mode) */ 176 u8 res7[0x8]; 177 } __attribute__ ((packed)) spi_t; 178 179 /* SI */ 180 typedef struct si1 { 181 u16 siamr1; /* SI1 TDMA mode register */ 182 u16 sibmr1; /* SI1 TDMB mode register */ 183 u16 sicmr1; /* SI1 TDMC mode register */ 184 u16 sidmr1; /* SI1 TDMD mode register */ 185 u8 siglmr1_h; /* SI1 global mode register high */ 186 u8 res0[0x1]; 187 u8 sicmdr1_h; /* SI1 command register high */ 188 u8 res2[0x1]; 189 u8 sistr1_h; /* SI1 status register high */ 190 u8 res3[0x1]; 191 u16 sirsr1_h; /* SI1 RAM shadow address register high */ 192 u8 sitarc1; /* SI1 RAM counter Tx TDMA */ 193 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ 194 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ 195 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ 196 u8 sirarc1; /* SI1 RAM counter Rx TDMA */ 197 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ 198 u8 sircrc1; /* SI1 RAM counter Rx TDMC */ 199 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ 200 u8 res4[0x8]; 201 u16 siemr1; /* SI1 TDME mode register 16 bits */ 202 u16 sifmr1; /* SI1 TDMF mode register 16 bits */ 203 u16 sigmr1; /* SI1 TDMG mode register 16 bits */ 204 u16 sihmr1; /* SI1 TDMH mode register 16 bits */ 205 u8 siglmg1_l; /* SI1 global mode register low 8 bits */ 206 u8 res5[0x1]; 207 u8 sicmdr1_l; /* SI1 command register low 8 bits */ 208 u8 res6[0x1]; 209 u8 sistr1_l; /* SI1 status register low 8 bits */ 210 u8 res7[0x1]; 211 u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ 212 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ 213 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ 214 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ 215 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ 216 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ 217 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ 218 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ 219 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ 220 u8 res8[0x8]; 221 u32 siml1; /* SI1 multiframe limit register */ 222 u8 siedm1; /* SI1 extended diagnostic mode register */ 223 u8 res9[0xBB]; 224 } __attribute__ ((packed)) si1_t; 225 226 /* SI Routing Tables */ 227 typedef struct sir { 228 u8 tx[0x400]; 229 u8 rx[0x400]; 230 u8 res0[0x800]; 231 } __attribute__ ((packed)) sir_t; 232 233 /* USB Controller. */ 234 typedef struct usb_ctlr { 235 u8 usb_usmod; 236 u8 usb_usadr; 237 u8 usb_uscom; 238 u8 res1[1]; 239 u16 usb_usep1; 240 u16 usb_usep2; 241 u16 usb_usep3; 242 u16 usb_usep4; 243 u8 res2[4]; 244 u16 usb_usber; 245 u8 res3[2]; 246 u16 usb_usbmr; 247 u8 res4[1]; 248 u8 usb_usbs; 249 u16 usb_ussft; 250 u8 res5[2]; 251 u16 usb_usfrn; 252 u8 res6[0x22]; 253 } __attribute__ ((packed)) usb_t; 254 255 /* MCC */ 256 typedef struct mcc { 257 u32 mcce; /* MCC event register */ 258 u32 mccm; /* MCC mask register */ 259 u32 mccf; /* MCC configuration register */ 260 u32 merl; /* MCC emergency request level register */ 261 u8 res0[0xF0]; 262 } __attribute__ ((packed)) mcc_t; 263 264 /* QE UCC Slow */ 265 typedef struct ucc_slow { 266 u32 gumr_l; /* UCCx general mode register (low) */ 267 u32 gumr_h; /* UCCx general mode register (high) */ 268 u16 upsmr; /* UCCx protocol-specific mode register */ 269 u8 res0[0x2]; 270 u16 utodr; /* UCCx transmit on demand register */ 271 u16 udsr; /* UCCx data synchronization register */ 272 u16 ucce; /* UCCx event register */ 273 u8 res1[0x2]; 274 u16 uccm; /* UCCx mask register */ 275 u8 res2[0x1]; 276 u8 uccs; /* UCCx status register */ 277 u8 res3[0x24]; 278 u16 utpt; 279 u8 guemr; /* UCC general extended mode register */ 280 u8 res4[0x200 - 0x091]; 281 } __attribute__ ((packed)) ucc_slow_t; 282 283 typedef struct ucc_mii_mng { 284 u32 miimcfg; /* MII management configuration reg */ 285 u32 miimcom; /* MII management command reg */ 286 u32 miimadd; /* MII management address reg */ 287 u32 miimcon; /* MII management control reg */ 288 u32 miimstat; /* MII management status reg */ 289 u32 miimind; /* MII management indication reg */ 290 u32 ifctl; /* interface control reg */ 291 u32 ifstat; /* interface statux reg */ 292 } __attribute__ ((packed))uec_mii_t; 293 294 typedef struct ucc_ethernet { 295 u32 maccfg1; /* mac configuration reg. 1 */ 296 u32 maccfg2; /* mac configuration reg. 2 */ 297 u32 ipgifg; /* interframe gap reg. */ 298 u32 hafdup; /* half-duplex reg. */ 299 u8 res1[0x10]; 300 u32 miimcfg; /* MII management configuration reg */ 301 u32 miimcom; /* MII management command reg */ 302 u32 miimadd; /* MII management address reg */ 303 u32 miimcon; /* MII management control reg */ 304 u32 miimstat; /* MII management status reg */ 305 u32 miimind; /* MII management indication reg */ 306 u32 ifctl; /* interface control reg */ 307 u32 ifstat; /* interface statux reg */ 308 u32 macstnaddr1; /* mac station address part 1 reg */ 309 u32 macstnaddr2; /* mac station address part 2 reg */ 310 u8 res2[0x8]; 311 u32 uempr; /* UCC Ethernet Mac parameter reg */ 312 u32 utbipar; /* UCC tbi address reg */ 313 u16 uescr; /* UCC Ethernet statistics control reg */ 314 u8 res3[0x180 - 0x15A]; 315 u32 tx64; /* Total number of frames (including bad 316 * frames) transmitted that were exactly 317 * of the minimal length (64 for un tagged, 318 * 68 for tagged, or with length exactly 319 * equal to the parameter MINLength */ 320 u32 tx127; /* Total number of frames (including bad 321 * frames) transmitted that were between 322 * MINLength (Including FCS length==4) 323 * and 127 octets */ 324 u32 tx255; /* Total number of frames (including bad 325 * frames) transmitted that were between 326 * 128 (Including FCS length==4) and 255 327 * octets */ 328 u32 rx64; /* Total number of frames received including 329 * bad frames that were exactly of the 330 * mninimal length (64 bytes) */ 331 u32 rx127; /* Total number of frames (including bad 332 * frames) received that were between 333 * MINLength (Including FCS length==4) 334 * and 127 octets */ 335 u32 rx255; /* Total number of frames (including 336 * bad frames) received that were between 337 * 128 (Including FCS length==4) and 255 338 * octets */ 339 u32 txok; /* Total number of octets residing in frames 340 * that where involved in succesfull 341 * transmission */ 342 u16 txcf; /* Total number of PAUSE control frames 343 * transmitted by this MAC */ 344 u8 res4[0x2]; 345 u32 tmca; /* Total number of frames that were transmitted 346 * succesfully with the group address bit set 347 * that are not broadcast frames */ 348 u32 tbca; /* Total number of frames transmitted 349 * succesfully that had destination address 350 * field equal to the broadcast address */ 351 u32 rxfok; /* Total number of frames received OK */ 352 u32 rxbok; /* Total number of octets received OK */ 353 u32 rbyt; /* Total number of octets received including 354 * octets in bad frames. Must be implemented 355 * in HW because it includes octets in frames 356 * that never even reach the UCC */ 357 u32 rmca; /* Total number of frames that were received 358 * succesfully with the group address bit set 359 * that are not broadcast frames */ 360 u32 rbca; /* Total number of frames received succesfully 361 * that had destination address equal to the 362 * broadcast address */ 363 u32 scar; /* Statistics carry register */ 364 u32 scam; /* Statistics caryy mask register */ 365 u8 res5[0x200 - 0x1c4]; 366 } __attribute__ ((packed)) uec_t; 367 368 /* QE UCC Fast */ 369 typedef struct ucc_fast { 370 u32 gumr; /* UCCx general mode register */ 371 u32 upsmr; /* UCCx protocol-specific mode register */ 372 u16 utodr; /* UCCx transmit on demand register */ 373 u8 res0[0x2]; 374 u16 udsr; /* UCCx data synchronization register */ 375 u8 res1[0x2]; 376 u32 ucce; /* UCCx event register */ 377 u32 uccm; /* UCCx mask register. */ 378 u8 uccs; /* UCCx status register */ 379 u8 res2[0x7]; 380 u32 urfb; /* UCC receive FIFO base */ 381 u16 urfs; /* UCC receive FIFO size */ 382 u8 res3[0x2]; 383 u16 urfet; /* UCC receive FIFO emergency threshold */ 384 u16 urfset; /* UCC receive FIFO special emergency 385 * threshold */ 386 u32 utfb; /* UCC transmit FIFO base */ 387 u16 utfs; /* UCC transmit FIFO size */ 388 u8 res4[0x2]; 389 u16 utfet; /* UCC transmit FIFO emergency threshold */ 390 u8 res5[0x2]; 391 u16 utftt; /* UCC transmit FIFO transmit threshold */ 392 u8 res6[0x2]; 393 u16 utpt; /* UCC transmit polling timer */ 394 u8 res7[0x2]; 395 u32 urtry; /* UCC retry counter register */ 396 u8 res8[0x4C]; 397 u8 guemr; /* UCC general extended mode register */ 398 u8 res9[0x100 - 0x091]; 399 uec_t ucc_eth; 400 } __attribute__ ((packed)) ucc_fast_t; 401 402 /* QE UCC */ 403 typedef struct ucc_common { 404 u8 res1[0x90]; 405 u8 guemr; 406 u8 res2[0x200 - 0x091]; 407 } __attribute__ ((packed)) ucc_common_t; 408 409 typedef struct ucc { 410 union { 411 ucc_slow_t slow; 412 ucc_fast_t fast; 413 ucc_common_t common; 414 }; 415 } __attribute__ ((packed)) ucc_t; 416 417 /* MultiPHY UTOPIA POS Controllers (UPC) */ 418 typedef struct upc { 419 u32 upgcr; /* UTOPIA/POS general configuration register */ 420 u32 uplpa; /* UTOPIA/POS last PHY address */ 421 u32 uphec; /* ATM HEC register */ 422 u32 upuc; /* UTOPIA/POS UCC configuration */ 423 u32 updc1; /* UTOPIA/POS device 1 configuration */ 424 u32 updc2; /* UTOPIA/POS device 2 configuration */ 425 u32 updc3; /* UTOPIA/POS device 3 configuration */ 426 u32 updc4; /* UTOPIA/POS device 4 configuration */ 427 u32 upstpa; /* UTOPIA/POS STPA threshold */ 428 u8 res0[0xC]; 429 u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ 430 u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ 431 u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ 432 u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ 433 u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ 434 u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ 435 u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ 436 u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ 437 u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ 438 u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ 439 u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ 440 u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ 441 u32 upde1; /* UTOPIA/POS device 1 event */ 442 u32 upde2; /* UTOPIA/POS device 2 event */ 443 u32 upde3; /* UTOPIA/POS device 3 event */ 444 u32 upde4; /* UTOPIA/POS device 4 event */ 445 u16 uprp1; 446 u16 uprp2; 447 u16 uprp3; 448 u16 uprp4; 449 u8 res1[0x8]; 450 u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ 451 u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ 452 u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ 453 u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ 454 u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ 455 u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ 456 u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ 457 u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ 458 u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ 459 u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ 460 u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ 461 u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ 462 u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ 463 u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ 464 u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ 465 u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ 466 u32 uper1; /* Device 1 port enable register */ 467 u32 uper2; /* Device 2 port enable register */ 468 u32 uper3; /* Device 3 port enable register */ 469 u32 uper4; /* Device 4 port enable register */ 470 u8 res2[0x150]; 471 } __attribute__ ((packed)) upc_t; 472 473 /* SDMA */ 474 typedef struct sdma { 475 u32 sdsr; /* Serial DMA status register */ 476 u32 sdmr; /* Serial DMA mode register */ 477 u32 sdtr1; /* SDMA system bus threshold register */ 478 u32 sdtr2; /* SDMA secondary bus threshold register */ 479 u32 sdhy1; /* SDMA system bus hysteresis register */ 480 u32 sdhy2; /* SDMA secondary bus hysteresis register */ 481 u32 sdta1; /* SDMA system bus address register */ 482 u32 sdta2; /* SDMA secondary bus address register */ 483 u32 sdtm1; /* SDMA system bus MSNUM register */ 484 u32 sdtm2; /* SDMA secondary bus MSNUM register */ 485 u8 res0[0x10]; 486 u32 sdaqr; /* SDMA address bus qualify register */ 487 u32 sdaqmr; /* SDMA address bus qualify mask register */ 488 u8 res1[0x4]; 489 u32 sdwbcr; /* SDMA CAM entries base register */ 490 u8 res2[0x38]; 491 } __attribute__ ((packed)) sdma_t; 492 493 /* Debug Space */ 494 typedef struct dbg { 495 u32 bpdcr; /* Breakpoint debug command register */ 496 u32 bpdsr; /* Breakpoint debug status register */ 497 u32 bpdmr; /* Breakpoint debug mask register */ 498 u32 bprmrr0; /* Breakpoint request mode risc register 0 */ 499 u32 bprmrr1; /* Breakpoint request mode risc register 1 */ 500 u8 res0[0x8]; 501 u32 bprmtr0; /* Breakpoint request mode trb register 0 */ 502 u32 bprmtr1; /* Breakpoint request mode trb register 1 */ 503 u8 res1[0x8]; 504 u32 bprmir; /* Breakpoint request mode immediate register */ 505 u32 bprmsr; /* Breakpoint request mode serial register */ 506 u32 bpemr; /* Breakpoint exit mode register */ 507 u8 res2[0x48]; 508 } __attribute__ ((packed)) dbg_t; 509 510 /* 511 * RISC Special Registers (Trap and Breakpoint). These are described in 512 * the QE Developer's Handbook. 513 */ 514 typedef struct rsp { 515 u32 tibcr[16]; /* Trap/instruction breakpoint control regs */ 516 u8 res0[64]; 517 u32 ibcr0; 518 u32 ibs0; 519 u32 ibcnr0; 520 u8 res1[4]; 521 u32 ibcr1; 522 u32 ibs1; 523 u32 ibcnr1; 524 u32 npcr; 525 u32 dbcr; 526 u32 dbar; 527 u32 dbamr; 528 u32 dbsr; 529 u32 dbcnr; 530 u8 res2[12]; 531 u32 dbdr_h; 532 u32 dbdr_l; 533 u32 dbdmr_h; 534 u32 dbdmr_l; 535 u32 bsr; 536 u32 bor; 537 u32 bior; 538 u8 res3[4]; 539 u32 iatr[4]; 540 u32 eccr; /* Exception control configuration register */ 541 u32 eicr; 542 u8 res4[0x100-0xf8]; 543 } __attribute__ ((packed)) rsp_t; 544 545 typedef struct qe_immap { 546 qe_iram_t iram; /* I-RAM */ 547 qe_ic_t ic; /* Interrupt Controller */ 548 cp_qe_t cp; /* Communications Processor */ 549 qe_mux_t qmx; /* QE Multiplexer */ 550 qe_timers_t qet; /* QE Timers */ 551 spi_t spi[0x2]; /* spi */ 552 mcc_t mcc; /* mcc */ 553 qe_brg_t brg; /* brg */ 554 usb_t usb; /* USB */ 555 si1_t si1; /* SI */ 556 u8 res11[0x800]; 557 sir_t sir; /* SI Routing Tables */ 558 ucc_t ucc1; /* ucc1 */ 559 ucc_t ucc3; /* ucc3 */ 560 ucc_t ucc5; /* ucc5 */ 561 ucc_t ucc7; /* ucc7 */ 562 u8 res12[0x600]; 563 upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ 564 ucc_t ucc2; /* ucc2 */ 565 ucc_t ucc4; /* ucc4 */ 566 ucc_t ucc6; /* ucc6 */ 567 ucc_t ucc8; /* ucc8 */ 568 u8 res13[0x600]; 569 upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ 570 sdma_t sdma; /* SDMA */ 571 dbg_t dbg; /* Debug Space */ 572 rsp_t rsp[0x2]; /* RISC Special Registers 573 * (Trap and Breakpoint) */ 574 u8 res14[0x300]; 575 u8 res15[0x3A00]; 576 u8 res16[0x8000]; /* 0x108000 - 0x110000 */ 577 u8 muram[QE_MURAM_SIZE]; 578 } __attribute__ ((packed)) qe_map_t; 579 580 extern qe_map_t *qe_immr; 581 582 #endif /* __IMMAP_QE_H__ */ 583