1*490f5fd2SSimon Glass /* 2*490f5fd2SSimon Glass * Copyright © 2008 Keith Packard 3*490f5fd2SSimon Glass * 4*490f5fd2SSimon Glass * Permission to use, copy, modify, distribute, and sell this software and its 5*490f5fd2SSimon Glass * documentation for any purpose is hereby granted without fee, provided that 6*490f5fd2SSimon Glass * the above copyright notice appear in all copies and that both that copyright 7*490f5fd2SSimon Glass * notice and this permission notice appear in supporting documentation, and 8*490f5fd2SSimon Glass * that the name of the copyright holders not be used in advertising or 9*490f5fd2SSimon Glass * publicity pertaining to distribution of the software without specific, 10*490f5fd2SSimon Glass * written prior permission. The copyright holders make no representations 11*490f5fd2SSimon Glass * about the suitability of this software for any purpose. It is provided "as 12*490f5fd2SSimon Glass * is" without express or implied warranty. 13*490f5fd2SSimon Glass * 14*490f5fd2SSimon Glass * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15*490f5fd2SSimon Glass * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16*490f5fd2SSimon Glass * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17*490f5fd2SSimon Glass * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18*490f5fd2SSimon Glass * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19*490f5fd2SSimon Glass * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20*490f5fd2SSimon Glass * OF THIS SOFTWARE. 21*490f5fd2SSimon Glass */ 22*490f5fd2SSimon Glass 23*490f5fd2SSimon Glass #ifndef _DRM_DP_HELPER_H_ 24*490f5fd2SSimon Glass #define _DRM_DP_HELPER_H_ 25*490f5fd2SSimon Glass 26*490f5fd2SSimon Glass /* 27*490f5fd2SSimon Glass * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 28*490f5fd2SSimon Glass * DP and DPCD versions are independent. Differences from 1.0 are not noted, 29*490f5fd2SSimon Glass * 1.0 devices basically don't exist in the wild. 30*490f5fd2SSimon Glass * 31*490f5fd2SSimon Glass * Abbreviations, in chronological order: 32*490f5fd2SSimon Glass * 33*490f5fd2SSimon Glass * eDP: Embedded DisplayPort version 1 34*490f5fd2SSimon Glass * DPI: DisplayPort Interoperability Guideline v1.1a 35*490f5fd2SSimon Glass * 1.2: DisplayPort 1.2 36*490f5fd2SSimon Glass * MST: Multistream Transport - part of DP 1.2a 37*490f5fd2SSimon Glass * 38*490f5fd2SSimon Glass * 1.2 formally includes both eDP and DPI definitions. 39*490f5fd2SSimon Glass */ 40*490f5fd2SSimon Glass 41*490f5fd2SSimon Glass #define DP_AUX_I2C_WRITE 0x0 42*490f5fd2SSimon Glass #define DP_AUX_I2C_READ 0x1 43*490f5fd2SSimon Glass #define DP_AUX_I2C_STATUS 0x2 44*490f5fd2SSimon Glass #define DP_AUX_I2C_MOT 0x4 45*490f5fd2SSimon Glass #define DP_AUX_NATIVE_WRITE 0x8 46*490f5fd2SSimon Glass #define DP_AUX_NATIVE_READ 0x9 47*490f5fd2SSimon Glass 48*490f5fd2SSimon Glass #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 49*490f5fd2SSimon Glass #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 50*490f5fd2SSimon Glass #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 51*490f5fd2SSimon Glass #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 52*490f5fd2SSimon Glass 53*490f5fd2SSimon Glass #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 54*490f5fd2SSimon Glass #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 55*490f5fd2SSimon Glass #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 56*490f5fd2SSimon Glass #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 57*490f5fd2SSimon Glass 58*490f5fd2SSimon Glass /* AUX CH addresses */ 59*490f5fd2SSimon Glass /* DPCD */ 60*490f5fd2SSimon Glass #define DP_DPCD_REV 0x000 61*490f5fd2SSimon Glass 62*490f5fd2SSimon Glass #define DP_MAX_LINK_RATE 0x001 63*490f5fd2SSimon Glass 64*490f5fd2SSimon Glass #define DP_MAX_LANE_COUNT 0x002 65*490f5fd2SSimon Glass # define DP_MAX_LANE_COUNT_MASK 0x1f 66*490f5fd2SSimon Glass # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 67*490f5fd2SSimon Glass # define DP_ENHANCED_FRAME_CAP (1 << 7) 68*490f5fd2SSimon Glass 69*490f5fd2SSimon Glass #define DP_MAX_DOWNSPREAD 0x003 70*490f5fd2SSimon Glass # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 71*490f5fd2SSimon Glass 72*490f5fd2SSimon Glass #define DP_NORP 0x004 73*490f5fd2SSimon Glass 74*490f5fd2SSimon Glass #define DP_DOWNSTREAMPORT_PRESENT 0x005 75*490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 76*490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 77*490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 78*490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 79*490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 80*490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 81*490f5fd2SSimon Glass # define DP_FORMAT_CONVERSION (1 << 3) 82*490f5fd2SSimon Glass # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 83*490f5fd2SSimon Glass 84*490f5fd2SSimon Glass #define DP_MAIN_LINK_CHANNEL_CODING 0x006 85*490f5fd2SSimon Glass 86*490f5fd2SSimon Glass #define DP_DOWN_STREAM_PORT_COUNT 0x007 87*490f5fd2SSimon Glass # define DP_PORT_COUNT_MASK 0x0f 88*490f5fd2SSimon Glass # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 89*490f5fd2SSimon Glass # define DP_OUI_SUPPORT (1 << 7) 90*490f5fd2SSimon Glass 91*490f5fd2SSimon Glass #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 92*490f5fd2SSimon Glass # define DP_I2C_SPEED_1K 0x01 93*490f5fd2SSimon Glass # define DP_I2C_SPEED_5K 0x02 94*490f5fd2SSimon Glass # define DP_I2C_SPEED_10K 0x04 95*490f5fd2SSimon Glass # define DP_I2C_SPEED_100K 0x08 96*490f5fd2SSimon Glass # define DP_I2C_SPEED_400K 0x10 97*490f5fd2SSimon Glass # define DP_I2C_SPEED_1M 0x20 98*490f5fd2SSimon Glass 99*490f5fd2SSimon Glass #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 100*490f5fd2SSimon Glass #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 101*490f5fd2SSimon Glass 102*490f5fd2SSimon Glass /* Multiple stream transport */ 103*490f5fd2SSimon Glass #define DP_FAUX_CAP 0x020 /* 1.2 */ 104*490f5fd2SSimon Glass # define DP_FAUX_CAP_1 (1 << 0) 105*490f5fd2SSimon Glass 106*490f5fd2SSimon Glass #define DP_MSTM_CAP 0x021 /* 1.2 */ 107*490f5fd2SSimon Glass # define DP_MST_CAP (1 << 0) 108*490f5fd2SSimon Glass 109*490f5fd2SSimon Glass #define DP_GUID 0x030 /* 1.2 */ 110*490f5fd2SSimon Glass 111*490f5fd2SSimon Glass #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 112*490f5fd2SSimon Glass # define DP_PSR_IS_SUPPORTED 1 113*490f5fd2SSimon Glass #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 114*490f5fd2SSimon Glass # define DP_PSR_NO_TRAIN_ON_EXIT 1 115*490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_330 (0 << 1) 116*490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_275 (1 << 1) 117*490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_220 (2 << 1) 118*490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_165 (3 << 1) 119*490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_110 (4 << 1) 120*490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_55 (5 << 1) 121*490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_0 (6 << 1) 122*490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_MASK (7 << 1) 123*490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_SHIFT 1 124*490f5fd2SSimon Glass 125*490f5fd2SSimon Glass /* 126*490f5fd2SSimon Glass * 0x80-0x8f describe downstream port capabilities, but there are two layouts 127*490f5fd2SSimon Glass * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 128*490f5fd2SSimon Glass * each port's descriptor is one byte wide. If it was set, each port's is 129*490f5fd2SSimon Glass * four bytes wide, starting with the one byte from the base info. As of 130*490f5fd2SSimon Glass * DP interop v1.1a only VGA defines additional detail. 131*490f5fd2SSimon Glass */ 132*490f5fd2SSimon Glass 133*490f5fd2SSimon Glass /* offset 0 */ 134*490f5fd2SSimon Glass #define DP_DOWNSTREAM_PORT_0 0x80 135*490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_MASK (7 << 0) 136*490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_DP 0 137*490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_VGA 1 138*490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_DVI 2 139*490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_HDMI 3 140*490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_NON_EDID 4 141*490f5fd2SSimon Glass # define DP_DS_PORT_HPD (1 << 3) 142*490f5fd2SSimon Glass /* offset 1 for VGA is maximum megapixels per second / 8 */ 143*490f5fd2SSimon Glass /* offset 2 */ 144*490f5fd2SSimon Glass # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) 145*490f5fd2SSimon Glass # define DP_DS_VGA_8BPC 0 146*490f5fd2SSimon Glass # define DP_DS_VGA_10BPC 1 147*490f5fd2SSimon Glass # define DP_DS_VGA_12BPC 2 148*490f5fd2SSimon Glass # define DP_DS_VGA_16BPC 3 149*490f5fd2SSimon Glass 150*490f5fd2SSimon Glass /* link configuration */ 151*490f5fd2SSimon Glass #define DP_LINK_BW_SET 0x100 152*490f5fd2SSimon Glass # define DP_LINK_BW_1_62 0x06 153*490f5fd2SSimon Glass # define DP_LINK_BW_2_7 0x0a 154*490f5fd2SSimon Glass # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 155*490f5fd2SSimon Glass 156*490f5fd2SSimon Glass #define DP_LANE_COUNT_SET 0x101 157*490f5fd2SSimon Glass # define DP_LANE_COUNT_MASK 0x0f 158*490f5fd2SSimon Glass # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 159*490f5fd2SSimon Glass 160*490f5fd2SSimon Glass #define DP_TRAINING_PATTERN_SET 0x102 161*490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_DISABLE 0 162*490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_1 1 163*490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_2 2 164*490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 165*490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_MASK 0x3 166*490f5fd2SSimon Glass 167*490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) 168*490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) 169*490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) 170*490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) 171*490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_MASK (3 << 2) 172*490f5fd2SSimon Glass 173*490f5fd2SSimon Glass # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 174*490f5fd2SSimon Glass # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 175*490f5fd2SSimon Glass 176*490f5fd2SSimon Glass # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 177*490f5fd2SSimon Glass # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 178*490f5fd2SSimon Glass # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 179*490f5fd2SSimon Glass # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 180*490f5fd2SSimon Glass 181*490f5fd2SSimon Glass #define DP_TRAINING_LANE0_SET 0x103 182*490f5fd2SSimon Glass #define DP_TRAINING_LANE1_SET 0x104 183*490f5fd2SSimon Glass #define DP_TRAINING_LANE2_SET 0x105 184*490f5fd2SSimon Glass #define DP_TRAINING_LANE3_SET 0x106 185*490f5fd2SSimon Glass 186*490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 187*490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 188*490f5fd2SSimon Glass # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 189*490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 190*490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 191*490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 192*490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 193*490f5fd2SSimon Glass 194*490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 195*490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 196*490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 197*490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 198*490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 199*490f5fd2SSimon Glass 200*490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 201*490f5fd2SSimon Glass # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 202*490f5fd2SSimon Glass 203*490f5fd2SSimon Glass #define DP_DOWNSPREAD_CTRL 0x107 204*490f5fd2SSimon Glass # define DP_SPREAD_AMP_0_5 (1 << 4) 205*490f5fd2SSimon Glass # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 206*490f5fd2SSimon Glass 207*490f5fd2SSimon Glass #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 208*490f5fd2SSimon Glass # define DP_SET_ANSI_8B10B (1 << 0) 209*490f5fd2SSimon Glass 210*490f5fd2SSimon Glass #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 211*490f5fd2SSimon Glass /* bitmask as for DP_I2C_SPEED_CAP */ 212*490f5fd2SSimon Glass 213*490f5fd2SSimon Glass #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 214*490f5fd2SSimon Glass 215*490f5fd2SSimon Glass #define DP_MSTM_CTRL 0x111 /* 1.2 */ 216*490f5fd2SSimon Glass # define DP_MST_EN (1 << 0) 217*490f5fd2SSimon Glass # define DP_UP_REQ_EN (1 << 1) 218*490f5fd2SSimon Glass # define DP_UPSTREAM_IS_SRC (1 << 2) 219*490f5fd2SSimon Glass 220*490f5fd2SSimon Glass #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 221*490f5fd2SSimon Glass # define DP_PSR_ENABLE (1 << 0) 222*490f5fd2SSimon Glass # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 223*490f5fd2SSimon Glass # define DP_PSR_CRC_VERIFICATION (1 << 2) 224*490f5fd2SSimon Glass # define DP_PSR_FRAME_CAPTURE (1 << 3) 225*490f5fd2SSimon Glass 226*490f5fd2SSimon Glass #define DP_ADAPTER_CTRL 0x1a0 227*490f5fd2SSimon Glass # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 228*490f5fd2SSimon Glass 229*490f5fd2SSimon Glass #define DP_BRANCH_DEVICE_CTRL 0x1a1 230*490f5fd2SSimon Glass # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 231*490f5fd2SSimon Glass 232*490f5fd2SSimon Glass #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 233*490f5fd2SSimon Glass #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 234*490f5fd2SSimon Glass #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 235*490f5fd2SSimon Glass 236*490f5fd2SSimon Glass #define DP_SINK_COUNT 0x200 237*490f5fd2SSimon Glass /* prior to 1.2 bit 7 was reserved mbz */ 238*490f5fd2SSimon Glass # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 239*490f5fd2SSimon Glass # define DP_SINK_CP_READY (1 << 6) 240*490f5fd2SSimon Glass 241*490f5fd2SSimon Glass #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 242*490f5fd2SSimon Glass # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 243*490f5fd2SSimon Glass # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 244*490f5fd2SSimon Glass # define DP_CP_IRQ (1 << 2) 245*490f5fd2SSimon Glass # define DP_MCCS_IRQ (1 << 3) 246*490f5fd2SSimon Glass # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 247*490f5fd2SSimon Glass # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 248*490f5fd2SSimon Glass # define DP_SINK_SPECIFIC_IRQ (1 << 6) 249*490f5fd2SSimon Glass 250*490f5fd2SSimon Glass #define DP_LANE0_1_STATUS 0x202 251*490f5fd2SSimon Glass #define DP_LANE2_3_STATUS 0x203 252*490f5fd2SSimon Glass # define DP_LANE_CR_DONE (1 << 0) 253*490f5fd2SSimon Glass # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 254*490f5fd2SSimon Glass # define DP_LANE_SYMBOL_LOCKED (1 << 2) 255*490f5fd2SSimon Glass 256*490f5fd2SSimon Glass #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 257*490f5fd2SSimon Glass DP_LANE_CHANNEL_EQ_DONE | \ 258*490f5fd2SSimon Glass DP_LANE_SYMBOL_LOCKED) 259*490f5fd2SSimon Glass 260*490f5fd2SSimon Glass #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 261*490f5fd2SSimon Glass 262*490f5fd2SSimon Glass #define DP_INTERLANE_ALIGN_DONE (1 << 0) 263*490f5fd2SSimon Glass #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 264*490f5fd2SSimon Glass #define DP_LINK_STATUS_UPDATED (1 << 7) 265*490f5fd2SSimon Glass 266*490f5fd2SSimon Glass #define DP_SINK_STATUS 0x205 267*490f5fd2SSimon Glass 268*490f5fd2SSimon Glass #define DP_RECEIVE_PORT_0_STATUS (1 << 0) 269*490f5fd2SSimon Glass #define DP_RECEIVE_PORT_1_STATUS (1 << 1) 270*490f5fd2SSimon Glass 271*490f5fd2SSimon Glass #define DP_ADJUST_REQUEST_LANE0_1 0x206 272*490f5fd2SSimon Glass #define DP_ADJUST_REQUEST_LANE2_3 0x207 273*490f5fd2SSimon Glass # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 274*490f5fd2SSimon Glass # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 275*490f5fd2SSimon Glass # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 276*490f5fd2SSimon Glass # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 277*490f5fd2SSimon Glass # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 278*490f5fd2SSimon Glass # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 279*490f5fd2SSimon Glass # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 280*490f5fd2SSimon Glass # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 281*490f5fd2SSimon Glass 282*490f5fd2SSimon Glass #define DP_TEST_REQUEST 0x218 283*490f5fd2SSimon Glass # define DP_TEST_LINK_TRAINING (1 << 0) 284*490f5fd2SSimon Glass # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 285*490f5fd2SSimon Glass # define DP_TEST_LINK_EDID_READ (1 << 2) 286*490f5fd2SSimon Glass # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 287*490f5fd2SSimon Glass # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 288*490f5fd2SSimon Glass 289*490f5fd2SSimon Glass #define DP_TEST_LINK_RATE 0x219 290*490f5fd2SSimon Glass # define DP_LINK_RATE_162 (0x6) 291*490f5fd2SSimon Glass # define DP_LINK_RATE_27 (0xa) 292*490f5fd2SSimon Glass 293*490f5fd2SSimon Glass #define DP_TEST_LANE_COUNT 0x220 294*490f5fd2SSimon Glass 295*490f5fd2SSimon Glass #define DP_TEST_PATTERN 0x221 296*490f5fd2SSimon Glass 297*490f5fd2SSimon Glass #define DP_TEST_CRC_R_CR 0x240 298*490f5fd2SSimon Glass #define DP_TEST_CRC_G_Y 0x242 299*490f5fd2SSimon Glass #define DP_TEST_CRC_B_CB 0x244 300*490f5fd2SSimon Glass 301*490f5fd2SSimon Glass #define DP_TEST_SINK_MISC 0x246 302*490f5fd2SSimon Glass #define DP_TEST_CRC_SUPPORTED (1 << 5) 303*490f5fd2SSimon Glass 304*490f5fd2SSimon Glass #define DP_TEST_RESPONSE 0x260 305*490f5fd2SSimon Glass # define DP_TEST_ACK (1 << 0) 306*490f5fd2SSimon Glass # define DP_TEST_NAK (1 << 1) 307*490f5fd2SSimon Glass # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 308*490f5fd2SSimon Glass 309*490f5fd2SSimon Glass #define DP_TEST_EDID_CHECKSUM 0x261 310*490f5fd2SSimon Glass 311*490f5fd2SSimon Glass #define DP_TEST_SINK 0x270 312*490f5fd2SSimon Glass #define DP_TEST_SINK_START (1 << 0) 313*490f5fd2SSimon Glass 314*490f5fd2SSimon Glass #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 315*490f5fd2SSimon Glass # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 316*490f5fd2SSimon Glass # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 317*490f5fd2SSimon Glass 318*490f5fd2SSimon Glass #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 319*490f5fd2SSimon Glass /* up to ID_SLOT_63 at 0x2ff */ 320*490f5fd2SSimon Glass 321*490f5fd2SSimon Glass #define DP_SOURCE_OUI 0x300 322*490f5fd2SSimon Glass #define DP_SINK_OUI 0x400 323*490f5fd2SSimon Glass #define DP_BRANCH_OUI 0x500 324*490f5fd2SSimon Glass 325*490f5fd2SSimon Glass #define DP_SET_POWER 0x600 326*490f5fd2SSimon Glass # define DP_SET_POWER_D0 0x1 327*490f5fd2SSimon Glass # define DP_SET_POWER_D3 0x2 328*490f5fd2SSimon Glass # define DP_SET_POWER_MASK 0x3 329*490f5fd2SSimon Glass 330*490f5fd2SSimon Glass #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 331*490f5fd2SSimon Glass #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 332*490f5fd2SSimon Glass #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 333*490f5fd2SSimon Glass #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 334*490f5fd2SSimon Glass 335*490f5fd2SSimon Glass #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ 336*490f5fd2SSimon Glass /* 0-5 sink count */ 337*490f5fd2SSimon Glass # define DP_SINK_COUNT_CP_READY (1 << 6) 338*490f5fd2SSimon Glass 339*490f5fd2SSimon Glass #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ 340*490f5fd2SSimon Glass 341*490f5fd2SSimon Glass #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 342*490f5fd2SSimon Glass 343*490f5fd2SSimon Glass #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 344*490f5fd2SSimon Glass 345*490f5fd2SSimon Glass #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 346*490f5fd2SSimon Glass # define DP_PSR_LINK_CRC_ERROR (1 << 0) 347*490f5fd2SSimon Glass # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 348*490f5fd2SSimon Glass 349*490f5fd2SSimon Glass #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 350*490f5fd2SSimon Glass # define DP_PSR_CAPS_CHANGE (1 << 0) 351*490f5fd2SSimon Glass 352*490f5fd2SSimon Glass #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 353*490f5fd2SSimon Glass # define DP_PSR_SINK_INACTIVE 0 354*490f5fd2SSimon Glass # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 355*490f5fd2SSimon Glass # define DP_PSR_SINK_ACTIVE_RFB 2 356*490f5fd2SSimon Glass # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 357*490f5fd2SSimon Glass # define DP_PSR_SINK_ACTIVE_RESYNC 4 358*490f5fd2SSimon Glass # define DP_PSR_SINK_INTERNAL_ERROR 7 359*490f5fd2SSimon Glass # define DP_PSR_SINK_STATE_MASK 0x07 360*490f5fd2SSimon Glass 361*490f5fd2SSimon Glass /* DP 1.2 Sideband message defines */ 362*490f5fd2SSimon Glass /* peer device type - DP 1.2a Table 2-92 */ 363*490f5fd2SSimon Glass #define DP_PEER_DEVICE_NONE 0x0 364*490f5fd2SSimon Glass #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 365*490f5fd2SSimon Glass #define DP_PEER_DEVICE_MST_BRANCHING 0x2 366*490f5fd2SSimon Glass #define DP_PEER_DEVICE_SST_SINK 0x3 367*490f5fd2SSimon Glass #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 368*490f5fd2SSimon Glass 369*490f5fd2SSimon Glass /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 370*490f5fd2SSimon Glass #define DP_LINK_ADDRESS 0x01 371*490f5fd2SSimon Glass #define DP_CONNECTION_STATUS_NOTIFY 0x02 372*490f5fd2SSimon Glass #define DP_ENUM_PATH_RESOURCES 0x10 373*490f5fd2SSimon Glass #define DP_ALLOCATE_PAYLOAD 0x11 374*490f5fd2SSimon Glass #define DP_QUERY_PAYLOAD 0x12 375*490f5fd2SSimon Glass #define DP_RESOURCE_STATUS_NOTIFY 0x13 376*490f5fd2SSimon Glass #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 377*490f5fd2SSimon Glass #define DP_REMOTE_DPCD_READ 0x20 378*490f5fd2SSimon Glass #define DP_REMOTE_DPCD_WRITE 0x21 379*490f5fd2SSimon Glass #define DP_REMOTE_I2C_READ 0x22 380*490f5fd2SSimon Glass #define DP_REMOTE_I2C_WRITE 0x23 381*490f5fd2SSimon Glass #define DP_POWER_UP_PHY 0x24 382*490f5fd2SSimon Glass #define DP_POWER_DOWN_PHY 0x25 383*490f5fd2SSimon Glass #define DP_SINK_EVENT_NOTIFY 0x30 384*490f5fd2SSimon Glass #define DP_QUERY_STREAM_ENC_STATUS 0x38 385*490f5fd2SSimon Glass 386*490f5fd2SSimon Glass /* DP 1.2 MST sideband nak reasons - table 2.84 */ 387*490f5fd2SSimon Glass #define DP_NAK_WRITE_FAILURE 0x01 388*490f5fd2SSimon Glass #define DP_NAK_INVALID_READ 0x02 389*490f5fd2SSimon Glass #define DP_NAK_CRC_FAILURE 0x03 390*490f5fd2SSimon Glass #define DP_NAK_BAD_PARAM 0x04 391*490f5fd2SSimon Glass #define DP_NAK_DEFER 0x05 392*490f5fd2SSimon Glass #define DP_NAK_LINK_FAILURE 0x06 393*490f5fd2SSimon Glass #define DP_NAK_NO_RESOURCES 0x07 394*490f5fd2SSimon Glass #define DP_NAK_DPCD_FAIL 0x08 395*490f5fd2SSimon Glass #define DP_NAK_I2C_NAK 0x09 396*490f5fd2SSimon Glass #define DP_NAK_ALLOCATE_FAIL 0x0a 397*490f5fd2SSimon Glass 398*490f5fd2SSimon Glass #define MODE_I2C_START 1 399*490f5fd2SSimon Glass #define MODE_I2C_WRITE 2 400*490f5fd2SSimon Glass #define MODE_I2C_READ 4 401*490f5fd2SSimon Glass #define MODE_I2C_STOP 8 402*490f5fd2SSimon Glass 403*490f5fd2SSimon Glass /* Rest of file omitted as it is not used in U-Boot */ 404*490f5fd2SSimon Glass 405*490f5fd2SSimon Glass #endif /* _DRM_DP_HELPER_H_ */ 406