1490f5fd2SSimon Glass /* 2490f5fd2SSimon Glass * Copyright © 2008 Keith Packard 3490f5fd2SSimon Glass * 4490f5fd2SSimon Glass * Permission to use, copy, modify, distribute, and sell this software and its 5490f5fd2SSimon Glass * documentation for any purpose is hereby granted without fee, provided that 6490f5fd2SSimon Glass * the above copyright notice appear in all copies and that both that copyright 7490f5fd2SSimon Glass * notice and this permission notice appear in supporting documentation, and 8490f5fd2SSimon Glass * that the name of the copyright holders not be used in advertising or 9490f5fd2SSimon Glass * publicity pertaining to distribution of the software without specific, 10490f5fd2SSimon Glass * written prior permission. The copyright holders make no representations 11490f5fd2SSimon Glass * about the suitability of this software for any purpose. It is provided "as 12490f5fd2SSimon Glass * is" without express or implied warranty. 13490f5fd2SSimon Glass * 14490f5fd2SSimon Glass * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15490f5fd2SSimon Glass * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16490f5fd2SSimon Glass * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17490f5fd2SSimon Glass * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18490f5fd2SSimon Glass * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19490f5fd2SSimon Glass * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20490f5fd2SSimon Glass * OF THIS SOFTWARE. 21490f5fd2SSimon Glass */ 22490f5fd2SSimon Glass 23490f5fd2SSimon Glass #ifndef _DRM_DP_HELPER_H_ 24490f5fd2SSimon Glass #define _DRM_DP_HELPER_H_ 25490f5fd2SSimon Glass 26490f5fd2SSimon Glass /* 27490f5fd2SSimon Glass * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 28490f5fd2SSimon Glass * DP and DPCD versions are independent. Differences from 1.0 are not noted, 29490f5fd2SSimon Glass * 1.0 devices basically don't exist in the wild. 30490f5fd2SSimon Glass * 31490f5fd2SSimon Glass * Abbreviations, in chronological order: 32490f5fd2SSimon Glass * 33490f5fd2SSimon Glass * eDP: Embedded DisplayPort version 1 34490f5fd2SSimon Glass * DPI: DisplayPort Interoperability Guideline v1.1a 35490f5fd2SSimon Glass * 1.2: DisplayPort 1.2 36490f5fd2SSimon Glass * MST: Multistream Transport - part of DP 1.2a 37490f5fd2SSimon Glass * 38490f5fd2SSimon Glass * 1.2 formally includes both eDP and DPI definitions. 39490f5fd2SSimon Glass */ 40490f5fd2SSimon Glass 41490f5fd2SSimon Glass #define DP_AUX_I2C_WRITE 0x0 42490f5fd2SSimon Glass #define DP_AUX_I2C_READ 0x1 43490f5fd2SSimon Glass #define DP_AUX_I2C_STATUS 0x2 44490f5fd2SSimon Glass #define DP_AUX_I2C_MOT 0x4 45490f5fd2SSimon Glass #define DP_AUX_NATIVE_WRITE 0x8 46490f5fd2SSimon Glass #define DP_AUX_NATIVE_READ 0x9 47490f5fd2SSimon Glass 48490f5fd2SSimon Glass #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 49490f5fd2SSimon Glass #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 50490f5fd2SSimon Glass #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 51490f5fd2SSimon Glass #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 52490f5fd2SSimon Glass 53490f5fd2SSimon Glass #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 54490f5fd2SSimon Glass #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 55490f5fd2SSimon Glass #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 56490f5fd2SSimon Glass #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 57490f5fd2SSimon Glass 58490f5fd2SSimon Glass /* AUX CH addresses */ 59490f5fd2SSimon Glass /* DPCD */ 60490f5fd2SSimon Glass #define DP_DPCD_REV 0x000 61490f5fd2SSimon Glass 62490f5fd2SSimon Glass #define DP_MAX_LINK_RATE 0x001 63490f5fd2SSimon Glass 64490f5fd2SSimon Glass #define DP_MAX_LANE_COUNT 0x002 65490f5fd2SSimon Glass # define DP_MAX_LANE_COUNT_MASK 0x1f 66490f5fd2SSimon Glass # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 67490f5fd2SSimon Glass # define DP_ENHANCED_FRAME_CAP (1 << 7) 68490f5fd2SSimon Glass 69490f5fd2SSimon Glass #define DP_MAX_DOWNSPREAD 0x003 70490f5fd2SSimon Glass # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 71490f5fd2SSimon Glass 72490f5fd2SSimon Glass #define DP_NORP 0x004 73490f5fd2SSimon Glass 74490f5fd2SSimon Glass #define DP_DOWNSTREAMPORT_PRESENT 0x005 75490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 76490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 77490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 78490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 79490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 80490f5fd2SSimon Glass # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 81490f5fd2SSimon Glass # define DP_FORMAT_CONVERSION (1 << 3) 82490f5fd2SSimon Glass # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 83490f5fd2SSimon Glass 84490f5fd2SSimon Glass #define DP_MAIN_LINK_CHANNEL_CODING 0x006 85490f5fd2SSimon Glass 86490f5fd2SSimon Glass #define DP_DOWN_STREAM_PORT_COUNT 0x007 87490f5fd2SSimon Glass # define DP_PORT_COUNT_MASK 0x0f 88490f5fd2SSimon Glass # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 89490f5fd2SSimon Glass # define DP_OUI_SUPPORT (1 << 7) 90490f5fd2SSimon Glass 91490f5fd2SSimon Glass #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 92490f5fd2SSimon Glass # define DP_I2C_SPEED_1K 0x01 93490f5fd2SSimon Glass # define DP_I2C_SPEED_5K 0x02 94490f5fd2SSimon Glass # define DP_I2C_SPEED_10K 0x04 95490f5fd2SSimon Glass # define DP_I2C_SPEED_100K 0x08 96490f5fd2SSimon Glass # define DP_I2C_SPEED_400K 0x10 97490f5fd2SSimon Glass # define DP_I2C_SPEED_1M 0x20 98490f5fd2SSimon Glass 99490f5fd2SSimon Glass #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 100490f5fd2SSimon Glass #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 101490f5fd2SSimon Glass 102490f5fd2SSimon Glass /* Multiple stream transport */ 103490f5fd2SSimon Glass #define DP_FAUX_CAP 0x020 /* 1.2 */ 104490f5fd2SSimon Glass # define DP_FAUX_CAP_1 (1 << 0) 105490f5fd2SSimon Glass 106490f5fd2SSimon Glass #define DP_MSTM_CAP 0x021 /* 1.2 */ 107490f5fd2SSimon Glass # define DP_MST_CAP (1 << 0) 108490f5fd2SSimon Glass 109490f5fd2SSimon Glass #define DP_GUID 0x030 /* 1.2 */ 110490f5fd2SSimon Glass 111490f5fd2SSimon Glass #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 112490f5fd2SSimon Glass # define DP_PSR_IS_SUPPORTED 1 113490f5fd2SSimon Glass #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 114490f5fd2SSimon Glass # define DP_PSR_NO_TRAIN_ON_EXIT 1 115490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_330 (0 << 1) 116490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_275 (1 << 1) 117490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_220 (2 << 1) 118490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_165 (3 << 1) 119490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_110 (4 << 1) 120490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_55 (5 << 1) 121490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_0 (6 << 1) 122490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_MASK (7 << 1) 123490f5fd2SSimon Glass # define DP_PSR_SETUP_TIME_SHIFT 1 124490f5fd2SSimon Glass 125490f5fd2SSimon Glass /* 126490f5fd2SSimon Glass * 0x80-0x8f describe downstream port capabilities, but there are two layouts 127490f5fd2SSimon Glass * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 128490f5fd2SSimon Glass * each port's descriptor is one byte wide. If it was set, each port's is 129490f5fd2SSimon Glass * four bytes wide, starting with the one byte from the base info. As of 130490f5fd2SSimon Glass * DP interop v1.1a only VGA defines additional detail. 131490f5fd2SSimon Glass */ 132490f5fd2SSimon Glass 133490f5fd2SSimon Glass /* offset 0 */ 134490f5fd2SSimon Glass #define DP_DOWNSTREAM_PORT_0 0x80 135490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_MASK (7 << 0) 136490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_DP 0 137490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_VGA 1 138490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_DVI 2 139490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_HDMI 3 140490f5fd2SSimon Glass # define DP_DS_PORT_TYPE_NON_EDID 4 141490f5fd2SSimon Glass # define DP_DS_PORT_HPD (1 << 3) 142490f5fd2SSimon Glass /* offset 1 for VGA is maximum megapixels per second / 8 */ 143490f5fd2SSimon Glass /* offset 2 */ 144490f5fd2SSimon Glass # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) 145490f5fd2SSimon Glass # define DP_DS_VGA_8BPC 0 146490f5fd2SSimon Glass # define DP_DS_VGA_10BPC 1 147490f5fd2SSimon Glass # define DP_DS_VGA_12BPC 2 148490f5fd2SSimon Glass # define DP_DS_VGA_16BPC 3 149490f5fd2SSimon Glass 150490f5fd2SSimon Glass /* link configuration */ 151490f5fd2SSimon Glass #define DP_LINK_BW_SET 0x100 152490f5fd2SSimon Glass # define DP_LINK_BW_1_62 0x06 153490f5fd2SSimon Glass # define DP_LINK_BW_2_7 0x0a 154490f5fd2SSimon Glass # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 155490f5fd2SSimon Glass 156490f5fd2SSimon Glass #define DP_LANE_COUNT_SET 0x101 157490f5fd2SSimon Glass # define DP_LANE_COUNT_MASK 0x0f 158490f5fd2SSimon Glass # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 159490f5fd2SSimon Glass 160490f5fd2SSimon Glass #define DP_TRAINING_PATTERN_SET 0x102 161490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_DISABLE 0 162490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_1 1 163490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_2 2 164490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 165490f5fd2SSimon Glass # define DP_TRAINING_PATTERN_MASK 0x3 166490f5fd2SSimon Glass 167490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) 168490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) 169490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) 170490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) 171490f5fd2SSimon Glass # define DP_LINK_QUAL_PATTERN_MASK (3 << 2) 172490f5fd2SSimon Glass 173490f5fd2SSimon Glass # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 174490f5fd2SSimon Glass # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 175490f5fd2SSimon Glass 176490f5fd2SSimon Glass # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 177490f5fd2SSimon Glass # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 178490f5fd2SSimon Glass # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 179490f5fd2SSimon Glass # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 180490f5fd2SSimon Glass 181490f5fd2SSimon Glass #define DP_TRAINING_LANE0_SET 0x103 182490f5fd2SSimon Glass #define DP_TRAINING_LANE1_SET 0x104 183490f5fd2SSimon Glass #define DP_TRAINING_LANE2_SET 0x105 184490f5fd2SSimon Glass #define DP_TRAINING_LANE3_SET 0x106 185490f5fd2SSimon Glass 186490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 187490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 188490f5fd2SSimon Glass # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 189490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 190490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 191490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 192490f5fd2SSimon Glass # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 193490f5fd2SSimon Glass 194490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 195490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 196490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 197490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 198490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 199490f5fd2SSimon Glass 200490f5fd2SSimon Glass # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 201490f5fd2SSimon Glass # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 202490f5fd2SSimon Glass 203490f5fd2SSimon Glass #define DP_DOWNSPREAD_CTRL 0x107 204490f5fd2SSimon Glass # define DP_SPREAD_AMP_0_5 (1 << 4) 205490f5fd2SSimon Glass # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 206490f5fd2SSimon Glass 207490f5fd2SSimon Glass #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 208490f5fd2SSimon Glass # define DP_SET_ANSI_8B10B (1 << 0) 209490f5fd2SSimon Glass 210490f5fd2SSimon Glass #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 211490f5fd2SSimon Glass /* bitmask as for DP_I2C_SPEED_CAP */ 212490f5fd2SSimon Glass 213490f5fd2SSimon Glass #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 214490f5fd2SSimon Glass 215490f5fd2SSimon Glass #define DP_MSTM_CTRL 0x111 /* 1.2 */ 216490f5fd2SSimon Glass # define DP_MST_EN (1 << 0) 217490f5fd2SSimon Glass # define DP_UP_REQ_EN (1 << 1) 218490f5fd2SSimon Glass # define DP_UPSTREAM_IS_SRC (1 << 2) 219490f5fd2SSimon Glass 220490f5fd2SSimon Glass #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 221490f5fd2SSimon Glass # define DP_PSR_ENABLE (1 << 0) 222490f5fd2SSimon Glass # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 223490f5fd2SSimon Glass # define DP_PSR_CRC_VERIFICATION (1 << 2) 224490f5fd2SSimon Glass # define DP_PSR_FRAME_CAPTURE (1 << 3) 225490f5fd2SSimon Glass 226490f5fd2SSimon Glass #define DP_ADAPTER_CTRL 0x1a0 227490f5fd2SSimon Glass # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 228490f5fd2SSimon Glass 229490f5fd2SSimon Glass #define DP_BRANCH_DEVICE_CTRL 0x1a1 230490f5fd2SSimon Glass # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 231490f5fd2SSimon Glass 232490f5fd2SSimon Glass #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 233490f5fd2SSimon Glass #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 234490f5fd2SSimon Glass #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 235490f5fd2SSimon Glass 236490f5fd2SSimon Glass #define DP_SINK_COUNT 0x200 237490f5fd2SSimon Glass /* prior to 1.2 bit 7 was reserved mbz */ 238490f5fd2SSimon Glass # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 239490f5fd2SSimon Glass # define DP_SINK_CP_READY (1 << 6) 240490f5fd2SSimon Glass 241490f5fd2SSimon Glass #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 242490f5fd2SSimon Glass # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 243490f5fd2SSimon Glass # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 244490f5fd2SSimon Glass # define DP_CP_IRQ (1 << 2) 245490f5fd2SSimon Glass # define DP_MCCS_IRQ (1 << 3) 246490f5fd2SSimon Glass # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 247490f5fd2SSimon Glass # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 248490f5fd2SSimon Glass # define DP_SINK_SPECIFIC_IRQ (1 << 6) 249490f5fd2SSimon Glass 250490f5fd2SSimon Glass #define DP_LANE0_1_STATUS 0x202 251490f5fd2SSimon Glass #define DP_LANE2_3_STATUS 0x203 252490f5fd2SSimon Glass # define DP_LANE_CR_DONE (1 << 0) 253490f5fd2SSimon Glass # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 254490f5fd2SSimon Glass # define DP_LANE_SYMBOL_LOCKED (1 << 2) 255490f5fd2SSimon Glass 256490f5fd2SSimon Glass #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 257490f5fd2SSimon Glass DP_LANE_CHANNEL_EQ_DONE | \ 258490f5fd2SSimon Glass DP_LANE_SYMBOL_LOCKED) 259490f5fd2SSimon Glass 260490f5fd2SSimon Glass #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 261490f5fd2SSimon Glass 262490f5fd2SSimon Glass #define DP_INTERLANE_ALIGN_DONE (1 << 0) 263490f5fd2SSimon Glass #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 264490f5fd2SSimon Glass #define DP_LINK_STATUS_UPDATED (1 << 7) 265490f5fd2SSimon Glass 266490f5fd2SSimon Glass #define DP_SINK_STATUS 0x205 267*dedc44b4SSimon Glass #define DP_SINK_STATUS_PORT0_IN_SYNC (1 << 0) 268490f5fd2SSimon Glass 269490f5fd2SSimon Glass #define DP_RECEIVE_PORT_0_STATUS (1 << 0) 270490f5fd2SSimon Glass #define DP_RECEIVE_PORT_1_STATUS (1 << 1) 271490f5fd2SSimon Glass 272490f5fd2SSimon Glass #define DP_ADJUST_REQUEST_LANE0_1 0x206 273490f5fd2SSimon Glass #define DP_ADJUST_REQUEST_LANE2_3 0x207 274490f5fd2SSimon Glass # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 275490f5fd2SSimon Glass # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 276490f5fd2SSimon Glass # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 277490f5fd2SSimon Glass # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 278490f5fd2SSimon Glass # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 279490f5fd2SSimon Glass # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 280490f5fd2SSimon Glass # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 281490f5fd2SSimon Glass # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 282490f5fd2SSimon Glass 283490f5fd2SSimon Glass #define DP_TEST_REQUEST 0x218 284490f5fd2SSimon Glass # define DP_TEST_LINK_TRAINING (1 << 0) 285490f5fd2SSimon Glass # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 286490f5fd2SSimon Glass # define DP_TEST_LINK_EDID_READ (1 << 2) 287490f5fd2SSimon Glass # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 288490f5fd2SSimon Glass # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 289490f5fd2SSimon Glass 290490f5fd2SSimon Glass #define DP_TEST_LINK_RATE 0x219 291490f5fd2SSimon Glass # define DP_LINK_RATE_162 (0x6) 292490f5fd2SSimon Glass # define DP_LINK_RATE_27 (0xa) 293490f5fd2SSimon Glass 294490f5fd2SSimon Glass #define DP_TEST_LANE_COUNT 0x220 295490f5fd2SSimon Glass 296490f5fd2SSimon Glass #define DP_TEST_PATTERN 0x221 297490f5fd2SSimon Glass 298490f5fd2SSimon Glass #define DP_TEST_CRC_R_CR 0x240 299490f5fd2SSimon Glass #define DP_TEST_CRC_G_Y 0x242 300490f5fd2SSimon Glass #define DP_TEST_CRC_B_CB 0x244 301490f5fd2SSimon Glass 302490f5fd2SSimon Glass #define DP_TEST_SINK_MISC 0x246 303490f5fd2SSimon Glass #define DP_TEST_CRC_SUPPORTED (1 << 5) 304490f5fd2SSimon Glass 305490f5fd2SSimon Glass #define DP_TEST_RESPONSE 0x260 306490f5fd2SSimon Glass # define DP_TEST_ACK (1 << 0) 307490f5fd2SSimon Glass # define DP_TEST_NAK (1 << 1) 308490f5fd2SSimon Glass # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 309490f5fd2SSimon Glass 310490f5fd2SSimon Glass #define DP_TEST_EDID_CHECKSUM 0x261 311490f5fd2SSimon Glass 312490f5fd2SSimon Glass #define DP_TEST_SINK 0x270 313490f5fd2SSimon Glass #define DP_TEST_SINK_START (1 << 0) 314490f5fd2SSimon Glass 315490f5fd2SSimon Glass #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 316490f5fd2SSimon Glass # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 317490f5fd2SSimon Glass # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 318490f5fd2SSimon Glass 319490f5fd2SSimon Glass #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 320490f5fd2SSimon Glass /* up to ID_SLOT_63 at 0x2ff */ 321490f5fd2SSimon Glass 322490f5fd2SSimon Glass #define DP_SOURCE_OUI 0x300 323490f5fd2SSimon Glass #define DP_SINK_OUI 0x400 324490f5fd2SSimon Glass #define DP_BRANCH_OUI 0x500 325490f5fd2SSimon Glass 326490f5fd2SSimon Glass #define DP_SET_POWER 0x600 327490f5fd2SSimon Glass # define DP_SET_POWER_D0 0x1 328490f5fd2SSimon Glass # define DP_SET_POWER_D3 0x2 329490f5fd2SSimon Glass # define DP_SET_POWER_MASK 0x3 330490f5fd2SSimon Glass 331490f5fd2SSimon Glass #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 332490f5fd2SSimon Glass #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 333490f5fd2SSimon Glass #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 334490f5fd2SSimon Glass #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 335490f5fd2SSimon Glass 336490f5fd2SSimon Glass #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ 337490f5fd2SSimon Glass /* 0-5 sink count */ 338490f5fd2SSimon Glass # define DP_SINK_COUNT_CP_READY (1 << 6) 339490f5fd2SSimon Glass 340490f5fd2SSimon Glass #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ 341490f5fd2SSimon Glass 342490f5fd2SSimon Glass #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 343490f5fd2SSimon Glass 344490f5fd2SSimon Glass #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 345490f5fd2SSimon Glass 346490f5fd2SSimon Glass #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 347490f5fd2SSimon Glass # define DP_PSR_LINK_CRC_ERROR (1 << 0) 348490f5fd2SSimon Glass # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 349490f5fd2SSimon Glass 350490f5fd2SSimon Glass #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 351490f5fd2SSimon Glass # define DP_PSR_CAPS_CHANGE (1 << 0) 352490f5fd2SSimon Glass 353490f5fd2SSimon Glass #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 354490f5fd2SSimon Glass # define DP_PSR_SINK_INACTIVE 0 355490f5fd2SSimon Glass # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 356490f5fd2SSimon Glass # define DP_PSR_SINK_ACTIVE_RFB 2 357490f5fd2SSimon Glass # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 358490f5fd2SSimon Glass # define DP_PSR_SINK_ACTIVE_RESYNC 4 359490f5fd2SSimon Glass # define DP_PSR_SINK_INTERNAL_ERROR 7 360490f5fd2SSimon Glass # define DP_PSR_SINK_STATE_MASK 0x07 361490f5fd2SSimon Glass 362490f5fd2SSimon Glass /* DP 1.2 Sideband message defines */ 363490f5fd2SSimon Glass /* peer device type - DP 1.2a Table 2-92 */ 364490f5fd2SSimon Glass #define DP_PEER_DEVICE_NONE 0x0 365490f5fd2SSimon Glass #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 366490f5fd2SSimon Glass #define DP_PEER_DEVICE_MST_BRANCHING 0x2 367490f5fd2SSimon Glass #define DP_PEER_DEVICE_SST_SINK 0x3 368490f5fd2SSimon Glass #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 369490f5fd2SSimon Glass 370490f5fd2SSimon Glass /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 371490f5fd2SSimon Glass #define DP_LINK_ADDRESS 0x01 372490f5fd2SSimon Glass #define DP_CONNECTION_STATUS_NOTIFY 0x02 373490f5fd2SSimon Glass #define DP_ENUM_PATH_RESOURCES 0x10 374490f5fd2SSimon Glass #define DP_ALLOCATE_PAYLOAD 0x11 375490f5fd2SSimon Glass #define DP_QUERY_PAYLOAD 0x12 376490f5fd2SSimon Glass #define DP_RESOURCE_STATUS_NOTIFY 0x13 377490f5fd2SSimon Glass #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 378490f5fd2SSimon Glass #define DP_REMOTE_DPCD_READ 0x20 379490f5fd2SSimon Glass #define DP_REMOTE_DPCD_WRITE 0x21 380490f5fd2SSimon Glass #define DP_REMOTE_I2C_READ 0x22 381490f5fd2SSimon Glass #define DP_REMOTE_I2C_WRITE 0x23 382490f5fd2SSimon Glass #define DP_POWER_UP_PHY 0x24 383490f5fd2SSimon Glass #define DP_POWER_DOWN_PHY 0x25 384490f5fd2SSimon Glass #define DP_SINK_EVENT_NOTIFY 0x30 385490f5fd2SSimon Glass #define DP_QUERY_STREAM_ENC_STATUS 0x38 386490f5fd2SSimon Glass 387490f5fd2SSimon Glass /* DP 1.2 MST sideband nak reasons - table 2.84 */ 388490f5fd2SSimon Glass #define DP_NAK_WRITE_FAILURE 0x01 389490f5fd2SSimon Glass #define DP_NAK_INVALID_READ 0x02 390490f5fd2SSimon Glass #define DP_NAK_CRC_FAILURE 0x03 391490f5fd2SSimon Glass #define DP_NAK_BAD_PARAM 0x04 392490f5fd2SSimon Glass #define DP_NAK_DEFER 0x05 393490f5fd2SSimon Glass #define DP_NAK_LINK_FAILURE 0x06 394490f5fd2SSimon Glass #define DP_NAK_NO_RESOURCES 0x07 395490f5fd2SSimon Glass #define DP_NAK_DPCD_FAIL 0x08 396490f5fd2SSimon Glass #define DP_NAK_I2C_NAK 0x09 397490f5fd2SSimon Glass #define DP_NAK_ALLOCATE_FAIL 0x0a 398490f5fd2SSimon Glass 399490f5fd2SSimon Glass #define MODE_I2C_START 1 400490f5fd2SSimon Glass #define MODE_I2C_WRITE 2 401490f5fd2SSimon Glass #define MODE_I2C_READ 4 402490f5fd2SSimon Glass #define MODE_I2C_STOP 8 403490f5fd2SSimon Glass 404490f5fd2SSimon Glass /* Rest of file omitted as it is not used in U-Boot */ 405490f5fd2SSimon Glass 406490f5fd2SSimon Glass #endif /* _DRM_DP_HELPER_H_ */ 407