1 /* 2 * MPC823 and PXA LCD Controller 3 * 4 * Modeled after video interface by Paolo Scaffardi 5 * 6 * 7 * (C) Copyright 2001 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef _LCD_H_ 14 #define _LCD_H_ 15 #include <lcd_console.h> 16 17 extern char lcd_is_enabled; 18 19 extern int lcd_line_length; 20 21 extern struct vidinfo panel_info; 22 23 void lcd_ctrl_init(void *lcdbase); 24 void lcd_enable(void); 25 26 /* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */ 27 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); 28 void lcd_initcolregs(void); 29 30 /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */ 31 struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, 32 void **alloc_addr); 33 int bmp_display(ulong addr, int x, int y); 34 35 /** 36 * Set whether we need to flush the dcache when changing the LCD image. This 37 * defaults to off. 38 * 39 * @param flush non-zero to flush cache after update, 0 to skip 40 */ 41 void lcd_set_flush_dcache(int flush); 42 43 #if defined CONFIG_MPC823 44 /* 45 * LCD controller stucture for MPC823 CPU 46 */ 47 typedef struct vidinfo { 48 ushort vl_col; /* Number of columns (i.e. 640) */ 49 ushort vl_row; /* Number of rows (i.e. 480) */ 50 ushort vl_width; /* Width of display area in millimeters */ 51 ushort vl_height; /* Height of display area in millimeters */ 52 53 /* LCD configuration register */ 54 u_char vl_clkp; /* Clock polarity */ 55 u_char vl_oep; /* Output Enable polarity */ 56 u_char vl_hsp; /* Horizontal Sync polarity */ 57 u_char vl_vsp; /* Vertical Sync polarity */ 58 u_char vl_dp; /* Data polarity */ 59 u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ 60 u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 61 u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ 62 u_char vl_clor; /* Color, 0 = mono, 1 = color */ 63 u_char vl_tft; /* 0 = passive, 1 = TFT */ 64 65 /* Horizontal control register. Timing from data sheet */ 66 ushort vl_wbl; /* Wait between lines */ 67 68 /* Vertical control register */ 69 u_char vl_vpw; /* Vertical sync pulse width */ 70 u_char vl_lcdac; /* LCD AC timing */ 71 u_char vl_wbf; /* Wait between frames */ 72 } vidinfo_t; 73 74 #elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ 75 defined CONFIG_CPU_MONAHANS 76 /* 77 * PXA LCD DMA descriptor 78 */ 79 struct pxafb_dma_descriptor { 80 u_long fdadr; /* Frame descriptor address register */ 81 u_long fsadr; /* Frame source address register */ 82 u_long fidr; /* Frame ID register */ 83 u_long ldcmd; /* Command register */ 84 }; 85 86 /* 87 * PXA LCD info 88 */ 89 struct pxafb_info { 90 91 /* Misc registers */ 92 u_long reg_lccr3; 93 u_long reg_lccr2; 94 u_long reg_lccr1; 95 u_long reg_lccr0; 96 u_long fdadr0; 97 u_long fdadr1; 98 99 /* DMA descriptors */ 100 struct pxafb_dma_descriptor * dmadesc_fblow; 101 struct pxafb_dma_descriptor * dmadesc_fbhigh; 102 struct pxafb_dma_descriptor * dmadesc_palette; 103 104 u_long screen; /* physical address of frame buffer */ 105 u_long palette; /* physical address of palette memory */ 106 u_int palette_size; 107 }; 108 109 /* 110 * LCD controller stucture for PXA CPU 111 */ 112 typedef struct vidinfo { 113 ushort vl_col; /* Number of columns (i.e. 640) */ 114 ushort vl_row; /* Number of rows (i.e. 480) */ 115 ushort vl_width; /* Width of display area in millimeters */ 116 ushort vl_height; /* Height of display area in millimeters */ 117 118 /* LCD configuration register */ 119 u_char vl_clkp; /* Clock polarity */ 120 u_char vl_oep; /* Output Enable polarity */ 121 u_char vl_hsp; /* Horizontal Sync polarity */ 122 u_char vl_vsp; /* Vertical Sync polarity */ 123 u_char vl_dp; /* Data polarity */ 124 u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 125 u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 126 u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ 127 u_char vl_clor; /* Color, 0 = mono, 1 = color */ 128 u_char vl_tft; /* 0 = passive, 1 = TFT */ 129 130 /* Horizontal control register. Timing from data sheet */ 131 ushort vl_hpw; /* Horz sync pulse width */ 132 u_char vl_blw; /* Wait before of line */ 133 u_char vl_elw; /* Wait end of line */ 134 135 /* Vertical control register. */ 136 u_char vl_vpw; /* Vertical sync pulse width */ 137 u_char vl_bfw; /* Wait before of frame */ 138 u_char vl_efw; /* Wait end of frame */ 139 140 /* PXA LCD controller params */ 141 struct pxafb_info pxa; 142 } vidinfo_t; 143 144 #elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) 145 146 typedef struct vidinfo { 147 ushort vl_col; /* Number of columns (i.e. 640) */ 148 ushort vl_row; /* Number of rows (i.e. 480) */ 149 u_long vl_clk; /* pixel clock in ps */ 150 151 /* LCD configuration register */ 152 u_long vl_sync; /* Horizontal / vertical sync */ 153 u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 154 u_long vl_tft; /* 0 = passive, 1 = TFT */ 155 u_long vl_cont_pol_low; /* contrast polarity is low */ 156 u_long vl_clk_pol; /* clock polarity */ 157 158 /* Horizontal control register. */ 159 u_long vl_hsync_len; /* Length of horizontal sync */ 160 u_long vl_left_margin; /* Time from sync to picture */ 161 u_long vl_right_margin; /* Time from picture to sync */ 162 163 /* Vertical control register. */ 164 u_long vl_vsync_len; /* Length of vertical sync */ 165 u_long vl_upper_margin; /* Time from sync to picture */ 166 u_long vl_lower_margin; /* Time from picture to sync */ 167 168 u_long mmio; /* Memory mapped registers */ 169 } vidinfo_t; 170 171 #elif defined(CONFIG_EXYNOS_FB) 172 173 enum { 174 FIMD_RGB_INTERFACE = 1, 175 FIMD_CPU_INTERFACE = 2, 176 }; 177 178 enum exynos_fb_rgb_mode_t { 179 MODE_RGB_P = 0, 180 MODE_BGR_P = 1, 181 MODE_RGB_S = 2, 182 MODE_BGR_S = 3, 183 }; 184 185 typedef struct vidinfo { 186 ushort vl_col; /* Number of columns (i.e. 640) */ 187 ushort vl_row; /* Number of rows (i.e. 480) */ 188 ushort vl_width; /* Width of display area in millimeters */ 189 ushort vl_height; /* Height of display area in millimeters */ 190 191 /* LCD configuration register */ 192 u_char vl_freq; /* Frequency */ 193 u_char vl_clkp; /* Clock polarity */ 194 u_char vl_oep; /* Output Enable polarity */ 195 u_char vl_hsp; /* Horizontal Sync polarity */ 196 u_char vl_vsp; /* Vertical Sync polarity */ 197 u_char vl_dp; /* Data polarity */ 198 u_char vl_bpix; /* Bits per pixel */ 199 200 /* Horizontal control register. Timing from data sheet */ 201 u_char vl_hspw; /* Horz sync pulse width */ 202 u_char vl_hfpd; /* Wait before of line */ 203 u_char vl_hbpd; /* Wait end of line */ 204 205 /* Vertical control register. */ 206 u_char vl_vspw; /* Vertical sync pulse width */ 207 u_char vl_vfpd; /* Wait before of frame */ 208 u_char vl_vbpd; /* Wait end of frame */ 209 u_char vl_cmd_allow_len; /* Wait end of frame */ 210 211 unsigned int win_id; 212 unsigned int init_delay; 213 unsigned int power_on_delay; 214 unsigned int reset_delay; 215 unsigned int interface_mode; 216 unsigned int mipi_enabled; 217 unsigned int dp_enabled; 218 unsigned int cs_setup; 219 unsigned int wr_setup; 220 unsigned int wr_act; 221 unsigned int wr_hold; 222 unsigned int logo_on; 223 unsigned int logo_width; 224 unsigned int logo_height; 225 int logo_x_offset; 226 int logo_y_offset; 227 unsigned long logo_addr; 228 unsigned int rgb_mode; 229 unsigned int resolution; 230 231 /* parent clock name(MPLL, EPLL or VPLL) */ 232 unsigned int pclk_name; 233 /* ratio value for source clock from parent clock. */ 234 unsigned int sclk_div; 235 236 unsigned int dual_lcd_enabled; 237 } vidinfo_t; 238 239 void init_panel_info(vidinfo_t *vid); 240 241 #else 242 243 typedef struct vidinfo { 244 ushort vl_col; /* Number of columns (i.e. 160) */ 245 ushort vl_row; /* Number of rows (i.e. 100) */ 246 247 u_char vl_bpix; /* Bits per pixel, 0 = 1 */ 248 249 ushort *cmap; /* Pointer to the colormap */ 250 251 void *priv; /* Pointer to driver-specific data */ 252 } vidinfo_t; 253 254 #endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */ 255 256 extern vidinfo_t panel_info; 257 258 /* Video functions */ 259 260 void lcd_putc(const char c); 261 void lcd_puts(const char *s); 262 void lcd_printf(const char *fmt, ...); 263 void lcd_clear(void); 264 int lcd_display_bitmap(ulong bmp_image, int x, int y); 265 266 /** 267 * Get the width of the LCD in pixels 268 * 269 * @return width of LCD in pixels 270 */ 271 int lcd_get_pixel_width(void); 272 273 /** 274 * Get the height of the LCD in pixels 275 * 276 * @return height of LCD in pixels 277 */ 278 int lcd_get_pixel_height(void); 279 280 /** 281 * Get the number of text lines/rows on the LCD 282 * 283 * @return number of rows 284 */ 285 int lcd_get_screen_rows(void); 286 287 /** 288 * Get the number of text columns on the LCD 289 * 290 * @return number of columns 291 */ 292 int lcd_get_screen_columns(void); 293 294 /** 295 * Get the background color of the LCD 296 * 297 * @return background color value 298 */ 299 int lcd_getbgcolor(void); 300 301 /** 302 * Get the foreground color of the LCD 303 * 304 * @return foreground color value 305 */ 306 int lcd_getfgcolor(void); 307 308 /** 309 * Set the position of the text cursor 310 * 311 * @param col Column to place cursor (0 = left side) 312 * @param row Row to place cursor (0 = top line) 313 */ 314 void lcd_position_cursor(unsigned col, unsigned row); 315 316 /* Allow boards to customize the information displayed */ 317 void lcd_show_board_info(void); 318 319 /* Return the size of the LCD frame buffer, and the line length */ 320 int lcd_get_size(int *line_length); 321 322 int lcd_dt_simplefb_add_node(void *blob); 323 int lcd_dt_simplefb_enable_existing_node(void *blob); 324 325 /* Update the LCD / flush the cache */ 326 void lcd_sync(void); 327 328 /************************************************************************/ 329 /* ** BITMAP DISPLAY SUPPORT */ 330 /************************************************************************/ 331 #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) 332 # include <bmp_layout.h> 333 # include <asm/byteorder.h> 334 #endif 335 336 /* 337 * Information about displays we are using. This is for configuring 338 * the LCD controller and memory allocation. Someone has to know what 339 * is connected, as we can't autodetect anything. 340 */ 341 #define CONFIG_SYS_HIGH 0 /* Pins are active high */ 342 #define CONFIG_SYS_LOW 1 /* Pins are active low */ 343 344 #define LCD_MONOCHROME 0 345 #define LCD_COLOR2 1 346 #define LCD_COLOR4 2 347 #define LCD_COLOR8 3 348 #define LCD_COLOR16 4 349 #define LCD_COLOR32 5 350 /*----------------------------------------------------------------------*/ 351 #if defined(CONFIG_LCD_INFO_BELOW_LOGO) 352 # define LCD_INFO_X 0 353 # define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) 354 #elif defined(CONFIG_LCD_LOGO) 355 # define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) 356 # define LCD_INFO_Y VIDEO_FONT_HEIGHT 357 #else 358 # define LCD_INFO_X VIDEO_FONT_WIDTH 359 # define LCD_INFO_Y VIDEO_FONT_HEIGHT 360 #endif 361 362 /* Default to 8bpp if bit depth not specified */ 363 #ifndef LCD_BPP 364 # define LCD_BPP LCD_COLOR8 365 #endif 366 #ifndef LCD_DF 367 # define LCD_DF 1 368 #endif 369 370 /* Calculate nr. of bits per pixel and nr. of colors */ 371 #define NBITS(bit_code) (1 << (bit_code)) 372 #define NCOLORS(bit_code) (1 << NBITS(bit_code)) 373 374 /************************************************************************/ 375 /* ** CONSOLE CONSTANTS */ 376 /************************************************************************/ 377 #if LCD_BPP == LCD_COLOR8 378 379 /* 380 * 8bpp color definitions 381 */ 382 # define CONSOLE_COLOR_BLACK 0 383 # define CONSOLE_COLOR_RED 1 384 # define CONSOLE_COLOR_GREEN 2 385 # define CONSOLE_COLOR_YELLOW 3 386 # define CONSOLE_COLOR_BLUE 4 387 # define CONSOLE_COLOR_MAGENTA 5 388 # define CONSOLE_COLOR_CYAN 6 389 # define CONSOLE_COLOR_GREY 14 390 # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ 391 392 #elif LCD_BPP == LCD_COLOR32 393 /* 394 * 32bpp color definitions 395 */ 396 # define CONSOLE_COLOR_RED 0x00ff0000 397 # define CONSOLE_COLOR_GREEN 0x0000ff00 398 # define CONSOLE_COLOR_YELLOW 0x00ffff00 399 # define CONSOLE_COLOR_BLUE 0x000000ff 400 # define CONSOLE_COLOR_MAGENTA 0x00ff00ff 401 # define CONSOLE_COLOR_CYAN 0x0000ffff 402 # define CONSOLE_COLOR_GREY 0x00aaaaaa 403 # define CONSOLE_COLOR_BLACK 0x00000000 404 # define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest*/ 405 # define NBYTES(bit_code) (NBITS(bit_code) >> 3) 406 407 #else 408 409 /* 410 * 16bpp color definitions 411 */ 412 # define CONSOLE_COLOR_BLACK 0x0000 413 # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ 414 415 #endif /* color definitions */ 416 417 /************************************************************************/ 418 #ifndef PAGE_SIZE 419 # define PAGE_SIZE 4096 420 #endif 421 422 /************************************************************************/ 423 424 #endif /* _LCD_H_ */ 425