xref: /openbmc/u-boot/include/lattice.h (revision 8167af14)
1 /*
2  * Porting to U-Boot:
3  *
4  * (C) Copyright 2010
5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
6  *
7  * Lattice's ispVME Embedded Tool to load Lattice's FPGA:
8  *
9  * Lattice Semiconductor Corp. Copyright 2009
10  *
11  * See file CREDITS for list of people who contributed to this
12  * project.
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License as
16  * published by the Free Software Foundation; either version 2 of
17  * the License, or (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27  * MA 02111-1307 USA
28  *
29  */
30 
31 #ifndef _VME_OPCODE_H
32 #define _VME_OPCODE_H
33 
34 #define VME_VERSION_NUMBER "12.1"
35 
36 /* Maximum declarations. */
37 
38 #define VMEHEXMAX	60000L	/* The hex file is split 60K per file. */
39 #define SCANMAX		64000L	/* The maximum SDR/SIR burst. */
40 
41 /*
42  *
43  * Supported JTAG state transitions.
44  *
45  */
46 
47 #define RESET		0x00
48 #define IDLE		0x01
49 #define IRPAUSE		0x02
50 #define DRPAUSE		0x03
51 #define SHIFTIR		0x04
52 #define SHIFTDR		0x05
53 /* 11/15/05 Nguyen changed to support DRCAPTURE*/
54 #define DRCAPTURE	0x06
55 
56 /*
57  * Flow control register bit definitions.  A set bit indicates
58  * that the register currently exhibits the corresponding mode.
59  */
60 
61 #define INTEL_PRGM	0x0001	/* Intelligent programming is in effect. */
62 #define CASCADE		0x0002	/* Currently splitting large SDR. */
63 #define REPEATLOOP	0x0008	/* Currently executing a repeat loop. */
64 #define SHIFTRIGHT	0x0080	/* The next data stream needs a right shift. */
65 #define SHIFTLEFT	0x0100	/* The next data stream needs a left shift. */
66 #define VERIFYUES	0x0200	/* Continue if fail is in effect. */
67 
68 /*
69  * DataType register bit definitions.  A set bit indicates
70  * that the register currently holds the corresponding type of data.
71  */
72 
73 #define EXPRESS		0x0001    /* Simultaneous program and verify. */
74 #define SIR_DATA	0x0002    /* SIR is the active SVF command. */
75 #define SDR_DATA	0x0004    /* SDR is the active SVF command. */
76 #define COMPRESS	0x0008    /* Data is compressed. */
77 #define TDI_DATA	0x0010    /* TDI data is present. */
78 #define TDO_DATA	0x0020    /* TDO data is present. */
79 #define MASK_DATA	0x0040    /* MASK data is present. */
80 #define HEAP_IN		0x0080    /* Data is from the heap. */
81 #define LHEAP_IN	0x0200    /* Data is from intel data buffer. */
82 #define VARIABLE	0x0400    /* Data is from a declared variable. */
83 #define CRC_DATA	0x0800	 /* CRC data is pressent. */
84 #define CMASK_DATA	0x1000    /* CMASK data is pressent. */
85 #define RMASK_DATA	0x2000	 /* RMASK data is pressent. */
86 #define READ_DATA	0x4000    /* READ data is pressent. */
87 #define DMASK_DATA	0x8000	 /* DMASK data is pressent. */
88 
89 /*
90  *
91  * Pin opcodes.
92  *
93  */
94 
95 #define signalENABLE	0x1C    /* ispENABLE pin. */
96 #define signalTMS	0x1D    /* TMS pin. */
97 #define signalTCK	0x1E    /* TCK pin. */
98 #define signalTDI	0x1F    /* TDI pin. */
99 #define signalTRST	0x20    /* TRST pin. */
100 
101 /*
102  *
103  * Supported vendors.
104  *
105  */
106 
107 #define VENDOR		0x56
108 #define LATTICE		0x01
109 #define ALTERA		0x02
110 #define XILINX		0x03
111 
112 /*
113  * Opcode definitions.
114  *
115  * Note: opcodes must be unique.
116  */
117 
118 #define ENDDATA		0x00	/* The end of the current SDR data stream. */
119 #define RUNTEST		0x01	/* The duration to stay at the stable state. */
120 #define ENDDR		0x02	/* The stable state after SDR. */
121 #define ENDIR		0x03	/* The stable state after SIR. */
122 #define ENDSTATE	0x04	/* The stable state after RUNTEST. */
123 #define TRST		0x05	/* Assert the TRST pin. */
124 #define HIR		0x06	/*
125 				 * The sum of the IR bits of the
126 				 * leading devices.
127 				 */
128 #define TIR		0x07	/*
129 				 * The sum of the IR bits of the trailing
130 				 * devices.
131 				 */
132 #define HDR		0x08	/* The number of leading devices. */
133 #define TDR		0x09	/* The number of trailing devices. */
134 #define ispEN		0x0A	/* Assert the ispEN pin. */
135 #define FREQUENCY	0x0B	/*
136 				 * The maximum clock rate to run the JTAG state
137 				 * machine.
138 				 */
139 #define STATE		0x10	/* Move to the next stable state. */
140 #define SIR		0x11	/* The instruction stream follows. */
141 #define SDR		0x12	/* The data stream follows. */
142 #define TDI		0x13	/* The following data stream feeds into
143 					the device. */
144 #define TDO		0x14	/*
145 				 * The following data stream is compared against
146 				 * the device.
147 				 */
148 #define MASK		0x15	/* The following data stream is used as mask. */
149 #define XSDR		0x16	/*
150 				 * The following data stream is for simultaneous
151 				 * program and verify.
152 				 */
153 #define XTDI		0x17	/* The following data stream is for shift in
154 				 * only. It must be stored for the next
155 				 * XSDR.
156 				 */
157 #define XTDO		0x18	/*
158 				 * There is not data stream.  The data stream
159 				 * was stored from the previous XTDI.
160 				 */
161 #define MEM		0x19	/*
162 				 * The maximum memory needed to allocate in
163 				 * order hold one row of data.
164 				 */
165 #define WAIT		0x1A	/* The duration of delay to observe. */
166 #define TCK		0x1B	/* The number of TCK pulses. */
167 #define SHR		0x23	/*
168 				 * Set the flow control register for
169 				 * right shift
170 				 */
171 #define SHL		0x24	/*
172 				 * Set the flow control register for left shift.
173 				 */
174 #define HEAP		0x32	/* The memory size needed to hold one loop. */
175 #define REPEAT		0x33	/* The beginning of the loop. */
176 #define LEFTPAREN	0x35	/* The beginning of data following the loop. */
177 #define VAR		0x55	/* Plac holder for loop data. */
178 #define SEC		0x1C	/*
179 				 * The delay time in seconds that must be
180 				 * observed.
181 				 */
182 #define SMASK		0x1D	/* The mask for TDI data. */
183 #define MAX_WAIT	0x1E	/* The absolute maximum wait time. */
184 #define ON		0x1F	/* Assert the targeted pin. */
185 #define OFF		0x20	/* Dis-assert the targeted pin. */
186 #define SETFLOW		0x30	/* Change the flow control register. */
187 #define RESETFLOW	0x31	/* Clear the flow control register. */
188 
189 #define CRC		0x47	/*
190 				 * The following data stream is used for CRC
191 				 * calculation.
192 				 */
193 #define CMASK		0x48	/*
194 				 * The following data stream is used as mask
195 				 * for CRC calculation.
196 				 */
197 #define RMASK		0x49	/*
198 				 * The following data stream is used as mask
199 				 * for read and save.
200 				 */
201 #define READ		0x50	/*
202 				 * The following data stream is used for read
203 				 * and save.
204 				 */
205 #define ENDLOOP		0x59	/* The end of the repeat loop. */
206 #define SECUREHEAP	0x60	/* Used to secure the HEAP opcode. */
207 #define VUES		0x61	/* Support continue if fail. */
208 #define DMASK		0x62	/*
209 				 * The following data stream is used for dynamic
210 				 * I/O.
211 				 */
212 #define COMMENT		0x63	/* Support SVF comments in the VME file. */
213 #define HEADER		0x64	/* Support header in VME file. */
214 #define FILE_CRC	0x65	/* Support crc-protected VME file. */
215 #define LCOUNT		0x66	/* Support intelligent programming. */
216 #define LDELAY		0x67	/* Support intelligent programming. */
217 #define LSDR		0x68	/* Support intelligent programming. */
218 #define LHEAP		0x69	/*
219 				 * Memory needed to hold intelligent data
220 				 * buffer
221 				 */
222 #define CONTINUE	0x70	/* Allow continuation. */
223 #define LVDS		0x71	/* Support LVDS. */
224 #define ENDVME		0x7F	/* End of the VME file. */
225 #define ENDFILE		0xFF	/* End of file. */
226 
227 /*
228  *
229  * ispVM Embedded Return Codes.
230  *
231  */
232 
233 #define VME_VERIFICATION_FAILURE	-1
234 #define VME_FILE_READ_FAILURE		-2
235 #define VME_VERSION_FAILURE		-3
236 #define VME_INVALID_FILE		-4
237 #define VME_ARGUMENT_FAILURE		-5
238 #define VME_CRC_FAILURE			-6
239 
240 #define g_ucPinTDI	0x01
241 #define g_ucPinTCK	0x02
242 #define g_ucPinTMS	0x04
243 #define g_ucPinENABLE	0x08
244 #define g_ucPinTRST	0x10
245 
246 /*
247  *
248  * Type definitions.
249  *
250  */
251 
252 /* Support LVDS */
253 typedef struct {
254 	unsigned short usPositiveIndex;
255 	unsigned short usNegativeIndex;
256 	unsigned char  ucUpdate;
257 } LVDSPair;
258 
259 typedef enum {
260 	min_lattice_iface_type,		/* insert all new types after this */
261 	lattice_jtag_mode,		/* jtag/tap  */
262 	max_lattice_iface_type		/* insert all new types before this */
263 } Lattice_iface;
264 
265 typedef enum {
266 	min_lattice_type,
267 	Lattice_XP2,			/* Lattice XP2 Family */
268 	max_lattice_type		/* insert all new types before this */
269 } Lattice_Family;
270 
271 typedef struct {
272 	Lattice_Family	family;	/* part type */
273 	Lattice_iface	iface;	/* interface type */
274 	size_t		size;	/* bytes of data part can accept */
275 	void		*iface_fns; /* interface function table */
276 	void		*base;	/* base interface address */
277 	int		cookie;	/* implementation specific cookie */
278 	char		*desc;	/* description string */
279 } Lattice_desc;			/* end, typedef Altera_desc */
280 
281 /* Lattice Model Type */
282 #define CONFIG_SYS_XP2		CONFIG_SYS_FPGA_DEV(0x1)
283 
284 /* Board specific implementation specific function types */
285 typedef void (*Lattice_jtag_init)(void);
286 typedef void (*Lattice_jtag_set_tdi)(int v);
287 typedef void (*Lattice_jtag_set_tms)(int v);
288 typedef void (*Lattice_jtag_set_tck)(int v);
289 typedef int (*Lattice_jtag_get_tdo)(void);
290 
291 typedef struct {
292 	Lattice_jtag_init	jtag_init;
293 	Lattice_jtag_set_tdi	jtag_set_tdi;
294 	Lattice_jtag_set_tms	jtag_set_tms;
295 	Lattice_jtag_set_tck	jtag_set_tck;
296 	Lattice_jtag_get_tdo	jtag_get_tdo;
297 } lattice_board_specific_func;
298 
299 void writePort(unsigned char pins, unsigned char value);
300 unsigned char readPort(void);
301 void sclock(void);
302 void ispVMDelay(unsigned short int a_usMicroSecondDelay);
303 void calibration(void);
304 
305 int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize);
306 int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize);
307 int lattice_info(Lattice_desc *desc);
308 
309 void ispVMStart(void);
310 void ispVMEnd(void);
311 extern void ispVMFreeMem(void);
312 signed char ispVMCode(void);
313 void ispVMDelay(unsigned short int a_usMicroSecondDelay);
314 void ispVMCalculateCRC32(unsigned char a_ucData);
315 unsigned char GetByte(void);
316 void writePort(unsigned char pins, unsigned char value);
317 unsigned char readPort(void);
318 void sclock(void);
319 #endif
320