1 /* 2 * (C) Copyright 2009 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _IMXIMAGE_H_ 9 #define _IMXIMAGE_H_ 10 11 #define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */ 12 #define MAX_PLUGIN_CODE_SIZE (64 * 1024) 13 #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */ 14 #define APP_CODE_BARKER 0xB1 15 #define DCD_BARKER 0xB17219E9 16 17 /* Specify the offset of the IVT in the IMX header as expected by BootROM */ 18 #define BOOTROM_IVT_HDR_OFFSET 0xC00 19 20 /* 21 * NOTE: This file must be kept in sync with arch/arm/include/asm/\ 22 * mach-imx/imximage.cfg because tools/imximage.c can not 23 * cross-include headers from arch/arm/ and vice-versa. 24 */ 25 #define CMD_DATA_STR "DATA" 26 27 /* Initial Vector Table Offset */ 28 #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF 29 #define FLASH_OFFSET_STANDARD 0x400 30 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD 31 #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD 32 #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD 33 #define FLASH_OFFSET_ONENAND 0x100 34 #define FLASH_OFFSET_NOR 0x1000 35 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD 36 #define FLASH_OFFSET_QSPI 0x1000 37 38 /* Initial Load Region Size */ 39 #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF 40 #define FLASH_LOADSIZE_STANDARD 0x1000 41 #define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD 42 #define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD 43 #define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD 44 #define FLASH_LOADSIZE_ONENAND 0x400 45 #define FLASH_LOADSIZE_NOR 0x0 /* entire image */ 46 #define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD 47 #define FLASH_LOADSIZE_QSPI 0x0 /* entire image */ 48 49 /* Command tags and parameters */ 50 #define IVT_HEADER_TAG 0xD1 51 #define IVT_VERSION 0x40 52 #define DCD_HEADER_TAG 0xD2 53 #define DCD_VERSION 0x40 54 #define DCD_WRITE_DATA_COMMAND_TAG 0xCC 55 #define DCD_WRITE_DATA_PARAM 0x4 56 #define DCD_WRITE_CLR_BIT_PARAM 0xC 57 #define DCD_WRITE_SET_BIT_PARAM 0x1C 58 #define DCD_CHECK_DATA_COMMAND_TAG 0xCF 59 #define DCD_CHECK_BITS_SET_PARAM 0x14 60 #define DCD_CHECK_BITS_CLR_PARAM 0x04 61 62 #ifndef __ASSEMBLY__ 63 enum imximage_cmd { 64 CMD_INVALID, 65 CMD_IMAGE_VERSION, 66 CMD_BOOT_FROM, 67 CMD_BOOT_OFFSET, 68 CMD_WRITE_DATA, 69 CMD_WRITE_CLR_BIT, 70 CMD_WRITE_SET_BIT, 71 CMD_CHECK_BITS_SET, 72 CMD_CHECK_BITS_CLR, 73 CMD_CSF, 74 CMD_PLUGIN, 75 }; 76 77 enum imximage_fld_types { 78 CFG_INVALID = -1, 79 CFG_COMMAND, 80 CFG_REG_SIZE, 81 CFG_REG_ADDRESS, 82 CFG_REG_VALUE 83 }; 84 85 enum imximage_version { 86 IMXIMAGE_VER_INVALID = -1, 87 IMXIMAGE_V1 = 1, 88 IMXIMAGE_V2 89 }; 90 91 typedef struct { 92 uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */ 93 uint32_t addr; /* Address to write to */ 94 uint32_t value; /* Data to write */ 95 } dcd_type_addr_data_t; 96 97 typedef struct { 98 uint32_t barker; /* Barker for sanity check */ 99 uint32_t length; /* Device configuration length (without preamble) */ 100 } dcd_preamble_t; 101 102 typedef struct { 103 dcd_preamble_t preamble; 104 dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1]; 105 } dcd_v1_t; 106 107 typedef struct { 108 uint32_t app_code_jump_vector; 109 uint32_t app_code_barker; 110 uint32_t app_code_csf; 111 uint32_t dcd_ptr_ptr; 112 uint32_t super_root_key; 113 uint32_t dcd_ptr; 114 uint32_t app_dest_ptr; 115 } flash_header_v1_t; 116 117 typedef struct { 118 uint32_t length; /* Length of data to be read from flash */ 119 } flash_cfg_parms_t; 120 121 typedef struct { 122 flash_header_v1_t fhdr; 123 dcd_v1_t dcd_table; 124 flash_cfg_parms_t ext_header; 125 } imx_header_v1_t; 126 127 typedef struct { 128 uint32_t addr; 129 uint32_t value; 130 } dcd_addr_data_t; 131 132 typedef struct { 133 uint8_t tag; 134 uint16_t length; 135 uint8_t version; 136 } __attribute__((packed)) ivt_header_t; 137 138 typedef struct { 139 uint8_t tag; 140 uint16_t length; 141 uint8_t param; 142 } __attribute__((packed)) write_dcd_command_t; 143 144 struct dcd_v2_cmd { 145 write_dcd_command_t write_dcd_command; 146 dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2]; 147 }; 148 149 typedef struct { 150 ivt_header_t header; 151 struct dcd_v2_cmd dcd_cmd; 152 uint32_t padding[1]; /* end up on an 8-byte boundary */ 153 } dcd_v2_t; 154 155 typedef struct { 156 uint32_t start; 157 uint32_t size; 158 uint32_t plugin; 159 } boot_data_t; 160 161 typedef struct { 162 ivt_header_t header; 163 uint32_t entry; 164 uint32_t reserved1; 165 uint32_t dcd_ptr; 166 uint32_t boot_data_ptr; 167 uint32_t self; 168 uint32_t csf; 169 uint32_t reserved2; 170 } flash_header_v2_t; 171 172 typedef struct { 173 flash_header_v2_t fhdr; 174 boot_data_t boot_data; 175 union { 176 dcd_v2_t dcd_table; 177 char plugin_code[MAX_PLUGIN_CODE_SIZE]; 178 } data; 179 } imx_header_v2_t; 180 181 /* The header must be aligned to 4k on MX53 for NAND boot */ 182 struct imx_header { 183 union { 184 imx_header_v1_t hdr_v1; 185 imx_header_v2_t hdr_v2; 186 } header; 187 }; 188 189 typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, 190 char *name, int lineno, 191 int fld, uint32_t value, 192 uint32_t off); 193 194 typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len, 195 int32_t cmd); 196 197 typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr, 198 uint32_t dcd_len, 199 char *name, int lineno); 200 201 typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len, 202 uint32_t entry_point, uint32_t flash_offset); 203 204 #endif /* __ASSEMBLY__ */ 205 #endif /* _IMXIMAGE_H_ */ 206