xref: /openbmc/u-boot/include/i2s.h (revision 35546f6f)
1 /*
2  * Copyright (C) 2012 Samsung Electronics
3  * R. Chandrasekar <rcsekar@samsung.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __I2S_H__
9 #define __I2S_H__
10 
11 /*
12  * DAI hardware audio formats.
13  *
14  * Describes the physical PCM data formating and clocking. Add new formats
15  * to the end.
16  */
17 #define SND_SOC_DAIFMT_I2S		1 /* I2S mode */
18 #define SND_SOC_DAIFMT_RIGHT_J		2 /* Right Justified mode */
19 #define SND_SOC_DAIFMT_LEFT_J		3 /* Left Justified mode */
20 #define SND_SOC_DAIFMT_DSP_A		4 /* L data MSB after FRM LRC */
21 #define SND_SOC_DAIFMT_DSP_B		5 /* L data MSB during FRM LRC */
22 #define SND_SOC_DAIFMT_AC97		6 /* AC97 */
23 #define SND_SOC_DAIFMT_PDM		7 /* Pulse density modulation */
24 
25 /* left and right justified also known as MSB and LSB respectively */
26 #define SND_SOC_DAIFMT_MSB		SND_SOC_DAIFMT_LEFT_J
27 #define SND_SOC_DAIFMT_LSB		SND_SOC_DAIFMT_RIGHT_J
28 
29 /*
30  * DAI hardware signal inversions.
31  *
32  * Specifies whether the DAI can also support inverted clocks for the specified
33  * format.
34  */
35 #define SND_SOC_DAIFMT_NB_NF	(1 << 8) /* normal bit clock + frame */
36 #define SND_SOC_DAIFMT_NB_IF	(2 << 8) /* normal BCLK + inv FRM */
37 #define SND_SOC_DAIFMT_IB_NF	(3 << 8) /* invert BCLK + nor FRM */
38 #define SND_SOC_DAIFMT_IB_IF	(4 << 8) /* invert BCLK + FRM */
39 
40 /*
41  * DAI hardware clock masters.
42  *
43  * This is wrt the codec, the inverse is true for the interface
44  * i.e. if the codec is clk and FRM master then the interface is
45  * clk and frame slave.
46  */
47 #define SND_SOC_DAIFMT_CBM_CFM	(1 << 12) /* codec clk & FRM master */
48 #define SND_SOC_DAIFMT_CBS_CFM	(2 << 12) /* codec clk slave & FRM master */
49 #define SND_SOC_DAIFMT_CBM_CFS	(3 << 12) /* codec clk master & frame slave */
50 #define SND_SOC_DAIFMT_CBS_CFS	(4 << 12) /* codec clk & FRM slave */
51 
52 #define SND_SOC_DAIFMT_FORMAT_MASK	0x000f
53 #define SND_SOC_DAIFMT_CLOCK_MASK	0x00f0
54 #define SND_SOC_DAIFMT_INV_MASK		0x0f00
55 #define SND_SOC_DAIFMT_MASTER_MASK	0xf000
56 
57 /*
58  * Master Clock Directions
59  */
60 #define SND_SOC_CLOCK_IN		0
61 #define SND_SOC_CLOCK_OUT		1
62 
63 /* I2S Tx Control */
64 #define I2S_TX_ON	1
65 #define I2S_TX_OFF	0
66 
67 #define FIFO_LENGTH	64
68 
69 /* I2s Registers */
70 struct i2s_reg {
71 	unsigned int con;	/* base + 0 , Control register */
72 	unsigned int mod;	/* Mode register */
73 	unsigned int fic;	/* FIFO control register */
74 	unsigned int psr;	/* Reserved */
75 	unsigned int txd;	/* Transmit data register */
76 	unsigned int rxd;	/* Receive Data Register */
77 };
78 
79 /* This structure stores the i2s related information */
80 struct i2stx_info {
81 	unsigned int rfs;		/* LR clock frame size */
82 	unsigned int bfs;		/* Bit slock frame size */
83 	unsigned int audio_pll_clk;	/* Audio pll frequency in Hz */
84 	unsigned int samplingrate;	/* sampling rate */
85 	unsigned int bitspersample;	/* bits per sample */
86 	unsigned int channels;		/* audio channels */
87 	unsigned int base_address;	/* I2S Register Base */
88 	unsigned int id;		/* I2S controller id */
89 };
90 
91 /*
92  * Sends the given data through i2s tx
93  *
94  * @param pi2s_tx	pointer of i2s transmitter parameter structure.
95  * @param data		address of the data buffer
96  * @param data_size	array size of the int buffer (total size / size of int)
97  *
98  * @return		int value 0 for success, -1 in case of error
99  */
100 int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data,
101 				unsigned long data_size);
102 
103 /*
104  * Initialise i2s transmiter
105  *
106  * @param pi2s_tx	pointer of i2s transmitter parameter structure.
107  *
108  * @return		int value 0 for success, -1 in case of error
109  */
110 int i2s_tx_init(struct i2stx_info *pi2s_tx);
111 
112 #endif /* __I2S_H__ */
113