1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. 4 * All rights reserved. 5 * Authors: Carsten Langgaard <carstenl@mips.com> 6 * Maciej W. Rozycki <macro@mips.com> 7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 8 */ 9 #ifndef _ASM_GT64120_H 10 #define _ASM_GT64120_H 11 12 #define MSK(n) ((1 << (n)) - 1) 13 14 /* 15 * Register offset addresses 16 */ 17 /* CPU Configuration. */ 18 #define GT_CPU_OFS 0x000 19 20 #define GT_MULTI_OFS 0x120 21 22 /* CPU Address Decode. */ 23 #define GT_SCS10LD_OFS 0x008 24 #define GT_SCS10HD_OFS 0x010 25 #define GT_SCS32LD_OFS 0x018 26 #define GT_SCS32HD_OFS 0x020 27 #define GT_CS20LD_OFS 0x028 28 #define GT_CS20HD_OFS 0x030 29 #define GT_CS3BOOTLD_OFS 0x038 30 #define GT_CS3BOOTHD_OFS 0x040 31 #define GT_PCI0IOLD_OFS 0x048 32 #define GT_PCI0IOHD_OFS 0x050 33 #define GT_PCI0M0LD_OFS 0x058 34 #define GT_PCI0M0HD_OFS 0x060 35 #define GT_ISD_OFS 0x068 36 37 #define GT_PCI0M1LD_OFS 0x080 38 #define GT_PCI0M1HD_OFS 0x088 39 #define GT_PCI1IOLD_OFS 0x090 40 #define GT_PCI1IOHD_OFS 0x098 41 #define GT_PCI1M0LD_OFS 0x0a0 42 #define GT_PCI1M0HD_OFS 0x0a8 43 #define GT_PCI1M1LD_OFS 0x0b0 44 #define GT_PCI1M1HD_OFS 0x0b8 45 #define GT_PCI1M1LD_OFS 0x0b0 46 #define GT_PCI1M1HD_OFS 0x0b8 47 48 #define GT_SCS10AR_OFS 0x0d0 49 #define GT_SCS32AR_OFS 0x0d8 50 #define GT_CS20R_OFS 0x0e0 51 #define GT_CS3BOOTR_OFS 0x0e8 52 53 #define GT_PCI0IOREMAP_OFS 0x0f0 54 #define GT_PCI0M0REMAP_OFS 0x0f8 55 #define GT_PCI0M1REMAP_OFS 0x100 56 #define GT_PCI1IOREMAP_OFS 0x108 57 #define GT_PCI1M0REMAP_OFS 0x110 58 #define GT_PCI1M1REMAP_OFS 0x118 59 60 /* CPU Error Report. */ 61 #define GT_CPUERR_ADDRLO_OFS 0x070 62 #define GT_CPUERR_ADDRHI_OFS 0x078 63 64 #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */ 65 #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */ 66 #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */ 67 68 /* CPU Sync Barrier. */ 69 #define GT_PCI0SYNC_OFS 0x0c0 70 #define GT_PCI1SYNC_OFS 0x0c8 71 72 /* SDRAM and Device Address Decode. */ 73 #define GT_SCS0LD_OFS 0x400 74 #define GT_SCS0HD_OFS 0x404 75 #define GT_SCS1LD_OFS 0x408 76 #define GT_SCS1HD_OFS 0x40c 77 #define GT_SCS2LD_OFS 0x410 78 #define GT_SCS2HD_OFS 0x414 79 #define GT_SCS3LD_OFS 0x418 80 #define GT_SCS3HD_OFS 0x41c 81 #define GT_CS0LD_OFS 0x420 82 #define GT_CS0HD_OFS 0x424 83 #define GT_CS1LD_OFS 0x428 84 #define GT_CS1HD_OFS 0x42c 85 #define GT_CS2LD_OFS 0x430 86 #define GT_CS2HD_OFS 0x434 87 #define GT_CS3LD_OFS 0x438 88 #define GT_CS3HD_OFS 0x43c 89 #define GT_BOOTLD_OFS 0x440 90 #define GT_BOOTHD_OFS 0x444 91 92 #define GT_ADERR_OFS 0x470 93 94 /* SDRAM Configuration. */ 95 #define GT_SDRAM_CFG_OFS 0x448 96 97 #define GT_SDRAM_OPMODE_OFS 0x474 98 #define GT_SDRAM_BM_OFS 0x478 99 #define GT_SDRAM_ADDRDECODE_OFS 0x47c 100 101 /* SDRAM Parameters. */ 102 #define GT_SDRAM_B0_OFS 0x44c 103 #define GT_SDRAM_B1_OFS 0x450 104 #define GT_SDRAM_B2_OFS 0x454 105 #define GT_SDRAM_B3_OFS 0x458 106 107 /* Device Parameters. */ 108 #define GT_DEV_B0_OFS 0x45c 109 #define GT_DEV_B1_OFS 0x460 110 #define GT_DEV_B2_OFS 0x464 111 #define GT_DEV_B3_OFS 0x468 112 #define GT_DEV_BOOT_OFS 0x46c 113 114 /* ECC. */ 115 #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ 116 #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ 117 #define GT_ECC_MEM 0x488 /* GT-64120A only */ 118 #define GT_ECC_CALC 0x48c /* GT-64120A only */ 119 #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ 120 121 /* DMA Record. */ 122 #define GT_DMA0_CNT_OFS 0x800 123 #define GT_DMA1_CNT_OFS 0x804 124 #define GT_DMA2_CNT_OFS 0x808 125 #define GT_DMA3_CNT_OFS 0x80c 126 #define GT_DMA0_SA_OFS 0x810 127 #define GT_DMA1_SA_OFS 0x814 128 #define GT_DMA2_SA_OFS 0x818 129 #define GT_DMA3_SA_OFS 0x81c 130 #define GT_DMA0_DA_OFS 0x820 131 #define GT_DMA1_DA_OFS 0x824 132 #define GT_DMA2_DA_OFS 0x828 133 #define GT_DMA3_DA_OFS 0x82c 134 #define GT_DMA0_NEXT_OFS 0x830 135 #define GT_DMA1_NEXT_OFS 0x834 136 #define GT_DMA2_NEXT_OFS 0x838 137 #define GT_DMA3_NEXT_OFS 0x83c 138 139 #define GT_DMA0_CUR_OFS 0x870 140 #define GT_DMA1_CUR_OFS 0x874 141 #define GT_DMA2_CUR_OFS 0x878 142 #define GT_DMA3_CUR_OFS 0x87c 143 144 /* DMA Channel Control. */ 145 #define GT_DMA0_CTRL_OFS 0x840 146 #define GT_DMA1_CTRL_OFS 0x844 147 #define GT_DMA2_CTRL_OFS 0x848 148 #define GT_DMA3_CTRL_OFS 0x84c 149 150 /* DMA Arbiter. */ 151 #define GT_DMA_ARB_OFS 0x860 152 153 /* Timer/Counter. */ 154 #define GT_TC0_OFS 0x850 155 #define GT_TC1_OFS 0x854 156 #define GT_TC2_OFS 0x858 157 #define GT_TC3_OFS 0x85c 158 159 #define GT_TC_CONTROL_OFS 0x864 160 161 /* PCI Internal. */ 162 #define GT_PCI0_CMD_OFS 0xc00 163 #define GT_PCI0_TOR_OFS 0xc04 164 #define GT_PCI0_BS_SCS10_OFS 0xc08 165 #define GT_PCI0_BS_SCS32_OFS 0xc0c 166 #define GT_PCI0_BS_CS20_OFS 0xc10 167 #define GT_PCI0_BS_CS3BT_OFS 0xc14 168 169 #define GT_PCI1_IACK_OFS 0xc30 170 #define GT_PCI0_IACK_OFS 0xc34 171 172 #define GT_PCI0_BARE_OFS 0xc3c 173 #define GT_PCI0_PREFMBR_OFS 0xc40 174 175 #define GT_PCI0_SCS10_BAR_OFS 0xc48 176 #define GT_PCI0_SCS32_BAR_OFS 0xc4c 177 #define GT_PCI0_CS20_BAR_OFS 0xc50 178 #define GT_PCI0_CS3BT_BAR_OFS 0xc54 179 #define GT_PCI0_SSCS10_BAR_OFS 0xc58 180 #define GT_PCI0_SSCS32_BAR_OFS 0xc5c 181 182 #define GT_PCI0_SCS3BT_BAR_OFS 0xc64 183 184 #define GT_PCI1_CMD_OFS 0xc80 185 #define GT_PCI1_TOR_OFS 0xc84 186 #define GT_PCI1_BS_SCS10_OFS 0xc88 187 #define GT_PCI1_BS_SCS32_OFS 0xc8c 188 #define GT_PCI1_BS_CS20_OFS 0xc90 189 #define GT_PCI1_BS_CS3BT_OFS 0xc94 190 191 #define GT_PCI1_BARE_OFS 0xcbc 192 #define GT_PCI1_PREFMBR_OFS 0xcc0 193 194 #define GT_PCI1_SCS10_BAR_OFS 0xcc8 195 #define GT_PCI1_SCS32_BAR_OFS 0xccc 196 #define GT_PCI1_CS20_BAR_OFS 0xcd0 197 #define GT_PCI1_CS3BT_BAR_OFS 0xcd4 198 #define GT_PCI1_SSCS10_BAR_OFS 0xcd8 199 #define GT_PCI1_SSCS32_BAR_OFS 0xcdc 200 201 #define GT_PCI1_SCS3BT_BAR_OFS 0xce4 202 203 #define GT_PCI1_CFGADDR_OFS 0xcf0 204 #define GT_PCI1_CFGDATA_OFS 0xcf4 205 #define GT_PCI0_CFGADDR_OFS 0xcf8 206 #define GT_PCI0_CFGDATA_OFS 0xcfc 207 208 /* Interrupts. */ 209 #define GT_INTRCAUSE_OFS 0xc18 210 #define GT_INTRMASK_OFS 0xc1c 211 212 #define GT_PCI0_ICMASK_OFS 0xc24 213 #define GT_PCI0_SERR0MASK_OFS 0xc28 214 215 #define GT_CPU_INTSEL_OFS 0xc70 216 #define GT_PCI0_INTSEL_OFS 0xc74 217 218 #define GT_HINTRCAUSE_OFS 0xc98 219 #define GT_HINTRMASK_OFS 0xc9c 220 221 #define GT_PCI0_HICMASK_OFS 0xca4 222 #define GT_PCI1_SERR1MASK_OFS 0xca8 223 224 225 /* 226 * I2O Support Registers 227 */ 228 #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 229 #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 230 #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 231 #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c 232 #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 233 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 234 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 235 #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c 236 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 237 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 238 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 239 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 240 #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 241 #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 242 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 243 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 244 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 245 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c 246 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 247 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 248 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 249 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c 250 251 #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 252 #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 253 #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 254 #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c 255 #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 256 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 257 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 258 #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c 259 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 260 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 261 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 262 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 263 #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 264 #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 265 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 266 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 267 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 268 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c 269 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 270 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 271 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 272 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c 273 274 /* 275 * Register encodings 276 */ 277 #define GT_CPU_ENDIAN_SHF 12 278 #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) 279 #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK 280 #define GT_CPU_WR_SHF 16 281 #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) 282 #define GT_CPU_WR_BIT GT_CPU_WR_MSK 283 #define GT_CPU_WR_DXDXDXDX 0 284 #define GT_CPU_WR_DDDD 1 285 286 287 #define GT_PCI_DCRM_SHF 21 288 #define GT_PCI_LD_SHF 0 289 #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) 290 #define GT_PCI_HD_SHF 0 291 #define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) 292 #define GT_PCI_REMAP_SHF 0 293 #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) 294 295 296 #define GT_CFGADDR_CFGEN_SHF 31 297 #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) 298 #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK 299 300 #define GT_CFGADDR_BUSNUM_SHF 16 301 #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) 302 303 #define GT_CFGADDR_DEVNUM_SHF 11 304 #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) 305 306 #define GT_CFGADDR_FUNCNUM_SHF 8 307 #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) 308 309 #define GT_CFGADDR_REGNUM_SHF 2 310 #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) 311 312 313 #define GT_SDRAM_BM_ORDER_SHF 2 314 #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) 315 #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK 316 #define GT_SDRAM_BM_ORDER_SUB 1 317 #define GT_SDRAM_BM_ORDER_LIN 0 318 319 #define GT_SDRAM_BM_RSVD_ALL1 0xffb 320 321 322 #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 323 #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) 324 #define GT_SDRAM_ADDRDECODE_ADDR_0 0 325 #define GT_SDRAM_ADDRDECODE_ADDR_1 1 326 #define GT_SDRAM_ADDRDECODE_ADDR_2 2 327 #define GT_SDRAM_ADDRDECODE_ADDR_3 3 328 #define GT_SDRAM_ADDRDECODE_ADDR_4 4 329 #define GT_SDRAM_ADDRDECODE_ADDR_5 5 330 #define GT_SDRAM_ADDRDECODE_ADDR_6 6 331 #define GT_SDRAM_ADDRDECODE_ADDR_7 7 332 333 334 #define GT_SDRAM_B0_CASLAT_SHF 0 335 #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) 336 #define GT_SDRAM_B0_CASLAT_2 1 337 #define GT_SDRAM_B0_CASLAT_3 2 338 339 #define GT_SDRAM_B0_FTDIS_SHF 2 340 #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) 341 #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK 342 343 #define GT_SDRAM_B0_SRASPRCHG_SHF 3 344 #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) 345 #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK 346 #define GT_SDRAM_B0_SRASPRCHG_2 0 347 #define GT_SDRAM_B0_SRASPRCHG_3 1 348 349 #define GT_SDRAM_B0_B0COMPAB_SHF 4 350 #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) 351 #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK 352 353 #define GT_SDRAM_B0_64BITINT_SHF 5 354 #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) 355 #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK 356 #define GT_SDRAM_B0_64BITINT_2 0 357 #define GT_SDRAM_B0_64BITINT_4 1 358 359 #define GT_SDRAM_B0_BW_SHF 6 360 #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) 361 #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK 362 #define GT_SDRAM_B0_BW_32 0 363 #define GT_SDRAM_B0_BW_64 1 364 365 #define GT_SDRAM_B0_BLODD_SHF 7 366 #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) 367 #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK 368 369 #define GT_SDRAM_B0_PAR_SHF 8 370 #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) 371 #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK 372 373 #define GT_SDRAM_B0_BYPASS_SHF 9 374 #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) 375 #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK 376 377 #define GT_SDRAM_B0_SRAS2SCAS_SHF 10 378 #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) 379 #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK 380 #define GT_SDRAM_B0_SRAS2SCAS_2 0 381 #define GT_SDRAM_B0_SRAS2SCAS_3 1 382 383 #define GT_SDRAM_B0_SIZE_SHF 11 384 #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) 385 #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK 386 #define GT_SDRAM_B0_SIZE_16M 0 387 #define GT_SDRAM_B0_SIZE_64M 1 388 389 #define GT_SDRAM_B0_EXTPAR_SHF 12 390 #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) 391 #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK 392 393 #define GT_SDRAM_B0_BLEN_SHF 13 394 #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) 395 #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK 396 #define GT_SDRAM_B0_BLEN_8 0 397 #define GT_SDRAM_B0_BLEN_4 1 398 399 400 #define GT_SDRAM_CFG_REFINT_SHF 0 401 #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) 402 403 #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 404 #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) 405 #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK 406 407 #define GT_SDRAM_CFG_RMW_SHF 15 408 #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) 409 #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK 410 411 #define GT_SDRAM_CFG_NONSTAGREF_SHF 16 412 #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) 413 #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK 414 415 #define GT_SDRAM_CFG_DUPCNTL_SHF 19 416 #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) 417 #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK 418 419 #define GT_SDRAM_CFG_DUPBA_SHF 20 420 #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) 421 #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK 422 423 #define GT_SDRAM_CFG_DUPEOT0_SHF 21 424 #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) 425 #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK 426 427 #define GT_SDRAM_CFG_DUPEOT1_SHF 22 428 #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) 429 #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK 430 431 #define GT_SDRAM_OPMODE_OP_SHF 0 432 #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) 433 #define GT_SDRAM_OPMODE_OP_NORMAL 0 434 #define GT_SDRAM_OPMODE_OP_NOP 1 435 #define GT_SDRAM_OPMODE_OP_PRCHG 2 436 #define GT_SDRAM_OPMODE_OP_MODE 3 437 #define GT_SDRAM_OPMODE_OP_CBR 4 438 439 #define GT_TC_CONTROL_ENTC0_SHF 0 440 #define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF) 441 #define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK 442 #define GT_TC_CONTROL_SELTC0_SHF 1 443 #define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF) 444 #define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK 445 446 447 #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 448 #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK \ 449 (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) 450 #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK 451 452 #define GT_PCI0_BARE_SWSCS32DIS_SHF 1 453 #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) 454 #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK 455 456 #define GT_PCI0_BARE_SWSCS10DIS_SHF 2 457 #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) 458 #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK 459 460 #define GT_PCI0_BARE_INTIODIS_SHF 3 461 #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) 462 #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK 463 464 #define GT_PCI0_BARE_INTMEMDIS_SHF 4 465 #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) 466 #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK 467 468 #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 469 #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) 470 #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK 471 472 #define GT_PCI0_BARE_CS20DIS_SHF 6 473 #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) 474 #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK 475 476 #define GT_PCI0_BARE_SCS32DIS_SHF 7 477 #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) 478 #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK 479 480 #define GT_PCI0_BARE_SCS10DIS_SHF 8 481 #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) 482 #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK 483 484 485 #define GT_INTRCAUSE_MASABORT0_SHF 18 486 #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) 487 #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK 488 489 #define GT_INTRCAUSE_TARABORT0_SHF 19 490 #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) 491 #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK 492 493 494 #define GT_PCI0_CFGADDR_REGNUM_SHF 2 495 #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) 496 #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 497 #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) 498 #define GT_PCI0_CFGADDR_DEVNUM_SHF 11 499 #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) 500 #define GT_PCI0_CFGADDR_BUSNUM_SHF 16 501 #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) 502 #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 503 #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) 504 #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK 505 506 #define GT_PCI0_CMD_MBYTESWAP_SHF 0 507 #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) 508 #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK 509 #define GT_PCI0_CMD_MWORDSWAP_SHF 10 510 #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) 511 #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK 512 #define GT_PCI0_CMD_SBYTESWAP_SHF 16 513 #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) 514 #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK 515 #define GT_PCI0_CMD_SWORDSWAP_SHF 11 516 #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) 517 #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK 518 519 #define GT_INTR_T0EXP_SHF 8 520 #define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF) 521 #define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK 522 #define GT_INTR_RETRYCTR0_SHF 20 523 #define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF) 524 #define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK 525 526 /* 527 * Misc 528 */ 529 #define GT_DEF_PCI0_IO_BASE 0x10000000 530 #define GT_DEF_PCI0_IO_SIZE 0x02000000 531 #define GT_DEF_PCI0_MEM0_BASE 0x12000000 532 #define GT_DEF_PCI0_MEM0_SIZE 0x02000000 533 #define GT_DEF_BASE 0x14000000 534 535 #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ 536 #define GT_LATTIM_MIN 6 /* Minimum lat */ 537 538 #endif /* _ASM_GT64120_H */ 539