1 /* 2 * (C) Copyright 2010 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef __GDSYS_FPGA_H 25 #define __GDSYS_FPGA_H 26 27 enum { 28 FPGA_STATE_DONE_FAILED = 1 << 0, 29 FPGA_STATE_REFLECTION_FAILED = 1 << 1, 30 }; 31 32 int get_fpga_state(unsigned dev); 33 void print_fpga_state(unsigned dev); 34 35 typedef struct ihs_gpio { 36 u16 read; 37 u16 clear; 38 u16 set; 39 } ihs_gpio_t; 40 41 typedef struct ihs_i2c { 42 u16 write_mailbox; 43 u16 write_mailbox_ext; 44 u16 read_mailbox; 45 u16 read_mailbox_ext; 46 } ihs_i2c_t; 47 48 typedef struct ihs_osd { 49 u16 version; 50 u16 features; 51 u16 control; 52 u16 xy_size; 53 u16 xy_scale; 54 u16 x_pos; 55 u16 y_pos; 56 } ihs_osd_t; 57 58 #ifdef CONFIG_IO 59 typedef struct ihs_fpga { 60 u16 reflection_low; /* 0x0000 */ 61 u16 versions; /* 0x0002 */ 62 u16 fpga_features; /* 0x0004 */ 63 u16 fpga_version; /* 0x0006 */ 64 u16 reserved_0[5]; /* 0x0008 */ 65 u16 quad_serdes_reset; /* 0x0012 */ 66 u16 reserved_1[8181]; /* 0x0014 */ 67 u16 reflection_high; /* 0x3ffe */ 68 } ihs_fpga_t; 69 #endif 70 71 #ifdef CONFIG_IOCON 72 typedef struct ihs_fpga { 73 u16 reflection_low; /* 0x0000 */ 74 u16 versions; /* 0x0002 */ 75 u16 fpga_version; /* 0x0004 */ 76 u16 fpga_features; /* 0x0006 */ 77 u16 reserved_0[6]; /* 0x0008 */ 78 ihs_gpio_t gpio; /* 0x0014 */ 79 u16 mpc3w_control; /* 0x001a */ 80 u16 reserved_1[19]; /* 0x001c */ 81 u16 videocontrol; /* 0x0042 */ 82 u16 reserved_2[93]; /* 0x0044 */ 83 u16 reflection_high; /* 0x00fe */ 84 ihs_osd_t osd; /* 0x0100 */ 85 u16 reserved_3[88]; /* 0x010e */ 86 u16 videomem; /* 0x0800 */ 87 } ihs_fpga_t; 88 #endif 89 90 #ifdef CONFIG_DLVISION_10G 91 typedef struct ihs_fpga { 92 u16 reflection_low; /* 0x0000 */ 93 u16 versions; /* 0x0002 */ 94 u16 fpga_version; /* 0x0004 */ 95 u16 fpga_features; /* 0x0006 */ 96 u16 reserved_0[10]; /* 0x0008 */ 97 u16 extended_interrupt; /* 0x001c */ 98 u16 reserved_1[9]; /* 0x001e */ 99 ihs_i2c_t i2c; /* 0x0030 */ 100 u16 reserved_2[16]; /* 0x0038 */ 101 u16 mpc3w_control; /* 0x0058 */ 102 u16 reserved_3[34]; /* 0x005a */ 103 u16 videocontrol; /* 0x009e */ 104 u16 reserved_4[176]; /* 0x00a0 */ 105 ihs_osd_t osd; /* 0x0200 */ 106 u16 reserved_5[761]; /* 0x020e */ 107 u16 videomem; /* 0x0800 */ 108 } ihs_fpga_t; 109 #endif 110 111 #endif 112