1 /* 2 * Freescale USB Controller 3 * 4 * Copyright 2013 Freescale Semiconductor, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _ASM_FSL_USB_H_ 10 #define _ASM_FSL_USB_H_ 11 12 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 13 struct ccsr_usb_port_ctrl { 14 u32 ctrl; 15 u32 drvvbuscfg; 16 u32 pwrfltcfg; 17 u32 sts; 18 u8 res_14[0xc]; 19 u32 bistcfg; 20 u32 biststs; 21 u32 abistcfg; 22 u32 abiststs; 23 u8 res_30[0x10]; 24 u32 xcvrprg; 25 u32 anaprg; 26 u32 anadrv; 27 u32 anasts; 28 }; 29 30 struct ccsr_usb_phy { 31 u32 id; 32 struct ccsr_usb_port_ctrl port1; 33 u8 res_50[0xc]; 34 u32 tvr; 35 u32 pllprg[4]; 36 u8 res_70[0x4]; 37 u32 anaccfg; 38 u32 dbg; 39 u8 res_7c[0x4]; 40 struct ccsr_usb_port_ctrl port2; 41 u8 res_dc[0x334]; 42 }; 43 44 #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) 45 #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) 46 #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) 47 #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0) 48 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) 49 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) 50 #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13) 51 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) 52 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) 53 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) 54 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) 55 #else 56 struct ccsr_usb_phy { 57 u8 res0[0x18]; 58 u32 usb_enable_override; 59 u8 res[0xe4]; 60 }; 61 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 62 #endif 63 64 #endif /*_ASM_FSL_USB_H_ */ 65