183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 29dee205dSramneek mehresh /* 39dee205dSramneek mehresh * Freescale USB Controller 49dee205dSramneek mehresh * 59dee205dSramneek mehresh * Copyright 2013 Freescale Semiconductor, Inc. 69dee205dSramneek mehresh */ 79dee205dSramneek mehresh 89dee205dSramneek mehresh #ifndef _ASM_FSL_USB_H_ 99dee205dSramneek mehresh #define _ASM_FSL_USB_H_ 109dee205dSramneek mehresh 119dee205dSramneek mehresh #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 129dee205dSramneek mehresh struct ccsr_usb_port_ctrl { 139dee205dSramneek mehresh u32 ctrl; 149dee205dSramneek mehresh u32 drvvbuscfg; 159dee205dSramneek mehresh u32 pwrfltcfg; 169dee205dSramneek mehresh u32 sts; 179dee205dSramneek mehresh u8 res_14[0xc]; 189dee205dSramneek mehresh u32 bistcfg; 199dee205dSramneek mehresh u32 biststs; 209dee205dSramneek mehresh u32 abistcfg; 219dee205dSramneek mehresh u32 abiststs; 229dee205dSramneek mehresh u8 res_30[0x10]; 239dee205dSramneek mehresh u32 xcvrprg; 249dee205dSramneek mehresh u32 anaprg; 259dee205dSramneek mehresh u32 anadrv; 269dee205dSramneek mehresh u32 anasts; 279dee205dSramneek mehresh }; 289dee205dSramneek mehresh 299dee205dSramneek mehresh struct ccsr_usb_phy { 309dee205dSramneek mehresh u32 id; 319dee205dSramneek mehresh struct ccsr_usb_port_ctrl port1; 329dee205dSramneek mehresh u8 res_50[0xc]; 339dee205dSramneek mehresh u32 tvr; 349dee205dSramneek mehresh u32 pllprg[4]; 359dee205dSramneek mehresh u8 res_70[0x4]; 369dee205dSramneek mehresh u32 anaccfg; 379dee205dSramneek mehresh u32 dbg; 389dee205dSramneek mehresh u8 res_7c[0x4]; 399dee205dSramneek mehresh struct ccsr_usb_port_ctrl port2; 409dee205dSramneek mehresh u8 res_dc[0x334]; 419dee205dSramneek mehresh }; 429dee205dSramneek mehresh 439dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) 449dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) 459dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) 469dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0) 479dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) 489dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) 499dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13) 50d1c561cdSNikhil Badola #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 51d1c561cdSNikhil Badola #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4) 52d1c561cdSNikhil Badola #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16) 53d1c561cdSNikhil Badola #define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20) 54d1c561cdSNikhil Badola #endif 559dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) 569dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) 579dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) 589dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) 599c641a87SSuresh Gupta #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7) 609c641a87SSuresh Gupta #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4) 619c641a87SSuresh Gupta 629c641a87SSuresh Gupta #define INC_DCNT_THRESHOLD_25MV (0 << 4) 639c641a87SSuresh Gupta #define INC_DCNT_THRESHOLD_50MV (1 << 4) 649c641a87SSuresh Gupta #define DEC_DCNT_THRESHOLD_25MV (2 << 4) 659c641a87SSuresh Gupta #define DEC_DCNT_THRESHOLD_50MV (3 << 4) 669dee205dSramneek mehresh #else 679dee205dSramneek mehresh struct ccsr_usb_phy { 689c641a87SSuresh Gupta u32 config1; 699c641a87SSuresh Gupta u32 config2; 709c641a87SSuresh Gupta u32 config3; 719c641a87SSuresh Gupta u32 config4; 729c641a87SSuresh Gupta u32 config5; 739c641a87SSuresh Gupta u32 status1; 749dee205dSramneek mehresh u32 usb_enable_override; 759dee205dSramneek mehresh u8 res[0xe4]; 769dee205dSramneek mehresh }; 779c641a87SSuresh Gupta #define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22) 789c641a87SSuresh Gupta #define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20) 799c641a87SSuresh Gupta #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13 809c641a87SSuresh Gupta #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16 819c641a87SSuresh Gupta #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0 829c641a87SSuresh Gupta #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3 839dee205dSramneek mehresh #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 849c641a87SSuresh Gupta #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07 859dee205dSramneek mehresh #endif 869dee205dSramneek mehresh 87c26c80a1SNikhil Badola /* USB Erratum Checking code */ 8892623672SSriram Dash #if defined(CONFIG_PPC) || defined(CONFIG_ARM) 8992623672SSriram Dash bool has_dual_phy(void); 90*4eaf7f52SChris Packham bool has_erratum_a005275(void); 9192623672SSriram Dash bool has_erratum_a006261(void); 9292623672SSriram Dash bool has_erratum_a007075(void); 9392623672SSriram Dash bool has_erratum_a007798(void); 9492623672SSriram Dash bool has_erratum_a007792(void); 9592623672SSriram Dash bool has_erratum_a005697(void); 9692623672SSriram Dash bool has_erratum_a004477(void); 97ef53b8c4SSriram Dash bool has_erratum_a008751(void); 984c043712SSriram Dash bool has_erratum_a010151(void); 99c26c80a1SNikhil Badola #endif 1009dee205dSramneek mehresh #endif /*_ASM_FSL_USB_H_ */ 101