xref: /openbmc/u-boot/include/fsl_sec.h (revision ff0960f9)
1 /*
2  * Common internal memory map for some Freescale SoCs
3  *
4  * Copyright 2014 Freescale Semiconductor, Inc.
5  *
6  */
7 
8 #ifndef __FSL_SEC_H
9 #define __FSL_SEC_H
10 
11 #include <common.h>
12 #include <asm/io.h>
13 
14 #ifdef CONFIG_SYS_FSL_SEC_LE
15 #define sec_in32(a)       in_le32(a)
16 #define sec_out32(a, v)   out_le32(a, v)
17 #define sec_in16(a)       in_le16(a)
18 #define sec_clrbits32     clrbits_le32
19 #define sec_setbits32     setbits_le32
20 #elif defined(CONFIG_SYS_FSL_SEC_BE)
21 #define sec_in32(a)       in_be32(a)
22 #define sec_out32(a, v)   out_be32(a, v)
23 #define sec_in16(a)       in_be16(a)
24 #define sec_clrbits32     clrbits_be32
25 #define sec_setbits32     setbits_be32
26 #else
27 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
28 #endif
29 
30 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
31 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
32 /* RNG4 TRNG test registers */
33 struct rng4tst {
34 #define RTMCTL_PRGM 0x00010000	/* 1 -> program mode, 0 -> run mode */
35 	u32 rtmctl;		/* misc. control register */
36 	u32 rtscmisc;		/* statistical check misc. register */
37 	u32 rtpkrrng;		/* poker range register */
38 #define RTSDCTL_ENT_DLY_MIN	1200
39 #define RTSDCTL_ENT_DLY_MAX	12800
40 	union {
41 		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
42 		u32 rtpkrsq;	/* PRGM=0: poker square calc. result register */
43 	};
44 #define RTSDCTL_ENT_DLY_SHIFT 16
45 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
46 	u32 rtsdctl;		/* seed control register */
47 	union {
48 		u32 rtsblim;	/* PRGM=1: sparse bit limit register */
49 		u32 rttotsam;	/* PRGM=0: total samples register */
50 	};
51 	u32 rtfreqmin;		/* frequency count min. limit register */
52 	union {
53 		u32 rtfreqmax;	/* PRGM=1: freq. count max. limit register */
54 		u32 rtfreqcnt;	/* PRGM=0: freq. count register */
55 	};
56 	u32 rsvd1[40];
57 #define RNG_STATE0_HANDLE_INSTANTIATED	0x00000001
58 	u32 rdsta;		/*RNG DRNG Status Register*/
59 	u32 rsvd2[15];
60 };
61 
62 typedef struct ccsr_sec {
63 	u32	res0;
64 	u32	mcfgr;		/* Master CFG Register */
65 	u8	res1[0x4];
66 	u32	scfgr;
67 	struct {
68 		u32	ms;	/* Job Ring LIODN Register, MS */
69 		u32	ls;	/* Job Ring LIODN Register, LS */
70 	} jrliodnr[4];
71 	u8	res2[0x2c];
72 	u32	jrstartr;	/* Job Ring Start Register */
73 	struct {
74 		u32	ms;	/* RTIC LIODN Register, MS */
75 		u32	ls;	/* RTIC LIODN Register, LS */
76 	} rticliodnr[4];
77 	u8	res3[0x1c];
78 	u32	decorr;		/* DECO Request Register */
79 	struct {
80 		u32	ms;	/* DECO LIODN Register, MS */
81 		u32	ls;	/* DECO LIODN Register, LS */
82 	} decoliodnr[8];
83 	u8	res4[0x40];
84 	u32	dar;		/* DECO Avail Register */
85 	u32	drr;		/* DECO Reset Register */
86 	u8	res5[0x4d8];
87 	struct rng4tst rng;	/* RNG Registers */
88 	u8	res11[0x8a0];
89 	u32	crnr_ms;	/* CHA Revision Number Register, MS */
90 	u32	crnr_ls;	/* CHA Revision Number Register, LS */
91 	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
92 	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
93 	u8	res6[0x10];
94 	u32	far_ms;		/* Fault Address Register, MS */
95 	u32	far_ls;		/* Fault Address Register, LS */
96 	u32	falr;		/* Fault Address LIODN Register */
97 	u32	fadr;		/* Fault Address Detail Register */
98 	u8	res7[0x4];
99 	u32	csta;		/* CAAM Status Register */
100 	u8	res8[0x8];
101 	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
102 	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
103 	u32	chavid_ms;	/* CHA Version ID Register, MS */
104 	u32	chavid_ls;	/* CHA Version ID Register, LS */
105 	u32	chanum_ms;	/* CHA Number Register, MS */
106 	u32	chanum_ls;	/* CHA Number Register, LS */
107 	u32	secvid_ms;	/* SEC Version ID Register, MS */
108 	u32	secvid_ls;	/* SEC Version ID Register, LS */
109 	u8	res9[0x6020];
110 	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
111 	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
112 	u8	res10[0x8fd8];
113 } ccsr_sec_t;
114 
115 #define SEC_CTPR_MS_AXI_LIODN		0x08000000
116 #define SEC_CTPR_MS_QI			0x02000000
117 #define SEC_CTPR_MS_VIRT_EN_INCL	0x00000001
118 #define SEC_CTPR_MS_VIRT_EN_POR		0x00000002
119 #define SEC_RVID_MA			0x0f000000
120 #define SEC_CHANUM_MS_JRNUM_MASK	0xf0000000
121 #define SEC_CHANUM_MS_JRNUM_SHIFT	28
122 #define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
123 #define SEC_CHANUM_MS_DECONUM_SHIFT	24
124 #define SEC_SECVID_MS_IPID_MASK	0xffff0000
125 #define SEC_SECVID_MS_IPID_SHIFT	16
126 #define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
127 #define SEC_SECVID_MS_MAJ_REV_SHIFT	8
128 #define SEC_CCBVID_ERA_MASK		0xff000000
129 #define SEC_CCBVID_ERA_SHIFT		24
130 #define SEC_SCFGR_RDBENABLE		0x00000400
131 #define SEC_SCFGR_VIRT_EN		0x00008000
132 #define SEC_CHAVID_LS_RNG_SHIFT		16
133 #define SEC_CHAVID_RNG_LS_MASK		0x000f0000
134 
135 #define CONFIG_JRSTARTR_JR0		0x00000001
136 
137 struct jr_regs {
138 #ifdef CONFIG_SYS_FSL_SEC_LE
139 	u32 irba_l;
140 	u32 irba_h;
141 #else
142 	u32 irba_h;
143 	u32 irba_l;
144 #endif
145 	u32 rsvd1;
146 	u32 irs;
147 	u32 rsvd2;
148 	u32 irsa;
149 	u32 rsvd3;
150 	u32 irja;
151 #ifdef CONFIG_SYS_FSL_SEC_LE
152 	u32 orba_l;
153 	u32 orba_h;
154 #else
155 	u32 orba_h;
156 	u32 orba_l;
157 #endif
158 	u32 rsvd4;
159 	u32 ors;
160 	u32 rsvd5;
161 	u32 orjr;
162 	u32 rsvd6;
163 	u32 orsf;
164 	u32 rsvd7;
165 	u32 jrsta;
166 	u32 rsvd8;
167 	u32 jrint;
168 	u32 jrcfg0;
169 	u32 jrcfg1;
170 	u32 rsvd9;
171 	u32 irri;
172 	u32 rsvd10;
173 	u32 orwi;
174 	u32 rsvd11;
175 	u32 jrcr;
176 };
177 
178 int sec_init(void);
179 #endif
180 
181 #endif /* __FSL_SEC_H */
182