1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __FSL_QBMAN_H__ 8 #define __FSL_QBMAN_H__ 9 void fdt_fixup_qportals(void *blob); 10 void fdt_fixup_bportals(void *blob); 11 void inhibit_portals(void __iomem *addr, int max_portals, 12 int arch_max_portals, int portal_cinh_size); 13 void setup_qbman_portals(void); 14 15 struct ccsr_qman { 16 #ifdef CONFIG_SYS_FSL_QMAN_V3 17 u8 res0[0x200]; 18 #else 19 struct { 20 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ 21 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ 22 u32 res; 23 u32 qcsp_dd_cfg; /* 0xc - SW Portal Dynamic Debug cfg */ 24 } qcsp[32]; 25 #endif 26 /* Not actually reserved, but irrelevant to u-boot */ 27 u8 res[0xbf8 - 0x200]; 28 u32 ip_rev_1; 29 u32 ip_rev_2; 30 u32 fqd_bare; /* FQD Extended Base Addr Register */ 31 u32 fqd_bar; /* FQD Base Addr Register */ 32 u8 res1[0x8]; 33 u32 fqd_ar; /* FQD Attributes Register */ 34 u8 res2[0xc]; 35 u32 pfdr_bare; /* PFDR Extended Base Addr Register */ 36 u32 pfdr_bar; /* PFDR Base Addr Register */ 37 u8 res3[0x8]; 38 u32 pfdr_ar; /* PFDR Attributes Register */ 39 u8 res4[0x4c]; 40 u32 qcsp_bare; /* QCSP Extended Base Addr Register */ 41 u32 qcsp_bar; /* QCSP Base Addr Register */ 42 u8 res5[0x78]; 43 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ 44 u32 srcidr; /* Source ID Register */ 45 u32 liodnr; /* LIODN Register */ 46 u8 res6[4]; 47 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ 48 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ 49 u8 res7[0x2e8]; 50 #ifdef CONFIG_SYS_FSL_QMAN_V3 51 struct { 52 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ 53 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ 54 u32 res; 55 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/ 56 } qcsp[50]; 57 #endif 58 }; 59 60 struct ccsr_bman { 61 /* Not actually reserved, but irrelevant to u-boot */ 62 u8 res[0xbf8]; 63 u32 ip_rev_1; 64 u32 ip_rev_2; 65 u32 fbpr_bare; /* FBPR Extended Base Addr Register */ 66 u32 fbpr_bar; /* FBPR Base Addr Register */ 67 u8 res1[0x8]; 68 u32 fbpr_ar; /* FBPR Attributes Register */ 69 u8 res2[0xf0]; 70 u32 srcidr; /* Source ID Register */ 71 u32 liodnr; /* LIODN Register */ 72 u8 res7[0x2f4]; 73 }; 74 75 #endif /* __FSL_QBMAN_H__ */ 76